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Changeset d65ed62 in rtems
- Timestamp:
- Oct 27, 2015, 1:39:47 PM (5 years ago)
- Branches:
- 5, master
- Children:
- 65243416
- Parents:
- 98df160
- git-author:
- Sebastian Huber <sebastian.huber@…> (10/27/15 13:39:47)
- git-committer:
- Sebastian Huber <sebastian.huber@…> (10/28/15 12:06:18)
- Location:
- c/src/lib/libbsp/powerpc/qoriq
- Files:
-
- 3 edited
-
include/irq.h (modified) (1 diff)
-
include/qoriq.h (modified) (1 diff)
-
irq/irq.c (modified) (7 diffs)
Legend:
- Unmodified
- Added
- Removed
-
c/src/lib/libbsp/powerpc/qoriq/include/irq.h
r98df160 rd65ed62 135 135 #define QORIQ_IRQ_DMA_CHANNEL_3_8 247 136 136 137 #define QORIQ_IRQ_EXT_BASE 128137 #define QORIQ_IRQ_EXT_BASE 256 138 138 139 139 #else /* QORIQ_CHIP_VARIANT */ -
c/src/lib/libbsp/powerpc/qoriq/include/qoriq.h
r98df160 rd65ed62 149 149 qoriq_pic_src_cfg ei [12]; 150 150 QORIQ_RESERVE(0x10180, 0x10200); 151 qoriq_pic_src_cfg ii [64]; 152 QORIQ_RESERVE(0x10a00, 0x11600); 151 qoriq_pic_src_cfg ii_0 [160]; 153 152 qoriq_pic_src_cfg mi [8]; 154 153 QORIQ_RESERVE(0x11700, 0x11c00); 155 154 qoriq_pic_src_cfg msi [8]; 156 QORIQ_RESERVE(0x11d00, 0x20000); 155 QORIQ_RESERVE(0x11d00, 0x13000); 156 qoriq_pic_src_cfg ii_1 [96]; 157 QORIQ_RESERVE(0x13c00, 0x20000); 157 158 qoriq_pic_per_cpu per_cpu [2]; 158 159 } qoriq_pic; -
c/src/lib/libbsp/powerpc/qoriq/irq/irq.c
r98df160 rd65ed62 20 20 * http://www.rtems.org/license/LICENSE. 21 21 */ 22 23 #include <sys/param.h> 22 24 23 25 #include <rtems.h> … … 50 52 RTEMS_INTERRUPT_LOCK_DEFINE(static, lock, "QorIQ IRQ") 51 53 52 static const uint16_t vpr_and_dr_offsets [] = { 53 [0] = 0x10200 >> 4, 54 [1] = 0x10220 >> 4, 55 [2] = 0x10240 >> 4, 56 [3] = 0x10260 >> 4, 57 [4] = 0x10280 >> 4, 58 [5] = 0x102a0 >> 4, 59 [6] = 0x102c0 >> 4, 60 [7] = 0x102e0 >> 4, 61 [8] = 0x10300 >> 4, 62 [9] = 0x10320 >> 4, 63 [10] = 0x10340 >> 4, 64 [11] = 0x10360 >> 4, 65 [12] = 0x10380 >> 4, 66 [13] = 0x103a0 >> 4, 67 [14] = 0x103c0 >> 4, 68 [15] = 0x103e0 >> 4, 69 [16] = 0x10400 >> 4, 70 [17] = 0x10420 >> 4, 71 [18] = 0x10440 >> 4, 72 [19] = 0x10460 >> 4, 73 [20] = 0x10480 >> 4, 74 [21] = 0x104a0 >> 4, 75 [22] = 0x104c0 >> 4, 76 [23] = 0x104e0 >> 4, 77 [24] = 0x10500 >> 4, 78 [25] = 0x10520 >> 4, 79 [26] = 0x10540 >> 4, 80 [27] = 0x10560 >> 4, 81 [28] = 0x10580 >> 4, 82 [29] = 0x105a0 >> 4, 83 [30] = 0x105c0 >> 4, 84 [31] = 0x105e0 >> 4, 85 [32] = 0x10600 >> 4, 86 [33] = 0x10620 >> 4, 87 [34] = 0x10640 >> 4, 88 [35] = 0x10660 >> 4, 89 [36] = 0x10680 >> 4, 90 [37] = 0x106a0 >> 4, 91 [38] = 0x106c0 >> 4, 92 [39] = 0x106e0 >> 4, 93 [40] = 0x10700 >> 4, 94 [41] = 0x10720 >> 4, 95 [42] = 0x10740 >> 4, 96 [43] = 0x10760 >> 4, 97 [44] = 0x10780 >> 4, 98 [45] = 0x107a0 >> 4, 99 [46] = 0x107c0 >> 4, 100 [47] = 0x107e0 >> 4, 101 [48] = 0x10800 >> 4, 102 [49] = 0x10820 >> 4, 103 [50] = 0x10840 >> 4, 104 [51] = 0x10860 >> 4, 105 [52] = 0x10880 >> 4, 106 [53] = 0x108a0 >> 4, 107 [54] = 0x108c0 >> 4, 108 [55] = 0x108e0 >> 4, 109 [56] = 0x10900 >> 4, 110 [57] = 0x10920 >> 4, 111 [58] = 0x10940 >> 4, 112 [59] = 0x10960 >> 4, 113 [60] = 0x10980 >> 4, 114 [61] = 0x109a0 >> 4, 115 [62] = 0x109c0 >> 4, 116 [63] = 0x109e0 >> 4, 117 [QORIQ_IRQ_EXT_0] = 0x10000 >> 4, 118 [QORIQ_IRQ_EXT_1] = 0x10020 >> 4, 119 [QORIQ_IRQ_EXT_2] = 0x10040 >> 4, 120 [QORIQ_IRQ_EXT_3] = 0x10060 >> 4, 121 [QORIQ_IRQ_EXT_4] = 0x10080 >> 4, 122 [QORIQ_IRQ_EXT_5] = 0x100a0 >> 4, 123 [QORIQ_IRQ_EXT_6] = 0x100c0 >> 4, 124 [QORIQ_IRQ_EXT_7] = 0x100e0 >> 4, 125 [QORIQ_IRQ_EXT_8] = 0x10100 >> 4, 126 [QORIQ_IRQ_EXT_9] = 0x10120 >> 4, 127 [QORIQ_IRQ_EXT_10] = 0x10140 >> 4, 128 [QORIQ_IRQ_EXT_11] = 0x10160 >> 4, 129 [QORIQ_IRQ_IPI_0] = 0x010a0 >> 4, 130 [QORIQ_IRQ_IPI_1] = 0x010b0 >> 4, 131 [QORIQ_IRQ_IPI_2] = 0x010c0 >> 4, 132 [QORIQ_IRQ_IPI_3] = 0x010d0 >> 4, 133 [QORIQ_IRQ_MI_0] = 0x11600 >> 4, 134 [QORIQ_IRQ_MI_1] = 0x11620 >> 4, 135 [QORIQ_IRQ_MI_2] = 0x11640 >> 4, 136 [QORIQ_IRQ_MI_3] = 0x11660 >> 4, 137 [QORIQ_IRQ_MI_4] = 0x11680 >> 4, 138 [QORIQ_IRQ_MI_5] = 0x116a0 >> 4, 139 [QORIQ_IRQ_MI_6] = 0x116c0 >> 4, 140 [QORIQ_IRQ_MI_7] = 0x116e0 >> 4, 141 [QORIQ_IRQ_MSI_0] = 0x11c00 >> 4, 142 [QORIQ_IRQ_MSI_1] = 0x11c20 >> 4, 143 [QORIQ_IRQ_MSI_2] = 0x11c40 >> 4, 144 [QORIQ_IRQ_MSI_3] = 0x11c60 >> 4, 145 [QORIQ_IRQ_MSI_4] = 0x11c80 >> 4, 146 [QORIQ_IRQ_MSI_5] = 0x11ca0 >> 4, 147 [QORIQ_IRQ_MSI_6] = 0x11cc0 >> 4, 148 [QORIQ_IRQ_MSI_7] = 0x11ce0 >> 4, 149 [QORIQ_IRQ_GT_A_0] = 0x01120 >> 4, 150 [QORIQ_IRQ_GT_A_1] = 0x01160 >> 4, 151 [QORIQ_IRQ_GT_A_2] = 0x011a0 >> 4, 152 [QORIQ_IRQ_GT_A_3] = 0x011e0 >> 4, 153 [QORIQ_IRQ_GT_B_0] = 0x02120 >> 4, 154 [QORIQ_IRQ_GT_B_1] = 0x02160 >> 4, 155 [QORIQ_IRQ_GT_B_2] = 0x021a0 >> 4, 156 [QORIQ_IRQ_GT_B_3] = 0x021e0 >> 4 54 #define SRC_CFG_IDX(i) ((i) - QORIQ_IRQ_EXT_BASE) 55 56 static const uint16_t src_cfg_offsets [] = { 57 [SRC_CFG_IDX(QORIQ_IRQ_EXT_0)] = 0x10000 >> 4, 58 [SRC_CFG_IDX(QORIQ_IRQ_EXT_1)] = 0x10020 >> 4, 59 [SRC_CFG_IDX(QORIQ_IRQ_EXT_2)] = 0x10040 >> 4, 60 [SRC_CFG_IDX(QORIQ_IRQ_EXT_3)] = 0x10060 >> 4, 61 [SRC_CFG_IDX(QORIQ_IRQ_EXT_4)] = 0x10080 >> 4, 62 [SRC_CFG_IDX(QORIQ_IRQ_EXT_5)] = 0x100a0 >> 4, 63 [SRC_CFG_IDX(QORIQ_IRQ_EXT_6)] = 0x100c0 >> 4, 64 [SRC_CFG_IDX(QORIQ_IRQ_EXT_7)] = 0x100e0 >> 4, 65 [SRC_CFG_IDX(QORIQ_IRQ_EXT_8)] = 0x10100 >> 4, 66 [SRC_CFG_IDX(QORIQ_IRQ_EXT_9)] = 0x10120 >> 4, 67 [SRC_CFG_IDX(QORIQ_IRQ_EXT_10)] = 0x10140 >> 4, 68 [SRC_CFG_IDX(QORIQ_IRQ_EXT_11)] = 0x10160 >> 4, 69 [SRC_CFG_IDX(QORIQ_IRQ_IPI_0)] = 0x010a0 >> 4, 70 [SRC_CFG_IDX(QORIQ_IRQ_IPI_1)] = 0x010b0 >> 4, 71 [SRC_CFG_IDX(QORIQ_IRQ_IPI_2)] = 0x010c0 >> 4, 72 [SRC_CFG_IDX(QORIQ_IRQ_IPI_3)] = 0x010d0 >> 4, 73 [SRC_CFG_IDX(QORIQ_IRQ_MI_0)] = 0x11600 >> 4, 74 [SRC_CFG_IDX(QORIQ_IRQ_MI_1)] = 0x11620 >> 4, 75 [SRC_CFG_IDX(QORIQ_IRQ_MI_2)] = 0x11640 >> 4, 76 [SRC_CFG_IDX(QORIQ_IRQ_MI_3)] = 0x11660 >> 4, 77 [SRC_CFG_IDX(QORIQ_IRQ_MI_4)] = 0x11680 >> 4, 78 [SRC_CFG_IDX(QORIQ_IRQ_MI_5)] = 0x116a0 >> 4, 79 [SRC_CFG_IDX(QORIQ_IRQ_MI_6)] = 0x116c0 >> 4, 80 [SRC_CFG_IDX(QORIQ_IRQ_MI_7)] = 0x116e0 >> 4, 81 [SRC_CFG_IDX(QORIQ_IRQ_MSI_0)] = 0x11c00 >> 4, 82 [SRC_CFG_IDX(QORIQ_IRQ_MSI_1)] = 0x11c20 >> 4, 83 [SRC_CFG_IDX(QORIQ_IRQ_MSI_2)] = 0x11c40 >> 4, 84 [SRC_CFG_IDX(QORIQ_IRQ_MSI_3)] = 0x11c60 >> 4, 85 [SRC_CFG_IDX(QORIQ_IRQ_MSI_4)] = 0x11c80 >> 4, 86 [SRC_CFG_IDX(QORIQ_IRQ_MSI_5)] = 0x11ca0 >> 4, 87 [SRC_CFG_IDX(QORIQ_IRQ_MSI_6)] = 0x11cc0 >> 4, 88 [SRC_CFG_IDX(QORIQ_IRQ_MSI_7)] = 0x11ce0 >> 4, 89 [SRC_CFG_IDX(QORIQ_IRQ_GT_A_0)] = 0x01120 >> 4, 90 [SRC_CFG_IDX(QORIQ_IRQ_GT_A_1)] = 0x01160 >> 4, 91 [SRC_CFG_IDX(QORIQ_IRQ_GT_A_2)] = 0x011a0 >> 4, 92 [SRC_CFG_IDX(QORIQ_IRQ_GT_A_3)] = 0x011e0 >> 4, 93 [SRC_CFG_IDX(QORIQ_IRQ_GT_B_0)] = 0x02120 >> 4, 94 [SRC_CFG_IDX(QORIQ_IRQ_GT_B_1)] = 0x02160 >> 4, 95 [SRC_CFG_IDX(QORIQ_IRQ_GT_B_2)] = 0x021a0 >> 4, 96 [SRC_CFG_IDX(QORIQ_IRQ_GT_B_3)] = 0x021e0 >> 4 157 97 }; 98 99 static volatile qoriq_pic_src_cfg *get_src_cfg(rtems_vector_number vector) 100 { 101 uint32_t n = MIN(RTEMS_ARRAY_SIZE(qoriq.pic.ii_0), QORIQ_IRQ_EXT_BASE); 102 103 if (vector < n) { 104 return &qoriq.pic.ii_0 [vector]; 105 } else if (vector < QORIQ_IRQ_EXT_BASE) { 106 return &qoriq.pic.ii_1 [vector - n]; 107 } else { 108 uint32_t offs = ((uint32_t) 109 src_cfg_offsets [vector - QORIQ_IRQ_EXT_BASE]) << 4; 110 111 return (volatile qoriq_pic_src_cfg *) ((uint32_t) &qoriq.pic + offs); 112 } 113 } 158 114 159 115 rtems_status_code qoriq_pic_set_priority( … … 167 123 168 124 if (bsp_interrupt_is_valid_vector(vector)) { 169 int offs = vpr_and_dr_offsets [vector] << 2; 170 volatile uint32_t *vpr = (volatile uint32_t *) &qoriq.pic + offs; 125 volatile qoriq_pic_src_cfg *src_cfg = get_src_cfg(vector); 171 126 172 127 if (QORIQ_PIC_PRIORITY_IS_VALID(new_priority)) { … … 174 129 175 130 rtems_interrupt_lock_acquire(&lock, &lock_context); 176 old_vpr = *vpr;177 *vpr = VPR_PRIORITY_SET(old_vpr, (uint32_t) new_priority);131 old_vpr = src_cfg->vpr; 132 src_cfg->vpr = VPR_PRIORITY_SET(old_vpr, (uint32_t) new_priority); 178 133 rtems_interrupt_lock_release(&lock, &lock_context); 179 134 } else if (new_priority < 0) { 180 old_vpr = *vpr;135 old_vpr = src_cfg->vpr; 181 136 } else { 182 137 sc = RTEMS_INVALID_PRIORITY; … … 202 157 if (bsp_interrupt_is_valid_vector(vector)) { 203 158 if (processor_index <= 1) { 204 int offs = (vpr_and_dr_offsets [vector] << 2) + 4; 205 volatile uint32_t *dr = (volatile uint32_t *) &qoriq.pic + offs; 206 207 *dr = BSP_BIT32(processor_index); 159 volatile qoriq_pic_src_cfg *src_cfg = get_src_cfg(vector); 160 161 src_cfg->dr = BSP_BIT32(processor_index); 208 162 } else { 209 163 sc = RTEMS_INVALID_NUMBER; … … 221 175 222 176 if (bsp_interrupt_is_valid_vector(vector)) { 223 int offs = vpr_and_dr_offsets [vector] << 2; 224 volatile uint32_t *vpr = (volatile uint32_t *) &qoriq.pic + offs; 177 volatile qoriq_pic_src_cfg *src_cfg = get_src_cfg(vector); 225 178 rtems_interrupt_lock_context lock_context; 226 179 227 180 rtems_interrupt_lock_acquire(&lock, &lock_context); 228 *vpr = (*vpr & ~VPR_MSK) | msk;181 src_cfg->vpr = (src_cfg->vpr & ~VPR_MSK) | msk; 229 182 rtems_interrupt_lock_release(&lock, &lock_context); 230 183 } … … 318 271 319 272 for (i = BSP_INTERRUPT_VECTOR_MIN; i <= BSP_INTERRUPT_VECTOR_MAX; ++i) { 320 volatile uint32_t *base = (volatile uint32_t *) &qoriq.pic; 321 int offs = vpr_and_dr_offsets [i] << 2; 322 volatile uint32_t *vpr = base + offs; 323 324 *vpr = VPR_MSK | VPR_P | VPR_PRIORITY(1) | VPR_VECTOR(i); 273 volatile qoriq_pic_src_cfg *src_cfg = get_src_cfg(i); 274 275 src_cfg->vpr = VPR_MSK | VPR_P | VPR_PRIORITY(1) | VPR_VECTOR(i); 325 276 326 277 if (!pic_is_ipi(i)) { 327 volatile uint32_t *dr = base + offs + 4; 328 329 *dr = 0x1; 278 src_cfg->dr = 0x1; 330 279 } 331 280 }
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