Changeset d5fe91e in rtems
- Timestamp:
- 04/19/05 20:50:45 (19 years ago)
- Branches:
- 4.10, 4.11, 4.8, 4.9, 5, master
- Children:
- b17dd93
- Parents:
- c163605f
- Location:
- c/src/lib/libbsp/m68k/uC5282
- Files:
-
- 2 edited
Legend:
- Unmodified
- Added
- Removed
-
c/src/lib/libbsp/m68k/uC5282/ChangeLog
rc163605f rd5fe91e 1 2005-04-19 Eric Norum <norume@aps.anl.gov> 2 3 * startup/bspstart.c: Expose read/write copy of cache control registers 4 in case some application diagnostic code wants to 5 display the values. 6 1 7 2005-04-13 Eric Norum <norume@aps.anl.gov> 2 8 -
c/src/lib/libbsp/m68k/uC5282/startup/bspstart.c
rc163605f rd5fe91e 75 75 76 76 /* 77 * Read/write copy of c ommon cache77 * Read/write copy of cache registers 78 78 * Split I/D cache 79 79 * Allow CPUSHL to invalidate a cache line … … 82 82 * Default cache mode is *disabled* (cache only ACRx areas) 83 83 */ 84 static uint32_t cacr_mode = MCF5XXX_CACR_CENB | 85 MCF5XXX_CACR_DBWE | 86 MCF5XXX_CACR_DCM; 84 uint32_t mcf5282_cacr_mode = MCF5XXX_CACR_CENB | 85 MCF5XXX_CACR_DBWE | 86 MCF5XXX_CACR_DCM; 87 uint32_t mcf5282_acr0_mode = 0; 88 uint32_t mcf5282_acr1_mode = 0; 87 89 /* 88 90 * Cannot be frozen … … 104 106 105 107 rtems_interrupt_disable(level); 106 cacr_mode &= ~MCF5XXX_CACR_DIDI;107 m68k_set_cacr( cacr_mode);108 mcf5282_cacr_mode &= ~MCF5XXX_CACR_DIDI; 109 m68k_set_cacr(mcf5282_cacr_mode); 108 110 rtems_interrupt_enable(level); 109 111 } … … 114 116 115 117 rtems_interrupt_disable(level); 116 cacr_mode |= MCF5XXX_CACR_DIDI;117 m68k_set_cacr( cacr_mode);118 mcf5282_cacr_mode |= MCF5XXX_CACR_DIDI; 119 m68k_set_cacr(mcf5282_cacr_mode); 118 120 rtems_interrupt_enable(level); 119 121 } … … 121 123 void _CPU_cache_invalidate_entire_instruction(void) 122 124 { 123 m68k_set_cacr( cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVI);125 m68k_set_cacr(mcf5282_cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVI); 124 126 } 125 127 … … 138 140 139 141 rtems_interrupt_disable(level); 140 cacr_mode &= ~MCF5XXX_CACR_DISD;141 m68k_set_cacr( cacr_mode);142 mcf5282_cacr_mode &= ~MCF5XXX_CACR_DISD; 143 m68k_set_cacr(mcf5282_cacr_mode); 142 144 rtems_interrupt_enable(level); 143 145 } … … 149 151 rtems_interrupt_disable(level); 150 152 rtems_interrupt_disable(level); 151 cacr_mode |= MCF5XXX_CACR_DISD;152 m68k_set_cacr( cacr_mode);153 mcf5282_cacr_mode |= MCF5XXX_CACR_DISD; 154 m68k_set_cacr(mcf5282_cacr_mode); 153 155 rtems_interrupt_enable(level); 154 156 } … … 156 158 void _CPU_cache_invalidate_entire_data(void) 157 159 { 158 m68k_set_cacr( cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVD);160 m68k_set_cacr(mcf5282_cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVD); 159 161 } 160 162 … … 217 219 * Invalidate the cache and disable it 218 220 */ 219 m68k_set_acr0( 0);220 m68k_set_acr1( 0);221 m68k_set_acr0(mcf5282_acr0_mode); 222 m68k_set_acr1(mcf5282_acr1_mode); 221 223 m68k_set_cacr(MCF5XXX_CACR_CINV); 222 224 … … 224 226 * Cache SDRAM 225 227 */ 226 m68k_set_acr0(MCF5XXX_ACR_AB((uint32_t)_RamBase) | 227 MCF5XXX_ACR_AM((uint32_t)_RamSize-1) | 228 MCF5XXX_ACR_EN | 229 MCF5XXX_ACR_BWE | 230 MCF5XXX_ACR_SM_IGNORE); 228 mcf5282_acr0_mode = MCF5XXX_ACR_AB((uint32_t)_RamBase) | 229 MCF5XXX_ACR_AM((uint32_t)_RamSize-1) | 230 MCF5XXX_ACR_EN | 231 MCF5XXX_ACR_BWE | 232 MCF5XXX_ACR_SM_IGNORE; 233 m68k_set_acr0(mcf5282_acr0_mode); 231 234 232 235 /* 233 236 * Enable the cache 234 237 */ 235 m68k_set_cacr( cacr_mode);238 m68k_set_cacr(mcf5282_cacr_mode); 236 239 237 240 /*
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