Changeset d5fa273e in rtems
- Timestamp:
- 07/23/03 18:07:04 (20 years ago)
- Children:
- c213219
- Parents:
- 36e95a87
- Location:
- c/src/lib/libbsp/powerpc
- Files:
-
- 2 edited
Legend:
- Unmodified
- Added
- Removed
-
c/src/lib/libbsp/powerpc/ChangeLog
r36e95a87 rd5fa273e 1 2003-07-18 Till Straumann <strauman@slac.stanford.edu> 2 3 PR 288/rtems 4 * support/new_exception_processing/cpu.c: _ISR_Nest_level is now 5 properly maintained and does not reside in SPRG0. 6 1 7 2003-03-06 Ralf Corsepius <corsepiu@faw.uni-ulm.de> 2 8 -
c/src/lib/libbsp/powerpc/support/new_exception_processing/cpu.c
r36e95a87 rd5fa273e 51 51 { 52 52 _CPU_Table = *cpu_table; 53 54 { unsigned hasFixed = 0; 55 /* assert that our BSP has fixed PR288 */ 56 __asm__ __volatile__ ("mfspr %0, %2":"=r"(hasFixed):"0"(hasFixed),"i"(SPRG0)); 57 if ( PPC_BSP_HAS_FIXED_PR288 != hasFixed ) { 58 BSP_panic("This BSP needs to fix PR#288"); 59 } 60 } 53 61 } 54 62 … … 144 152 } 145 153 146 /*PAGE147 *148 * This is the PowerPC specific implementation of the routine which149 * returns TRUE if an interrupt is in progress.150 */151 152 boolean _ISR_Is_in_progress( void )153 {154 /*155 * Until the patch on PR288 is in all new exception BSPs, this is156 * the safest thing to do.157 */158 #ifdef mpc8260159 return (_ISR_Nest_level != 0);160 #else161 register unsigned int isr_nesting_level;162 /*163 * Move from special purpose register 0 (mfspr SPRG0, r3)164 */165 asm volatile ("mfspr %0, 272" : "=r" (isr_nesting_level));166 return isr_nesting_level;167 #endif168 }169
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