Changeset d5587f9f in rtems


Ignore:
Timestamp:
Apr 17, 2013, 2:03:03 PM (6 years ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
4.11, master
Children:
740abbd
Parents:
47fb2fe
git-author:
Sebastian Huber <sebastian.huber@…> (04/17/13 14:03:03)
git-committer:
Sebastian Huber <sebastian.huber@…> (04/23/13 07:59:55)
Message:

bsp/mpc5200: Fix cache handling

Location:
c/src/lib/libbsp/powerpc/gen5200/startup
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/powerpc/gen5200/startup/bspstart.c

    r47fb2fe rd5587f9f  
    166166  bsp_clicks_per_usec    = (XLB_CLOCK/4000000);
    167167
    168   /*
    169    * Enable instruction and data caches. Do not force writethrough mode.
    170    */
    171   #if BSP_INSTRUCTION_CACHE_ENABLED
    172     rtems_cache_enable_instruction();
    173   #endif
    174   #if BSP_DATA_CACHE_ENABLED
    175     rtems_cache_enable_data();
    176   #endif
    177 
    178168  /* Initialize exception handler */
    179169  ppc_exc_cache_wb_check = 0;
  • c/src/lib/libbsp/powerpc/gen5200/startup/cpuinit.c

    r47fb2fe rd5587f9f  
    291291  uint32_t msr;
    292292
    293   /* Enable instruction cache */
    294   PPC_SET_SPECIAL_PURPOSE_REGISTER_BITS( HID0, HID0_ICE);
     293  #if BSP_INSTRUCTION_CACHE_ENABLED
     294    rtems_cache_enable_instruction();
     295  #endif
    295296
    296297  /* Set up DBAT registers in MMU */
     
    312313  ppc_set_machine_state_register( msr);
    313314
    314   /*
    315    * Enable data cache.
    316    *
    317    * NOTE: TRACE32 now supports data cache for MGT5x00.
    318    */
    319   PPC_SET_SPECIAL_PURPOSE_REGISTER_BITS( HID0, HID0_DCE);
     315  #if BSP_DATA_CACHE_ENABLED
     316    rtems_cache_enable_data();
     317  #endif
    320318}
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