Changeset d53de34 in rtems
- Timestamp:
- 11/19/14 13:08:44 (9 years ago)
- Branches:
- 4.11, 5, master
- Children:
- 55741886
- Parents:
- 861d315
- git-author:
- Sebastian Huber <sebastian.huber@…> (11/19/14 13:08:44)
- git-committer:
- Sebastian Huber <sebastian.huber@…> (11/20/14 09:30:27)
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h
r861d315 rd53de34 99 99 L2C_310_RTL_RELEASE_R3_P2 = 0x8, 100 100 L2C_310_RTL_RELEASE_R3_P3 = 0x9 101 } cache_l2c_310_rtl_release;101 } l2c_310_rtl_release; 102 102 103 103 /** … … 464 464 } L2CC; 465 465 466 rtems_interrupt_lock l2c_310_ cache_lock = RTEMS_INTERRUPT_LOCK_INITIALIZER(466 rtems_interrupt_lock l2c_310_lock = RTEMS_INTERRUPT_LOCK_INITIALIZER( 467 467 "cache" 468 468 ); … … 478 478 * r3 releases Software Developers Errata Notice" 479 479 * Please see this document for more information on these erratas */ 480 static bool l2c_310_ cache_errata_is_applicable_753970(481 cache_l2c_310_rtl_release rtl_release480 static bool l2c_310_errata_is_applicable_753970( 481 l2c_310_rtl_release rtl_release 482 482 ) 483 483 { … … 504 504 } 505 505 506 static bool l2c_310_ cache_errata_is_applicable_727913(507 cache_l2c_310_rtl_release rtl_release506 static bool l2c_310_errata_is_applicable_727913( 507 l2c_310_rtl_release rtl_release 508 508 ) 509 509 { … … 530 530 } 531 531 532 static bool l2c_310_ cache_errata_is_applicable_727914(533 cache_l2c_310_rtl_release rtl_release532 static bool l2c_310_errata_is_applicable_727914( 533 l2c_310_rtl_release rtl_release 534 534 ) 535 535 { … … 556 556 } 557 557 558 static bool l2c_310_ cache_errata_is_applicable_727915(559 cache_l2c_310_rtl_release rtl_release558 static bool l2c_310_errata_is_applicable_727915( 559 l2c_310_rtl_release rtl_release 560 560 ) 561 561 { … … 582 582 } 583 583 584 static bool l2c_310_ cache_errata_is_applicable_729806(585 cache_l2c_310_rtl_release rtl_release584 static bool l2c_310_errata_is_applicable_729806( 585 l2c_310_rtl_release rtl_release 586 586 ) 587 587 { … … 608 608 } 609 609 610 static bool l2c_310_ cache_errata_is_applicable_729815(611 cache_l2c_310_rtl_release rtl_release610 static bool l2c_310_errata_is_applicable_729815( 611 l2c_310_rtl_release rtl_release 612 612 ) 613 613 { … … 634 634 } 635 635 636 static bool l2c_310_ cache_errata_is_applicable_742884(637 cache_l2c_310_rtl_release rtl_release636 static bool l2c_310_errata_is_applicable_742884( 637 l2c_310_rtl_release rtl_release 638 638 ) 639 639 { … … 660 660 } 661 661 662 static bool l2c_310_ cache_errata_is_applicable_752271(663 cache_l2c_310_rtl_release rtl_release662 static bool l2c_310_errata_is_applicable_752271( 663 l2c_310_rtl_release rtl_release 664 664 ) 665 665 { … … 686 686 } 687 687 688 static bool l2c_310_ cache_errata_is_applicable_765569(689 cache_l2c_310_rtl_release rtl_release688 static bool l2c_310_errata_is_applicable_765569( 689 l2c_310_rtl_release rtl_release 690 690 ) 691 691 { … … 710 710 } 711 711 712 static bool l2c_310_ cache_errata_is_applicable_769419(713 cache_l2c_310_rtl_release rtl_release712 static bool l2c_310_errata_is_applicable_769419( 713 l2c_310_rtl_release rtl_release 714 714 ) 715 715 { … … 736 736 } 737 737 738 static bool l2c_310_ cache_errata_is_applicable_588369(739 cache_l2c_310_rtl_release rtl_release738 static bool l2c_310_errata_is_applicable_588369( 739 l2c_310_rtl_release rtl_release 740 740 ) 741 741 { … … 763 763 764 764 #ifdef CACHE_ERRATA_CHECKS_FOR_IMPLEMENTED_ERRATAS 765 static bool l2c_310_ cache_errata_is_applicable_754670(766 cache_l2c_310_rtl_release rtl_release765 static bool l2c_310_errata_is_applicable_754670( 766 l2c_310_rtl_release rtl_release 767 767 ) 768 768 { … … 796 796 } \ 797 797 798 static void l2c_310_c ache_check_errata( cache_l2c_310_rtl_release rtl_release )798 static void l2c_310_check_errata( l2c_310_rtl_release rtl_release ) 799 799 { 800 800 /* This erratum gets handled within the sources */ … … 802 802 * keep the cache line if it was clean. See ARMs documentation on the erratum 803 803 * for a workaround */ 804 /* assert( ! l2c_310_ cache_errata_is_applicable_588369( rtl_release ) ); */804 /* assert( ! l2c_310_errata_is_applicable_588369( rtl_release ) ); */ 805 805 806 806 /* Unhandled erratum present: 727913 Prefetch dropping feature can cause 807 807 * incorrect behavior when PL310 handles reads that cross cache line 808 808 * boundary */ 809 assert( ! l2c_310_ cache_errata_is_applicable_727913( rtl_release ) );809 assert( ! l2c_310_errata_is_applicable_727913( rtl_release ) ); 810 810 811 811 /* Unhandled erratum present: 727914 Double linefill feature can cause 812 812 * deadlock */ 813 assert( ! l2c_310_ cache_errata_is_applicable_727914( rtl_release ) );813 assert( ! l2c_310_errata_is_applicable_727914( rtl_release ) ); 814 814 815 815 /* Unhandled erratum present: 727915 Background Clean and Invalidate by Way 816 816 * operation can cause data corruption */ 817 assert( ! l2c_310_ cache_errata_is_applicable_727915( rtl_release ) );817 assert( ! l2c_310_errata_is_applicable_727915( rtl_release ) ); 818 818 819 819 /* Unhandled erratum present: 729806 Speculative reads from the Cortex-A9 820 820 * MPCore processor can cause deadlock */ 821 assert( ! l2c_310_ cache_errata_is_applicable_729806( rtl_release ) );822 823 if( l2c_310_ cache_errata_is_applicable_729815( rtl_release ) )821 assert( ! l2c_310_errata_is_applicable_729806( rtl_release ) ); 822 823 if( l2c_310_errata_is_applicable_729815( rtl_release ) ) 824 824 { 825 825 volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE; … … 846 846 /* Unhandled erratum present: 742884 Double linefill feature might introduce 847 847 * circular dependency and deadlock */ 848 assert( ! l2c_310_ cache_errata_is_applicable_742884( rtl_release ) );848 assert( ! l2c_310_errata_is_applicable_742884( rtl_release ) ); 849 849 850 850 /* Unhandled erratum present: 752271 Double linefill feature can cause data 851 851 * corruption */ 852 assert( ! l2c_310_ cache_errata_is_applicable_752271( rtl_release ) );852 assert( ! l2c_310_errata_is_applicable_752271( rtl_release ) ); 853 853 854 854 /* This erratum can not be worked around: 754670 A continuous write flow can 855 855 * stall a read targeting the same memory area 856 856 * But this erratum does not lead to any data corruption */ 857 /* assert( ! l2c_310_ cache_errata_is_applicable_754670() ); */858 859 if( l2c_310_ cache_errata_is_applicable_765569( rtl_release ) )857 /* assert( ! l2c_310_errata_is_applicable_754670() ); */ 858 859 if( l2c_310_errata_is_applicable_765569( rtl_release ) ) 860 860 { 861 861 volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE; … … 881 881 /* Unhandled erratum present: 769419 No automatic Store Buffer drain, 882 882 * visibility of written data requires an explicit Cache */ 883 assert( ! l2c_310_ cache_errata_is_applicable_769419( rtl_release ) );884 } 885 886 static inline void 887 cache_l2c_310_sync( void )883 assert( ! l2c_310_errata_is_applicable_769419( rtl_release ) ); 884 } 885 886 static inline void 887 l2c_310_sync( void ) 888 888 { 889 889 volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE; 890 cache_l2c_310_rtl_release rtl_release =890 l2c_310_rtl_release rtl_release = 891 891 l2cc->cache_id & L2C_310_ID_RTL_MASK; 892 892 893 if( l2c_310_ cache_errata_is_applicable_753970( rtl_release ) ) {893 if( l2c_310_errata_is_applicable_753970( rtl_release ) ) { 894 894 l2cc->dummy_cache_sync_reg = 0; 895 895 } else { … … 899 899 900 900 static inline void 901 cache_l2c_310_flush_1_line(901 l2c_310_flush_1_line( 902 902 const void *d_addr, 903 903 const bool is_errata_588369applicable … … 914 914 */ 915 915 l2cc->clean_pa = (uint32_t) d_addr; 916 cache_l2c_310_sync();916 l2c_310_sync(); 917 917 l2cc->inv_pa = (uint32_t) d_addr; 918 918 } else { … … 922 922 923 923 static inline void 924 cache_l2c_310_flush_range( const void* d_addr, const size_t n_bytes )924 l2c_310_flush_range( const void* d_addr, const size_t n_bytes ) 925 925 { 926 926 rtems_interrupt_lock_context lock_context; … … 933 933 L2C_310_MIN( ADDR_LAST, adx + L2C_310_MAX_LOCKING_BYTES ); 934 934 volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE; 935 cache_l2c_310_rtl_release rtl_release =935 l2c_310_rtl_release rtl_release = 936 936 l2cc->cache_id & L2C_310_ID_RTL_MASK; 937 937 bool is_errata_588369_applicable = 938 l2c_310_ cache_errata_is_applicable_588369( rtl_release );939 940 rtems_interrupt_lock_acquire( &l2c_310_ cache_lock, &lock_context );938 l2c_310_errata_is_applicable_588369( rtl_release ); 939 940 rtems_interrupt_lock_acquire( &l2c_310_lock, &lock_context ); 941 941 942 942 for (; … … 945 945 block_end = L2C_310_MIN( ADDR_LAST, adx + L2C_310_MAX_LOCKING_BYTES )) { 946 946 for (; adx <= block_end; adx += CPU_DATA_CACHE_ALIGNMENT ) { 947 cache_l2c_310_flush_1_line( (void*)adx, is_errata_588369_applicable );947 l2c_310_flush_1_line( (void*)adx, is_errata_588369_applicable ); 948 948 } 949 949 if( block_end < ADDR_LAST ) { 950 rtems_interrupt_lock_release( &l2c_310_ cache_lock, &lock_context );951 rtems_interrupt_lock_acquire( &l2c_310_ cache_lock, &lock_context );950 rtems_interrupt_lock_release( &l2c_310_lock, &lock_context ); 951 rtems_interrupt_lock_acquire( &l2c_310_lock, &lock_context ); 952 952 } 953 953 } 954 cache_l2c_310_sync();955 rtems_interrupt_lock_release( &l2c_310_ cache_lock, &lock_context );956 } 957 958 static inline void 959 cache_l2c_310_flush_entire( void )954 l2c_310_sync(); 955 rtems_interrupt_lock_release( &l2c_310_lock, &lock_context ); 956 } 957 958 static inline void 959 l2c_310_flush_entire( void ) 960 960 { 961 961 volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE; … … 968 968 _ARM_Data_memory_barrier(); 969 969 970 rtems_interrupt_lock_acquire( &l2c_310_ cache_lock, &lock_context );970 rtems_interrupt_lock_acquire( &l2c_310_lock, &lock_context ); 971 971 l2cc->clean_inv_way = L2C_310_WAY_MASK; 972 972 … … 974 974 975 975 /* Wait for the flush to complete */ 976 cache_l2c_310_sync();977 978 rtems_interrupt_lock_release( &l2c_310_ cache_lock, &lock_context );979 } 980 } 981 982 static inline void 983 cache_l2c_310_invalidate_1_line( const void *d_addr )976 l2c_310_sync(); 977 978 rtems_interrupt_lock_release( &l2c_310_lock, &lock_context ); 979 } 980 } 981 982 static inline void 983 l2c_310_invalidate_1_line( const void *d_addr ) 984 984 { 985 985 volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE; … … 987 987 988 988 l2cc->inv_pa = (uint32_t) d_addr; 989 cache_l2c_310_sync();990 } 991 992 static inline void 993 cache_l2c_310_invalidate_range( uint32_t adx, const uint32_t ADDR_LAST )989 l2c_310_sync(); 990 } 991 992 static inline void 993 l2c_310_invalidate_range( uint32_t adx, const uint32_t ADDR_LAST ) 994 994 { 995 995 volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE; 996 996 rtems_interrupt_lock_context lock_context; 997 997 998 rtems_interrupt_lock_acquire( &l2c_310_ cache_lock, &lock_context );998 rtems_interrupt_lock_acquire( &l2c_310_lock, &lock_context ); 999 999 for (; 1000 1000 adx <= ADDR_LAST; … … 1003 1003 l2cc->inv_pa = adx; 1004 1004 } 1005 cache_l2c_310_sync();1006 rtems_interrupt_lock_release( &l2c_310_ cache_lock, &lock_context );1007 } 1008 1009 static inline void 1010 cache_l2c_310_invalidate_entire( void )1005 l2c_310_sync(); 1006 rtems_interrupt_lock_release( &l2c_310_lock, &lock_context ); 1007 } 1008 1009 static inline void 1010 l2c_310_invalidate_entire( void ) 1011 1011 { 1012 1012 volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE; … … 1022 1022 1023 1023 /* Wait for the invalidate to complete */ 1024 cache_l2c_310_sync();1025 } 1026 1027 static inline void 1028 cache_l2c_310_clean_and_invalidate_entire( void )1024 l2c_310_sync(); 1025 } 1026 1027 static inline void 1028 l2c_310_clean_and_invalidate_entire( void ) 1029 1029 { 1030 1030 volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE; … … 1037 1037 _ARM_Data_memory_barrier(); 1038 1038 1039 rtems_interrupt_lock_acquire( &l2c_310_ cache_lock, &lock_context );1039 rtems_interrupt_lock_acquire( &l2c_310_lock, &lock_context ); 1040 1040 l2cc->clean_inv_way = L2C_310_WAY_MASK; 1041 1041 … … 1043 1043 1044 1044 /* Wait for the invalidate to complete */ 1045 cache_l2c_310_sync();1046 1047 rtems_interrupt_lock_release( &l2c_310_ cache_lock, &lock_context );1048 } 1049 } 1050 1051 static inline void 1052 cache_l2c_310_freeze( void )1045 l2c_310_sync(); 1046 1047 rtems_interrupt_lock_release( &l2c_310_lock, &lock_context ); 1048 } 1049 } 1050 1051 static inline void 1052 l2c_310_freeze( void ) 1053 1053 { 1054 1054 /* To be implemented as needed, if supported … … 1057 1057 1058 1058 static inline void 1059 cache_l2c_310_unfreeze( void )1059 l2c_310_unfreeze( void ) 1060 1060 { 1061 1061 /* To be implemented as needed, if supported … … 1064 1064 1065 1065 static inline size_t 1066 cache_l2c_310_get_cache_size( void )1066 l2c_310_get_cache_size( void ) 1067 1067 { 1068 1068 size_t size = 0; … … 1103 1103 } 1104 1104 1105 static void cache_l2c_310_unlock( volatile L2CC *l2cc )1105 static void l2c_310_unlock( volatile L2CC *l2cc ) 1106 1106 { 1107 1107 l2cc->d_lockdown_0 = 0; … … 1123 1123 } 1124 1124 1125 static void cache_l2c_310_wait_for_background_ops( volatile L2CC *l2cc )1125 static void l2c_310_wait_for_background_ops( volatile L2CC *l2cc ) 1126 1126 { 1127 1127 while ( l2cc->inv_way & L2C_310_WAY_MASK ) ; … … 1145 1145 1146 1146 static inline void 1147 cache_l2c_310_enable( void )1147 l2c_310_enable( void ) 1148 1148 { 1149 1149 volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE; 1150 1150 uint32_t cache_id = l2cc->cache_id; 1151 cache_l2c_310_rtl_release rtl_release =1151 l2c_310_rtl_release rtl_release = 1152 1152 cache_id & L2C_310_ID_RTL_MASK; 1153 1153 uint32_t id_mask = … … 1165 1165 } 1166 1166 1167 l2c_310_c ache_check_errata( rtl_release );1167 l2c_310_check_errata( rtl_release ); 1168 1168 1169 1169 /* Only enable if L2CC is currently disabled */ … … 1173 1173 1174 1174 /* Make sure that I&D is not locked down when starting */ 1175 cache_l2c_310_unlock( l2cc );1176 1177 cache_l2c_310_wait_for_background_ops( l2cc );1175 l2c_310_unlock( l2cc ); 1176 1177 l2c_310_wait_for_background_ops( l2cc ); 1178 1178 1179 1179 aux_ctrl = l2cc->aux_ctrl; … … 1199 1199 l2cc->data_ram_ctrl = L2C_310_DATA_RAM_DEFAULT_MASK; 1200 1200 1201 cache_l2c_310_invalidate_entire();1201 l2c_310_invalidate_entire(); 1202 1202 1203 1203 /* Clear the pending interrupts */ … … 1210 1210 1211 1211 static inline void 1212 cache_l2c_310_disable( void )1212 l2c_310_disable( void ) 1213 1213 { 1214 1214 volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE; … … 1217 1217 if ( l2cc->ctrl & L2C_310_ENABLE_MASK ) { 1218 1218 /* Clean and Invalidate L2 Cache */ 1219 cache_l2c_310_flush_entire();1220 rtems_interrupt_lock_acquire( &l2c_310_ cache_lock, &lock_context );1221 1222 cache_l2c_310_wait_for_background_ops( l2cc );1219 l2c_310_flush_entire(); 1220 rtems_interrupt_lock_acquire( &l2c_310_lock, &lock_context ); 1221 1222 l2c_310_wait_for_background_ops( l2cc ); 1223 1223 1224 1224 /* Disable the L2 cache */ 1225 1225 l2cc->ctrl &= ~L2C_310_ENABLE_MASK; 1226 rtems_interrupt_lock_release( &l2c_310_ cache_lock, &lock_context );1226 rtems_interrupt_lock_release( &l2c_310_lock, &lock_context ); 1227 1227 } 1228 1228 } … … 1231 1231 _CPU_cache_enable_data( void ) 1232 1232 { 1233 cache_l2c_310_enable();1233 l2c_310_enable(); 1234 1234 } 1235 1235 … … 1238 1238 { 1239 1239 arm_cache_l1_disable_data(); 1240 cache_l2c_310_disable();1240 l2c_310_disable(); 1241 1241 } 1242 1242 … … 1244 1244 _CPU_cache_enable_instruction( void ) 1245 1245 { 1246 cache_l2c_310_enable();1246 l2c_310_enable(); 1247 1247 } 1248 1248 … … 1251 1251 { 1252 1252 arm_cache_l1_disable_instruction(); 1253 cache_l2c_310_disable();1253 l2c_310_disable(); 1254 1254 } 1255 1255 … … 1265 1265 n_bytes 1266 1266 ); 1267 cache_l2c_310_flush_range(1267 l2c_310_flush_range( 1268 1268 d_addr, 1269 1269 n_bytes … … 1276 1276 { 1277 1277 arm_cache_l1_flush_entire_data(); 1278 cache_l2c_310_flush_entire();1278 l2c_310_flush_entire(); 1279 1279 } 1280 1280 … … 1300 1300 adx = block_end + 1, 1301 1301 block_end = L2C_310_MIN( ADDR_LAST, adx + L2C_310_MAX_LOCKING_BYTES )) { 1302 cache_l2c_310_invalidate_range(1302 l2c_310_invalidate_range( 1303 1303 adx, 1304 1304 block_end … … 1316 1316 adx = block_end + 1, 1317 1317 block_end = L2C_310_MIN( ADDR_LAST, adx + L2C_310_MAX_LOCKING_BYTES )) { 1318 cache_l2c_310_invalidate_range(1318 l2c_310_invalidate_range( 1319 1319 adx, 1320 1320 block_end … … 1335 1335 1336 1336 /* forces the address out past level 2 */ 1337 cache_l2c_310_clean_and_invalidate_entire();1337 l2c_310_clean_and_invalidate_entire(); 1338 1338 1339 1339 /*This is broadcast within the cluster */ … … 1345 1345 { 1346 1346 arm_cache_l1_freeze_data(); 1347 cache_l2c_310_freeze();1347 l2c_310_freeze(); 1348 1348 } 1349 1349 … … 1352 1352 { 1353 1353 arm_cache_l1_unfreeze_data(); 1354 cache_l2c_310_unfreeze();1354 l2c_310_unfreeze(); 1355 1355 } 1356 1356 … … 1371 1371 { 1372 1372 arm_cache_l1_freeze_instruction(); 1373 cache_l2c_310_freeze();1373 l2c_310_freeze(); 1374 1374 } 1375 1375 … … 1378 1378 { 1379 1379 arm_cache_l1_unfreeze_instruction(); 1380 cache_l2c_310_unfreeze();1380 l2c_310_unfreeze(); 1381 1381 } 1382 1382 … … 1393 1393 case 0: 1394 1394 case 2: 1395 size = cache_l2c_310_get_cache_size();1395 size = l2c_310_get_cache_size(); 1396 1396 break; 1397 1397 default: … … 1414 1414 case 0: 1415 1415 case 2: 1416 size = cache_l2c_310_get_cache_size();1416 size = l2c_310_get_cache_size(); 1417 1417 break; 1418 1418 default:
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