Changeset d53de34 in rtems


Ignore:
Timestamp:
Nov 19, 2014, 1:08:44 PM (5 years ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
4.11, master
Children:
55741886
Parents:
861d315
git-author:
Sebastian Huber <sebastian.huber@…> (11/19/14 13:08:44)
git-committer:
Sebastian Huber <sebastian.huber@…> (11/20/14 09:30:27)
Message:

bsps/arm: L2C 310 use l2c_310_* prefix throughout

File:
1 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h

    r861d315 rd53de34  
    9999  L2C_310_RTL_RELEASE_R3_P2 = 0x8,
    100100  L2C_310_RTL_RELEASE_R3_P3 = 0x9
    101 } cache_l2c_310_rtl_release;
     101} l2c_310_rtl_release;
    102102
    103103/**
     
    464464} L2CC;
    465465
    466 rtems_interrupt_lock l2c_310_cache_lock = RTEMS_INTERRUPT_LOCK_INITIALIZER(
     466rtems_interrupt_lock l2c_310_lock = RTEMS_INTERRUPT_LOCK_INITIALIZER(
    467467  "cache"
    468468);
     
    478478*   r3 releases Software Developers Errata Notice"
    479479* Please see this document for more information on these erratas */
    480 static bool l2c_310_cache_errata_is_applicable_753970(
    481   cache_l2c_310_rtl_release rtl_release
     480static bool l2c_310_errata_is_applicable_753970(
     481  l2c_310_rtl_release rtl_release
    482482)
    483483{
     
    504504}
    505505
    506 static bool l2c_310_cache_errata_is_applicable_727913(
    507   cache_l2c_310_rtl_release rtl_release
     506static bool l2c_310_errata_is_applicable_727913(
     507  l2c_310_rtl_release rtl_release
    508508)
    509509{
     
    530530}
    531531
    532 static bool l2c_310_cache_errata_is_applicable_727914(
    533   cache_l2c_310_rtl_release rtl_release
     532static bool l2c_310_errata_is_applicable_727914(
     533  l2c_310_rtl_release rtl_release
    534534)
    535535{
     
    556556}
    557557
    558 static bool l2c_310_cache_errata_is_applicable_727915(
    559   cache_l2c_310_rtl_release rtl_release
     558static bool l2c_310_errata_is_applicable_727915(
     559  l2c_310_rtl_release rtl_release
    560560)
    561561{
     
    582582}
    583583
    584 static bool l2c_310_cache_errata_is_applicable_729806(
    585   cache_l2c_310_rtl_release rtl_release
     584static bool l2c_310_errata_is_applicable_729806(
     585  l2c_310_rtl_release rtl_release
    586586)
    587587{
     
    608608}
    609609
    610 static bool l2c_310_cache_errata_is_applicable_729815(
    611   cache_l2c_310_rtl_release rtl_release
     610static bool l2c_310_errata_is_applicable_729815(
     611  l2c_310_rtl_release rtl_release
    612612)
    613613{
     
    634634}
    635635
    636 static bool l2c_310_cache_errata_is_applicable_742884(
    637   cache_l2c_310_rtl_release rtl_release
     636static bool l2c_310_errata_is_applicable_742884(
     637  l2c_310_rtl_release rtl_release
    638638)
    639639{
     
    660660}
    661661
    662 static bool l2c_310_cache_errata_is_applicable_752271(
    663   cache_l2c_310_rtl_release rtl_release
     662static bool l2c_310_errata_is_applicable_752271(
     663  l2c_310_rtl_release rtl_release
    664664)
    665665{
     
    686686}
    687687
    688 static bool l2c_310_cache_errata_is_applicable_765569(
    689   cache_l2c_310_rtl_release rtl_release
     688static bool l2c_310_errata_is_applicable_765569(
     689  l2c_310_rtl_release rtl_release
    690690)
    691691{
     
    710710}
    711711
    712 static bool l2c_310_cache_errata_is_applicable_769419(
    713   cache_l2c_310_rtl_release rtl_release
     712static bool l2c_310_errata_is_applicable_769419(
     713  l2c_310_rtl_release rtl_release
    714714)
    715715{
     
    736736}
    737737
    738 static bool l2c_310_cache_errata_is_applicable_588369(
    739   cache_l2c_310_rtl_release rtl_release
     738static bool l2c_310_errata_is_applicable_588369(
     739  l2c_310_rtl_release rtl_release
    740740)
    741741{
     
    763763
    764764#ifdef CACHE_ERRATA_CHECKS_FOR_IMPLEMENTED_ERRATAS
    765 static bool l2c_310_cache_errata_is_applicable_754670(
    766   cache_l2c_310_rtl_release rtl_release
     765static bool l2c_310_errata_is_applicable_754670(
     766  l2c_310_rtl_release rtl_release
    767767)
    768768{
     
    796796  }                                                         \
    797797
    798 static void l2c_310_cache_check_errata( cache_l2c_310_rtl_release rtl_release )
     798static void l2c_310_check_errata( l2c_310_rtl_release rtl_release )
    799799{
    800800  /* This erratum gets handled within the sources */
     
    802802   * keep the cache line if it was clean. See ARMs documentation on the erratum
    803803   * for a workaround */
    804   /* assert( ! l2c_310_cache_errata_is_applicable_588369( rtl_release ) ); */
     804  /* assert( ! l2c_310_errata_is_applicable_588369( rtl_release ) ); */
    805805
    806806  /* Unhandled erratum present: 727913 Prefetch dropping feature can cause
    807807   * incorrect behavior when PL310 handles reads that cross cache line
    808808   * boundary */
    809   assert( ! l2c_310_cache_errata_is_applicable_727913( rtl_release ) );
     809  assert( ! l2c_310_errata_is_applicable_727913( rtl_release ) );
    810810
    811811  /* Unhandled erratum present: 727914 Double linefill feature can cause
    812812   * deadlock */
    813   assert( ! l2c_310_cache_errata_is_applicable_727914( rtl_release ) );
     813  assert( ! l2c_310_errata_is_applicable_727914( rtl_release ) );
    814814
    815815  /* Unhandled erratum present: 727915 Background Clean and Invalidate by Way
    816816   * operation can cause data corruption */
    817   assert( ! l2c_310_cache_errata_is_applicable_727915( rtl_release ) );
     817  assert( ! l2c_310_errata_is_applicable_727915( rtl_release ) );
    818818
    819819  /* Unhandled erratum present: 729806 Speculative reads from the Cortex-A9
    820820   * MPCore processor can cause deadlock */
    821   assert( ! l2c_310_cache_errata_is_applicable_729806( rtl_release ) );
    822 
    823   if( l2c_310_cache_errata_is_applicable_729815( rtl_release ) )
     821  assert( ! l2c_310_errata_is_applicable_729806( rtl_release ) );
     822
     823  if( l2c_310_errata_is_applicable_729815( rtl_release ) )
    824824  {
    825825    volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE;
     
    846846  /* Unhandled erratum present: 742884 Double linefill feature might introduce
    847847   * circular dependency and deadlock */
    848   assert( ! l2c_310_cache_errata_is_applicable_742884( rtl_release ) );
     848  assert( ! l2c_310_errata_is_applicable_742884( rtl_release ) );
    849849
    850850  /* Unhandled erratum present: 752271 Double linefill feature can cause data
    851851   * corruption */
    852   assert( ! l2c_310_cache_errata_is_applicable_752271( rtl_release ) );
     852  assert( ! l2c_310_errata_is_applicable_752271( rtl_release ) );
    853853
    854854  /* This erratum can not be worked around: 754670 A continuous write flow can
    855855   * stall a read targeting the same memory area
    856856   * But this erratum does not lead to any data corruption */
    857   /* assert( ! l2c_310_cache_errata_is_applicable_754670() ); */
    858 
    859   if( l2c_310_cache_errata_is_applicable_765569( rtl_release ) )
     857  /* assert( ! l2c_310_errata_is_applicable_754670() ); */
     858
     859  if( l2c_310_errata_is_applicable_765569( rtl_release ) )
    860860  {
    861861    volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE;
     
    881881  /* Unhandled erratum present: 769419 No automatic Store Buffer drain,
    882882   * visibility of written data requires an explicit Cache */
    883   assert( ! l2c_310_cache_errata_is_applicable_769419( rtl_release ) );
    884 }
    885 
    886 static inline void
    887 cache_l2c_310_sync( void )
     883  assert( ! l2c_310_errata_is_applicable_769419( rtl_release ) );
     884}
     885
     886static inline void
     887l2c_310_sync( void )
    888888{
    889889  volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE;
    890   cache_l2c_310_rtl_release rtl_release =
     890  l2c_310_rtl_release rtl_release =
    891891    l2cc->cache_id & L2C_310_ID_RTL_MASK;
    892892
    893   if( l2c_310_cache_errata_is_applicable_753970( rtl_release ) ) {
     893  if( l2c_310_errata_is_applicable_753970( rtl_release ) ) {
    894894    l2cc->dummy_cache_sync_reg = 0;
    895895  } else {
     
    899899
    900900static inline void
    901 cache_l2c_310_flush_1_line(
     901l2c_310_flush_1_line(
    902902  const void *d_addr,
    903903  const bool  is_errata_588369applicable
     
    914914    */
    915915    l2cc->clean_pa     = (uint32_t) d_addr;
    916     cache_l2c_310_sync();
     916    l2c_310_sync();
    917917    l2cc->inv_pa       = (uint32_t) d_addr;
    918918  } else {
     
    922922
    923923static inline void
    924 cache_l2c_310_flush_range( const void* d_addr, const size_t n_bytes )
     924l2c_310_flush_range( const void* d_addr, const size_t n_bytes )
    925925{
    926926  rtems_interrupt_lock_context lock_context;
     
    933933    L2C_310_MIN( ADDR_LAST, adx + L2C_310_MAX_LOCKING_BYTES );
    934934  volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE;
    935   cache_l2c_310_rtl_release rtl_release =
     935  l2c_310_rtl_release rtl_release =
    936936    l2cc->cache_id & L2C_310_ID_RTL_MASK;
    937937  bool is_errata_588369_applicable =
    938     l2c_310_cache_errata_is_applicable_588369( rtl_release );
    939 
    940   rtems_interrupt_lock_acquire( &l2c_310_cache_lock, &lock_context );
     938    l2c_310_errata_is_applicable_588369( rtl_release );
     939
     940  rtems_interrupt_lock_acquire( &l2c_310_lock, &lock_context );
    941941
    942942  for (;
     
    945945       block_end = L2C_310_MIN( ADDR_LAST, adx + L2C_310_MAX_LOCKING_BYTES )) {
    946946    for (; adx <= block_end; adx += CPU_DATA_CACHE_ALIGNMENT ) {
    947       cache_l2c_310_flush_1_line( (void*)adx, is_errata_588369_applicable );
     947      l2c_310_flush_1_line( (void*)adx, is_errata_588369_applicable );
    948948    }
    949949    if( block_end < ADDR_LAST ) {
    950       rtems_interrupt_lock_release( &l2c_310_cache_lock, &lock_context );
    951       rtems_interrupt_lock_acquire( &l2c_310_cache_lock, &lock_context );
     950      rtems_interrupt_lock_release( &l2c_310_lock, &lock_context );
     951      rtems_interrupt_lock_acquire( &l2c_310_lock, &lock_context );
    952952    }
    953953  }
    954   cache_l2c_310_sync();
    955   rtems_interrupt_lock_release( &l2c_310_cache_lock, &lock_context );
    956 }
    957 
    958 static inline void
    959 cache_l2c_310_flush_entire( void )
     954  l2c_310_sync();
     955  rtems_interrupt_lock_release( &l2c_310_lock, &lock_context );
     956}
     957
     958static inline void
     959l2c_310_flush_entire( void )
    960960{
    961961  volatile L2CC               *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE;
     
    968968    _ARM_Data_memory_barrier();
    969969
    970     rtems_interrupt_lock_acquire( &l2c_310_cache_lock, &lock_context );
     970    rtems_interrupt_lock_acquire( &l2c_310_lock, &lock_context );
    971971    l2cc->clean_inv_way = L2C_310_WAY_MASK;
    972972
     
    974974
    975975    /* Wait for the flush to complete */
    976     cache_l2c_310_sync();
    977 
    978     rtems_interrupt_lock_release( &l2c_310_cache_lock, &lock_context );
    979   }
    980 }
    981 
    982 static inline void
    983 cache_l2c_310_invalidate_1_line( const void *d_addr )
     976    l2c_310_sync();
     977
     978    rtems_interrupt_lock_release( &l2c_310_lock, &lock_context );
     979  }
     980}
     981
     982static inline void
     983l2c_310_invalidate_1_line( const void *d_addr )
    984984{
    985985  volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE;
     
    987987
    988988  l2cc->inv_pa = (uint32_t) d_addr;
    989   cache_l2c_310_sync();
    990 }
    991 
    992 static inline void
    993 cache_l2c_310_invalidate_range( uint32_t adx, const uint32_t ADDR_LAST )
     989  l2c_310_sync();
     990}
     991
     992static inline void
     993l2c_310_invalidate_range( uint32_t adx, const uint32_t ADDR_LAST )
    994994{
    995995  volatile L2CC               *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE;
    996996  rtems_interrupt_lock_context lock_context;
    997997
    998   rtems_interrupt_lock_acquire( &l2c_310_cache_lock, &lock_context );
     998  rtems_interrupt_lock_acquire( &l2c_310_lock, &lock_context );
    999999  for (;
    10001000       adx <= ADDR_LAST;
     
    10031003    l2cc->inv_pa = adx;
    10041004  }
    1005   cache_l2c_310_sync();
    1006   rtems_interrupt_lock_release( &l2c_310_cache_lock, &lock_context );
    1007 }
    1008 
    1009 static inline void
    1010 cache_l2c_310_invalidate_entire( void )
     1005  l2c_310_sync();
     1006  rtems_interrupt_lock_release( &l2c_310_lock, &lock_context );
     1007}
     1008
     1009static inline void
     1010l2c_310_invalidate_entire( void )
    10111011{
    10121012  volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE;
     
    10221022
    10231023  /* Wait for the invalidate to complete */
    1024   cache_l2c_310_sync();
    1025 }
    1026 
    1027 static inline void
    1028 cache_l2c_310_clean_and_invalidate_entire( void )
     1024  l2c_310_sync();
     1025}
     1026
     1027static inline void
     1028l2c_310_clean_and_invalidate_entire( void )
    10291029{
    10301030  volatile L2CC               *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE;
     
    10371037    _ARM_Data_memory_barrier();
    10381038
    1039     rtems_interrupt_lock_acquire( &l2c_310_cache_lock, &lock_context );
     1039    rtems_interrupt_lock_acquire( &l2c_310_lock, &lock_context );
    10401040    l2cc->clean_inv_way = L2C_310_WAY_MASK;
    10411041
     
    10431043
    10441044    /* Wait for the invalidate to complete */
    1045     cache_l2c_310_sync();
    1046 
    1047     rtems_interrupt_lock_release( &l2c_310_cache_lock, &lock_context );
    1048   }
    1049 }
    1050 
    1051 static inline void
    1052 cache_l2c_310_freeze( void )
     1045    l2c_310_sync();
     1046
     1047    rtems_interrupt_lock_release( &l2c_310_lock, &lock_context );
     1048  }
     1049}
     1050
     1051static inline void
     1052l2c_310_freeze( void )
    10531053{
    10541054  /* To be implemented as needed, if supported
     
    10571057
    10581058static inline void
    1059 cache_l2c_310_unfreeze( void )
     1059l2c_310_unfreeze( void )
    10601060{
    10611061  /* To be implemented as needed, if supported
     
    10641064
    10651065static inline size_t
    1066 cache_l2c_310_get_cache_size( void )
     1066l2c_310_get_cache_size( void )
    10671067{
    10681068  size_t         size       = 0;
     
    11031103}
    11041104
    1105 static void cache_l2c_310_unlock( volatile L2CC *l2cc )
     1105static void l2c_310_unlock( volatile L2CC *l2cc )
    11061106{
    11071107  l2cc->d_lockdown_0 = 0;
     
    11231123}
    11241124
    1125 static void cache_l2c_310_wait_for_background_ops( volatile L2CC *l2cc )
     1125static void l2c_310_wait_for_background_ops( volatile L2CC *l2cc )
    11261126{
    11271127  while ( l2cc->inv_way & L2C_310_WAY_MASK ) ;
     
    11451145
    11461146static inline void
    1147 cache_l2c_310_enable( void )
     1147l2c_310_enable( void )
    11481148{
    11491149  volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE;
    11501150  uint32_t cache_id = l2cc->cache_id;
    1151   cache_l2c_310_rtl_release rtl_release =
     1151  l2c_310_rtl_release rtl_release =
    11521152    cache_id & L2C_310_ID_RTL_MASK;
    11531153  uint32_t id_mask =
     
    11651165  }
    11661166
    1167   l2c_310_cache_check_errata( rtl_release );
     1167  l2c_310_check_errata( rtl_release );
    11681168
    11691169  /* Only enable if L2CC is currently disabled */
     
    11731173
    11741174    /* Make sure that I&D is not locked down when starting */
    1175     cache_l2c_310_unlock( l2cc );
    1176 
    1177     cache_l2c_310_wait_for_background_ops( l2cc );
     1175    l2c_310_unlock( l2cc );
     1176
     1177    l2c_310_wait_for_background_ops( l2cc );
    11781178
    11791179    aux_ctrl = l2cc->aux_ctrl;
     
    11991199    l2cc->data_ram_ctrl = L2C_310_DATA_RAM_DEFAULT_MASK;
    12001200
    1201     cache_l2c_310_invalidate_entire();
     1201    l2c_310_invalidate_entire();
    12021202
    12031203    /* Clear the pending interrupts */
     
    12101210
    12111211static inline void
    1212 cache_l2c_310_disable( void )
     1212l2c_310_disable( void )
    12131213{
    12141214  volatile L2CC               *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE;
     
    12171217  if ( l2cc->ctrl & L2C_310_ENABLE_MASK ) {
    12181218    /* Clean and Invalidate L2 Cache */
    1219     cache_l2c_310_flush_entire();
    1220     rtems_interrupt_lock_acquire( &l2c_310_cache_lock, &lock_context );
    1221 
    1222     cache_l2c_310_wait_for_background_ops( l2cc );
     1219    l2c_310_flush_entire();
     1220    rtems_interrupt_lock_acquire( &l2c_310_lock, &lock_context );
     1221
     1222    l2c_310_wait_for_background_ops( l2cc );
    12231223
    12241224    /* Disable the L2 cache */
    12251225    l2cc->ctrl &= ~L2C_310_ENABLE_MASK;
    1226     rtems_interrupt_lock_release( &l2c_310_cache_lock, &lock_context );
     1226    rtems_interrupt_lock_release( &l2c_310_lock, &lock_context );
    12271227  }
    12281228}
     
    12311231_CPU_cache_enable_data( void )
    12321232{
    1233   cache_l2c_310_enable();
     1233  l2c_310_enable();
    12341234}
    12351235
     
    12381238{
    12391239  arm_cache_l1_disable_data();
    1240   cache_l2c_310_disable();
     1240  l2c_310_disable();
    12411241}
    12421242
     
    12441244_CPU_cache_enable_instruction( void )
    12451245{
    1246   cache_l2c_310_enable();
     1246  l2c_310_enable();
    12471247}
    12481248
     
    12511251{
    12521252  arm_cache_l1_disable_instruction();
    1253   cache_l2c_310_disable();
     1253  l2c_310_disable();
    12541254}
    12551255
     
    12651265      n_bytes
    12661266    );
    1267     cache_l2c_310_flush_range(
     1267    l2c_310_flush_range(
    12681268      d_addr,
    12691269      n_bytes
     
    12761276{
    12771277  arm_cache_l1_flush_entire_data();
    1278   cache_l2c_310_flush_entire();
     1278  l2c_310_flush_entire();
    12791279}
    12801280
     
    13001300         adx       = block_end + 1,
    13011301         block_end = L2C_310_MIN( ADDR_LAST, adx + L2C_310_MAX_LOCKING_BYTES )) {
    1302       cache_l2c_310_invalidate_range(
     1302      l2c_310_invalidate_range(
    13031303        adx,
    13041304        block_end
     
    13161316         adx       = block_end + 1,
    13171317         block_end = L2C_310_MIN( ADDR_LAST, adx + L2C_310_MAX_LOCKING_BYTES )) {
    1318       cache_l2c_310_invalidate_range(
     1318      l2c_310_invalidate_range(
    13191319        adx,
    13201320        block_end
     
    13351335
    13361336  /* forces the address out past level 2 */
    1337   cache_l2c_310_clean_and_invalidate_entire();
     1337  l2c_310_clean_and_invalidate_entire();
    13381338
    13391339  /*This is broadcast within the cluster */
     
    13451345{
    13461346  arm_cache_l1_freeze_data();
    1347   cache_l2c_310_freeze();
     1347  l2c_310_freeze();
    13481348}
    13491349
     
    13521352{
    13531353  arm_cache_l1_unfreeze_data();
    1354   cache_l2c_310_unfreeze();
     1354  l2c_310_unfreeze();
    13551355}
    13561356
     
    13711371{
    13721372  arm_cache_l1_freeze_instruction();
    1373   cache_l2c_310_freeze();
     1373  l2c_310_freeze();
    13741374}
    13751375
     
    13781378{
    13791379  arm_cache_l1_unfreeze_instruction();
    1380   cache_l2c_310_unfreeze();
     1380  l2c_310_unfreeze();
    13811381}
    13821382
     
    13931393    case 0:
    13941394    case 2:
    1395       size = cache_l2c_310_get_cache_size();
     1395      size = l2c_310_get_cache_size();
    13961396    break;
    13971397    default:
     
    14141414    case 0:
    14151415    case 2:
    1416       size = cache_l2c_310_get_cache_size();
     1416      size = l2c_310_get_cache_size();
    14171417      break;
    14181418    default:
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