Changeset d50c0d2 in rtems


Ignore:
Timestamp:
Apr 26, 2002, 9:34:58 PM (18 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, master
Children:
616b9f5
Parents:
6236b47
Message:

2002-04-26 Eric Norum <eric.norum@…>

  • netinet/in_cksum_i386.c: Add volatile so the more agressive optimization in gcc 3.1 does not reorder things.
Files:
7 edited

Legend:

Unmodified
Added
Removed
  • c/src/exec/libnetworking/ChangeLog

    r6236b47 rd50c0d2  
     12002-04-26      Eric Norum <eric.norum@usask.ca>
     2
     3        * netinet/in_cksum_i386.c: Add volatile so the more agressive
     4        optimization in gcc 3.1 does not reorder things.
     5
    162002-04-18      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
    27
  • c/src/exec/libnetworking/netinet/in_cksum_i386.c

    r6236b47 rd50c0d2  
    2020 * which registers contain sum & w.
    2121 */
    22 #define ADD(n)  asm("addl " #n "(%2), %0" : "=r" (sum) : "0" (sum), "r" (w))
    23 #define ADDC(n) asm("adcl " #n "(%2), %0" : "=r" (sum) : "0" (sum), "r" (w))
    24 #define LOAD(n) asm volatile("movb " #n "(%1), %0" : "=r" (junk) : "r" (w))
    25 #define MOP     asm("adcl         $0, %0" : "=r" (sum) : "0" (sum))
     22#define ADD(n)  __asm__ volatile \
     23    ("addl " #n "(%2), %0" : "=r" (sum) : "0" (sum), "r" (w))
     24#define ADDC(n) __asm__ volatile \
     25    ("adcl " #n "(%2), %0" : "=r" (sum) : "0" (sum), "r" (w))
     26#define LOAD(n) __asm__ volatile \
     27     ("movb " #n "(%1), %0" : "=r" (junk) : "r" (w))
     28#define MOP     __asm__ volatile \
     29    ("adcl         $0, %0" : "=r" (sum) : "0" (sum))
    2630
    2731int
  • c/src/libnetworking/ChangeLog

    r6236b47 rd50c0d2  
     12002-04-26      Eric Norum <eric.norum@usask.ca>
     2
     3        * netinet/in_cksum_i386.c: Add volatile so the more agressive
     4        optimization in gcc 3.1 does not reorder things.
     5
    162002-04-18      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
    27
  • c/src/libnetworking/netinet/in_cksum_i386.c

    r6236b47 rd50c0d2  
    2020 * which registers contain sum & w.
    2121 */
    22 #define ADD(n)  asm("addl " #n "(%2), %0" : "=r" (sum) : "0" (sum), "r" (w))
    23 #define ADDC(n) asm("adcl " #n "(%2), %0" : "=r" (sum) : "0" (sum), "r" (w))
    24 #define LOAD(n) asm volatile("movb " #n "(%1), %0" : "=r" (junk) : "r" (w))
    25 #define MOP     asm("adcl         $0, %0" : "=r" (sum) : "0" (sum))
     22#define ADD(n)  __asm__ volatile \
     23    ("addl " #n "(%2), %0" : "=r" (sum) : "0" (sum), "r" (w))
     24#define ADDC(n) __asm__ volatile \
     25    ("adcl " #n "(%2), %0" : "=r" (sum) : "0" (sum), "r" (w))
     26#define LOAD(n) __asm__ volatile \
     27     ("movb " #n "(%1), %0" : "=r" (junk) : "r" (w))
     28#define MOP     __asm__ volatile \
     29    ("adcl         $0, %0" : "=r" (sum) : "0" (sum))
    2630
    2731int
  • cpukit/libnetworking/ChangeLog

    r6236b47 rd50c0d2  
     12002-04-26      Eric Norum <eric.norum@usask.ca>
     2
     3        * netinet/in_cksum_i386.c: Add volatile so the more agressive
     4        optimization in gcc 3.1 does not reorder things.
     5
    162002-04-18      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
    27
  • cpukit/libnetworking/netinet/in_cksum_i386.c

    r6236b47 rd50c0d2  
    2020 * which registers contain sum & w.
    2121 */
    22 #define ADD(n)  asm("addl " #n "(%2), %0" : "=r" (sum) : "0" (sum), "r" (w))
    23 #define ADDC(n) asm("adcl " #n "(%2), %0" : "=r" (sum) : "0" (sum), "r" (w))
    24 #define LOAD(n) asm volatile("movb " #n "(%1), %0" : "=r" (junk) : "r" (w))
    25 #define MOP     asm("adcl         $0, %0" : "=r" (sum) : "0" (sum))
     22#define ADD(n)  __asm__ volatile \
     23    ("addl " #n "(%2), %0" : "=r" (sum) : "0" (sum), "r" (w))
     24#define ADDC(n) __asm__ volatile \
     25    ("adcl " #n "(%2), %0" : "=r" (sum) : "0" (sum), "r" (w))
     26#define LOAD(n) __asm__ volatile \
     27     ("movb " #n "(%1), %0" : "=r" (junk) : "r" (w))
     28#define MOP     __asm__ volatile \
     29    ("adcl         $0, %0" : "=r" (sum) : "0" (sum))
    2630
    2731int
  • cpukit/libnetworking/netinet/in_cksum_i386.h

    r6236b47 rd50c0d2  
    2020 * which registers contain sum & w.
    2121 */
    22 #define ADD(n)  asm("addl " #n "(%2), %0" : "=r" (sum) : "0" (sum), "r" (w))
    23 #define ADDC(n) asm("adcl " #n "(%2), %0" : "=r" (sum) : "0" (sum), "r" (w))
    24 #define LOAD(n) asm volatile("movb " #n "(%1), %0" : "=r" (junk) : "r" (w))
    25 #define MOP     asm("adcl         $0, %0" : "=r" (sum) : "0" (sum))
     22#define ADD(n)  __asm__ volatile \
     23    ("addl " #n "(%2), %0" : "=r" (sum) : "0" (sum), "r" (w))
     24#define ADDC(n) __asm__ volatile \
     25    ("adcl " #n "(%2), %0" : "=r" (sum) : "0" (sum), "r" (w))
     26#define LOAD(n) __asm__ volatile \
     27     ("movb " #n "(%1), %0" : "=r" (junk) : "r" (w))
     28#define MOP     __asm__ volatile \
     29    ("adcl         $0, %0" : "=r" (sum) : "0" (sum))
    2630
    2731int
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