Changeset d4b4664b in rtems


Ignore:
Timestamp:
Nov 29, 2009, 2:59:41 PM (9 years ago)
Author:
Ralf Corsepius <ralf.corsepius@…>
Branches:
4.10, 4.11, master
Children:
efdfd48
Parents:
32b8506
Message:

Whitespace removal.

Location:
c/src/lib/libbsp/m68k
Files:
51 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/m68k/av5282/console/console.c

    r32b8506 rd4b4664b  
    2828static void
    2929_BSP_null_char( char c )
    30 { 
     30{
    3131        int level;
    3232
     
    156156   value and sets it. At the moment this just sets the baud rate.
    157157
    158    Note: The highest baudrate is 115200 as this stays within 
     158   Note: The highest baudrate is 115200 as this stays within
    159159   an error of +/- 5% at 25MHz processor clock
    160160 ***************************************************************************/
     
    338338                info->hwflow   = -1;
    339339                info->iomode   = TERMIOS_POLLED;
    340                
     340
    341341                MCF5282_UART_UACR(chan) = 0;
    342342                MCF5282_UART_UIMR(chan) = 0;
     
    386386   Function : IntUartInterruptWrite
    387387
    388    Description : This writes a single character to the appropriate uart 
     388   Description : This writes a single character to the appropriate uart
    389389   channel. This is either called during an interrupt or in the user's task
    390    to initiate a transmit sequence. Calling this routine enables Tx 
     390   to initiate a transmit sequence. Calling this routine enables Tx
    391391   interrupts.
    392392 ***************************************************************************/
     
    495495        while ( ( index < count ) && ( index < RX_BUFFER_SIZE ) )
    496496        {
    497                 /* copy data byte */ 
     497                /* copy data byte */
    498498                buffer[index] = info->rx_buffer[info->rx_out];
    499499                index++;
     
    522522   Function : IntUartPollRead
    523523
    524    Description : This reads a character from the internal uart. It returns 
     524   Description : This reads a character from the internal uart. It returns
    525525   to the caller without blocking if not character is waiting.
    526526 ***************************************************************************/
     
    538538   Function : IntUartPollWrite
    539539
    540    Description : This writes out each character in the buffer to the 
    541    appropriate internal uart channel waiting till each one is sucessfully 
     540   Description : This writes out each character in the buffer to the
     541   appropriate internal uart channel waiting till each one is sucessfully
    542542   transmitted.
    543543 ***************************************************************************/
     
    576576        /* set io modes for the different channels and initialize device */
    577577    IntUartInfo[minor].iomode = TERMIOS_IRQ_DRIVEN;
    578         IntUartInitialize(); 
     578        IntUartInitialize();
    579579
    580580        /* Register the console port */
     
    609609   Function : console_open
    610610
    611    Description : This actually opens the device depending on the minor 
     611   Description : This actually opens the device depending on the minor
    612612   number set during initialisation. The device specific access routines are
    613613   passed to termios when the devices is opened depending on whether it is
  • c/src/lib/libbsp/m68k/av5282/include/bsp.h

    r32b8506 rd4b4664b  
    22 *  av5282 BSP header file
    33 */
    4  
     4
    55#ifndef __SBav5282_BSP_H
    66#define __SBav5282_BSP_H
  • c/src/lib/libbsp/m68k/av5282/network/network.c

    r32b8506 rd4b4664b  
    116116{
    117117    MCF5282_FEC_EIR = MCF5282_FEC_EIR_RXF;
    118     MCF5282_FEC_EIMR &= ~MCF5282_FEC_EIMR_RXF;   
     118    MCF5282_FEC_EIMR &= ~MCF5282_FEC_EIMR_RXF;
    119119    enet_driver[0].rxInterrupts++;
    120120    rtems_event_send(enet_driver[0].rxDaemonTid, RX_INTERRUPT_EVENT);
     
    125125{
    126126    MCF5282_FEC_EIR = MCF5282_FEC_EIR_TXF;
    127     MCF5282_FEC_EIMR &= ~MCF5282_FEC_EIMR_TXF;   
     127    MCF5282_FEC_EIMR &= ~MCF5282_FEC_EIMR_TXF;
    128128    enet_driver[0].txInterrupts++;
    129129    rtems_event_send(enet_driver[0].txDaemonTid, TX_INTERRUPT_EVENT);
     
    265265     *   No loopback
    266266     */
    267     MCF5282_FEC_RCR = MCF5282_FEC_RCR_MAX_FL(MAX_MTU_SIZE) | 
     267    MCF5282_FEC_RCR = MCF5282_FEC_RCR_MAX_FL(MAX_MTU_SIZE) |
    268268                      MCF5282_FEC_RCR_MII_MODE;
    269269
     
    335335                          MCF5282_INTC_ICR_IP(FEC_IRQ_RX_PRIORITY);
    336336    MCF5282_INTC0_IMRL &= ~(MCF5282_INTC_IMRL_INT27 | MCF5282_INTC_IMRL_MASKALL);
    337    
     337
    338338        status = rtems_interrupt_catch(mcf5282_mii_interrupt_handler, MII_VECTOR, &old_handler);
    339339    if (status != RTEMS_SUCCESSFUL)
     
    505505    nAdded = 0;
    506506    firstTxBd = sc->txBdBase + sc->txBdHead;
    507    
     507
    508508    while(m != NULL) {
    509                 /* 
     509                /*
    510510                * Wait for buffer descriptor to become available
    511511                */
     
    515515                */
    516516                MCF5282_FEC_EIR = MCF5282_FEC_EIR_TXF;
    517        
     517
    518518                /*
    519519                * Wait for buffer descriptor to become available.
     
    526526                        rtems_event_set events;
    527527                        int level;
    528        
     528
    529529                        rtems_interrupt_disable(level);
    530                         MCF5282_FEC_EIMR |= MCF5282_FEC_EIMR_TXF;   
     530                        MCF5282_FEC_EIMR |= MCF5282_FEC_EIMR_TXF;
    531531                        rtems_interrupt_enable(level);
    532532                        sc->txRawWait++;
     
    538538                }
    539539                }
    540        
     540
    541541                /*
    542542                * Don't set the READY flag on the first fragment
     
    544544                */
    545545                status = nAdded ? MCF5282_FEC_TxBD_R : 0;
    546        
     546
    547547                /*
    548548                * The IP fragmentation routine in ip_output
     
    623623         * Wait for packet
    624624         */
    625         rtems_bsdnet_event_receive(START_TRANSMIT_EVENT, 
    626                                     RTEMS_EVENT_ANY | RTEMS_WAIT, 
    627                                     RTEMS_NO_TIMEOUT, 
     625        rtems_bsdnet_event_receive(START_TRANSMIT_EVENT,
     626                                    RTEMS_EVENT_ANY | RTEMS_WAIT,
     627                                    RTEMS_NO_TIMEOUT,
    628628                                    &events);
    629629
  • c/src/lib/libbsp/m68k/av5282/start/start.S

    r32b8506 rd4b4664b  
    2525BEGIN_CODE
    2626#define INITIAL_STACK __SRAMBASE+SRAM_SIZE-4
    27        
     27
    2828        PUBLIC (INTERRUPT_VECTOR)
    2929SYM(INTERRUPT_VECTOR):
    30     .long   INITIAL_STACK   |   0: Initial 'SSP'   
     30    .long   INITIAL_STACK   |   0: Initial 'SSP'
    3131    .long   start           |   1: Initial PC
    3232    .long   SYM(_uhoh)      |   2: Bus error
     
    291291.align 4
    292292    PUBLIC (_uhoh)
    293 SYM(_uhoh): 
     293SYM(_uhoh):
    294294    nop                 | Leave spot for breakpoint
    295     stop    #0x2700             | Stop with interrupts disabled 
     295    stop    #0x2700             | Stop with interrupts disabled
    296296    bra.w   SYM(_uhoh)          | Stuck forever
    297297
     
    326326    move.l  #__IPSBAR+1,d0      | Enable the MCF5282 internal peripherals
    327327    move.l  d0,DEFAULT_IPSBAR
    328        
     328
    329329    /*
    330330     * Remainder of the startup code is handled by C code
     
    335335   Function : CopyDataClearBSSAndStart
    336336
    337    Description : Copy DATA segment, Copy SRAM segment, clear BSS segment, 
     337   Description : Copy DATA segment, Copy SRAM segment, clear BSS segment,
    338338   start C program. Assume that DATA and BSS sizes are multiples of 4.
    339339 ***************************************************************************/
     
    343343SYM(CopyDataClearBSSAndStart):
    344344    lea SYM(_data_dest_start),a0        | Get start of DATA in RAM
    345     lea SYM(_data_src_start),a2     | Get start of DATA in ROM 
     345    lea SYM(_data_src_start),a2     | Get start of DATA in ROM
    346346    cmpl    a0,a2                   | Are they the same?
    347347    beq.s   NODATACOPY              | Yes, no copy necessary
     
    354354    bcs.s   DATACOPYLOOP                | No, skip
    355355NODATACOPY:
    356        
     356
    357357/* Now, clear BSS */
    358358        lea _clear_start,a0     | Get start of BSS
     
    378378        nop
    379379        trap    #14
    380         bra     MULTI_TASK_EXIT 
    381        
     380        bra     MULTI_TASK_EXIT
     381
    382382END_CODE
    383383
  • c/src/lib/libbsp/m68k/av5282/startup/bspstart.c

    r32b8506 rd4b4664b  
    1818 *
    1919 *  http://www.rtems.com/license/LICENSE.
    20  * 
     20 *
    2121 *  $Id$
    2222 */
     
    2424#include <bsp.h>
    2525#include <string.h>
    26  
     26
    2727/*
    2828 * Cacheable areas
  • c/src/lib/libbsp/m68k/av5282/startup/init5282.c

    r32b8506 rd4b4664b  
    33 *  has been provided by the start.S code. No normal C or RTEMS
    44 *  functions can be called from here.
    5  * 
     5 *
    66 * This routine is pretty simple for the uC5282 because all the hard
    77 * work has been done by the bootstrap dBUG code.
     
    2525    int x;
    2626    int temp = 0;
    27    
     27
    2828    /*Setup the GPIO Registers */
    2929    MCF5282_GPIO_PBCDPAR = 0x80;
     
    3636    MCF5282_GPTA_GPTDDR = 0x0C;
    3737    MCF5282_GPTA_GPTPORT = 0x4;
    38    
     38
    3939    /*Setup the Chip Selects so CS0 is flash */
    4040    MCF5282_CS0_CSAR =(0xff800000 & 0xffff0000)>>16;
     
    5555        }
    5656        /* set ip ( bit 3 ) in dacr */
    57         MCF5282_SDRAMC_DACR0 |= (0x00000008) ; 
     57        MCF5282_SDRAMC_DACR0 |= (0x00000008) ;
    5858        /* init precharge */
    5959        *((short *)MM_SDRAM_BASE) = 0;
    6060        /* set RE in dacr */
    61         MCF5282_SDRAMC_DACR0 |= (0x00008000); 
     61        MCF5282_SDRAMC_DACR0 |= (0x00008000);
    6262        /* wait */
    6363        for(x=0; x<20000; x++)
     
    7373        }
    7474        *((unsigned long*)MM_SDRAM_BASE)=0x12345678;
    75    
     75
    7676    /* Copy the interrupt vector table to address 0x0 in SDRAM */
    7777    {
  • c/src/lib/libbsp/m68k/csb360/console/console-io.c

    r32b8506 rd4b4664b  
    5555        continue;
    5656    }
    57    
     57
    5858    uart->udata = ch;
    5959    for (i = 0; i < 1000; i++) g_cnt++;
     
    6161
    6262/*
    63  *  console_inbyte_nonblocking 
     63 *  console_inbyte_nonblocking
    6464 *
    6565 *  This routine polls for a character.
  • c/src/lib/libbsp/m68k/csb360/network/network.c

    r32b8506 rd4b4664b  
    88 *  rtems_enet_driver_attach determines which one to use. Currently,
    99 *  only one may be used at a time.
    10  * 
     10 *
    1111 *  Based on the MC68360 network driver by
    1212 *  W. Eric Norum
     
    134134    rtems_id                rxDaemonTid;
    135135    rtems_id                txDaemonTid;
    136    
     136
    137137    /*
    138138     * Statistics
     
    147147    unsigned long   rxOverrun;
    148148    unsigned long   rxTruncated;
    149    
     149
    150150    unsigned long   txInterrupts;
    151151    unsigned long   txDeferred;
     
    163163{
    164164    printf("**************************************************************\n");
    165    printf("ecr:   0x%08x  eir:   0x%08x  eimr:  0x%08x  ivsr:  0x%08x\n\r", 
    166           g_enet_regs->ecr, g_enet_regs->eir,     
    167           g_enet_regs->eimr, g_enet_regs->ivsr); 
    168    printf("rdar:  0x%08x  tdar:  0x%08x  mmfr:  0x%08x  mscr:  0x%08x\n\r", 
    169           g_enet_regs->rdar, g_enet_regs->tdar,     
    170           g_enet_regs->mmfr, g_enet_regs->mscr); 
    171    printf("frbr:  0x%08x  frsr:  0x%08x  tfwr:  0x%08x  tfsr:  0x%08x\n\r", 
    172           g_enet_regs->frbr, g_enet_regs->frsr,     
    173           g_enet_regs->tfwr, g_enet_regs->tfsr); 
    174    printf("rcr:   0x%08x  mflr:  0x%08x  tcr:   0x%08x  malr:  0x%08x\n\r", 
     165   printf("ecr:   0x%08x  eir:   0x%08x  eimr:  0x%08x  ivsr:  0x%08x\n\r",
     166          g_enet_regs->ecr, g_enet_regs->eir,
     167          g_enet_regs->eimr, g_enet_regs->ivsr);
     168   printf("rdar:  0x%08x  tdar:  0x%08x  mmfr:  0x%08x  mscr:  0x%08x\n\r",
     169          g_enet_regs->rdar, g_enet_regs->tdar,
     170          g_enet_regs->mmfr, g_enet_regs->mscr);
     171   printf("frbr:  0x%08x  frsr:  0x%08x  tfwr:  0x%08x  tfsr:  0x%08x\n\r",
     172          g_enet_regs->frbr, g_enet_regs->frsr,
     173          g_enet_regs->tfwr, g_enet_regs->tfsr);
     174   printf("rcr:   0x%08x  mflr:  0x%08x  tcr:   0x%08x  malr:  0x%08x\n\r",
    175175          g_enet_regs->rcr, g_enet_regs->mflr,
    176           g_enet_regs->tcr, g_enet_regs->malr); 
    177    printf("maur:  0x%08x  htur:  0x%08x  htlr:  0x%08x  erdsr: 0x%08x\n\r", 
    178           g_enet_regs->maur, g_enet_regs->htur,     
    179           g_enet_regs->htlr, g_enet_regs->erdsr); 
    180    printf("etdsr: 0x%08x  emrbr: 0x%08x\n\r", 
    181           g_enet_regs->etdsr, g_enet_regs->emrbr); 
     176          g_enet_regs->tcr, g_enet_regs->malr);
     177   printf("maur:  0x%08x  htur:  0x%08x  htlr:  0x%08x  erdsr: 0x%08x\n\r",
     178          g_enet_regs->maur, g_enet_regs->htur,
     179          g_enet_regs->htlr, g_enet_regs->erdsr);
     180   printf("etdsr: 0x%08x  emrbr: 0x%08x\n\r",
     181          g_enet_regs->etdsr, g_enet_regs->emrbr);
    182182}
    183183
     
    186186
    187187/*#define cp printk("%s:%d\n\r", __FUNCTION__, __LINE__) */
    188 #define cp 
     188#define cp
    189189#define mcf5272_bd_allocate(_n_) malloc((_n_) * sizeof(bd_t), 0, M_NOWAIT)
    190190
     
    237237     */
    238238    g_enet_regs->ecr=0x1;
    239    
     239
    240240    /*
    241241     * Set the TX and RX fifo sizes. For now, we'll split it evenly
     
    245245       g_enet_regs->x_fstart = 0;
    246246    */
    247    
     247
    248248    /* Copy mac address to device */
    249    
     249
    250250    hwaddr = sc->arpcom.ac_enaddr;
    251    
     251
    252252    g_enet_regs->malr = (hwaddr[0] << 24 |
    253253                         hwaddr[1] << 16 |
     
    262262    g_enet_regs->htlr = 0;
    263263    g_enet_regs->htur  = 0;
    264    
     264
    265265    /*
    266266     * Set up receive buffer size
    267267     */
    268268    g_enet_regs->emrbr = 0x5f0; /* set to 1520 */
    269    
     269
    270270    /*
    271271     * Allocate mbuf pointers
    272272     */
    273     sc->rxMbuf = malloc (sc->rxBdCount * sizeof *sc->rxMbuf, 
     273    sc->rxMbuf = malloc (sc->rxBdCount * sizeof *sc->rxMbuf,
    274274                         M_MBUF, M_NOWAIT);
    275     sc->txMbuf = malloc (sc->txBdCount * sizeof *sc->txMbuf, 
     275    sc->txMbuf = malloc (sc->txBdCount * sizeof *sc->txMbuf,
    276276                         M_MBUF, M_NOWAIT);
    277277    if (!sc->rxMbuf || !sc->txMbuf) {
    278278        rtems_panic ("No memory for mbuf pointers");
    279279    }
    280    
     280
    281281    /*
    282282     * Set receiver and transmitter buffer descriptor bases
     
    286286    g_enet_regs->erdsr = (int)sc->rxBdBase;
    287287    g_enet_regs->etdsr = (int)sc->txBdBase;
    288    
     288
    289289    /*
    290290     * Set up Receive Control Register:
     
    295295     */
    296296    g_enet_regs->rcr = 0x00000004;
    297    
     297
    298298    /*
    299299     * Set up Transmit Control Register:
     
    302302     */
    303303    g_enet_regs->tcr = 0x00000004;
    304    
    305     /*
    306      * Set MII speed to 2.5 MHz for 25 Mhz system clock 
     304
     305    /*
     306     * Set MII speed to 2.5 MHz for 25 Mhz system clock
    307307     */
    308308    g_enet_regs->mscr = 0x0a;
    309309    g_enet_regs->mmfr = 0x58021000;
    310    
     310
    311311    /*
    312312     * Set up receive buffer descriptors
     
    315315        (sc->rxBdBase + i)->status = 0;
    316316    }
    317  
     317
    318318    /*
    319319     * Set up transmit buffer descriptors
     
    326326    sc->txBdHead = sc->txBdTail = 0;
    327327    sc->txBdActiveCount = 0;
    328  
     328
    329329    /*
    330330     * Mask all FEC interrupts and clear events
    331331     */
    332     g_enet_regs->eimr = (MCF5272_ENET_EIR_TXF | 
     332    g_enet_regs->eimr = (MCF5272_ENET_EIR_TXF |
    333333                        MCF5272_ENET_EIR_RXF);
    334334    g_enet_regs->eir = ~0;
     
    342342    /* Configure ethernet interrupts */
    343343    icr = g_intctrl_regs->icr3;
    344     icr = icr & ~((MCF5272_ICR3_ERX_MASK | MCF5272_ICR3_ERX_PI) | 
     344    icr = icr & ~((MCF5272_ICR3_ERX_MASK | MCF5272_ICR3_ERX_PI) |
    345345                  (MCF5272_ICR3_ETX_MASK | MCF5272_ICR3_ETX_PI));
    346346    icr |= ((MCF5272_ICR3_ERX_IPL(BSP_INTLVL_ERX) | MCF5272_ICR3_ERX_PI)|
    347347            (MCF5272_ICR3_ETX_IPL(BSP_INTLVL_ETX) | MCF5272_ICR3_ETX_PI));
    348348    g_intctrl_regs->icr3 = icr;
    349    
     349
    350350}
    351351
     
    367367    int nRetired;
    368368    struct mbuf *m, *n;
    369    
     369
    370370    i = sc->txBdTail;
    371371    nRetired = 0;
     
    437437    bd_t *rxBd;
    438438    int rxBdIndex;
    439    
     439
    440440    /*
    441441     * Allocate space for incoming packets and start reception
     
    455455        }
    456456    }
    457    
     457
    458458    /*
    459459     * Input packet handling loop
     
    462462    for (;;) {
    463463        rxBd = sc->rxBdBase + rxBdIndex;
    464        
     464
    465465        /*
    466466         * Wait for packet if there's not one ready
     
    471471             */
    472472            g_enet_regs->eir = MCF5272_ENET_EIR_RXF;
    473            
     473
    474474            /*
    475475             * Wait for packet
     
    481481            while ((status = rxBd->status) & MCF5272_BD_EMPTY) {
    482482                rtems_event_set events;
    483                
     483
    484484                /*
    485485                 * Unmask RXF (Full frame received) event
    486486                 */
    487487                g_enet_regs->eir |= MCF5272_ENET_EIR_RXF;
    488                
     488
    489489                rtems_bsdnet_event_receive (INTERRUPT_EVENT,
    490490                                            RTEMS_WAIT|RTEMS_EVENT_ANY,
     
    495495        }
    496496    cp;
    497        
     497
    498498        /*
    499499         * Check that packet is valid
     
    505505             */
    506506            struct ether_header *eh;
    507            
     507
    508508            m = sc->rxMbuf[rxBdIndex];
    509509            m->m_len = m->m_pkthdr.len = (rxBd->length -
     
    513513            m->m_data += sizeof(struct ether_header);
    514514            ether_input (ifp, eh, m);
    515            
     515
    516516            /*
    517517             * Allocate a new mbuf
     
    572572    int nAdded;
    573573    cp;
    574    
     574
    575575    /*
    576576     * Free up buffer descriptors
    577577     */
    578578    mcf5272_enet_retire_tx_bd (sc);
    579    
     579
    580580    /*
    581581     * Set up the transmit buffer descriptors.
     
    597597             */
    598598            g_enet_regs->eir = MCF5272_ENET_EIR_TXF;
    599            
     599
    600600            /*
    601601             * Wait for buffer descriptor to become available.
     
    613613            while ((sc->txBdActiveCount + nAdded) == sc->txBdCount) {
    614614                rtems_event_set events;
    615                
     615
    616616                cp;
    617617                /*
     
    628628            }
    629629        }
    630        
     630
    631631        /*
    632632         * Don't set the READY flag till the
     
    635635        status = nAdded ? MCF5272_BD_READY : 0;
    636636        cp;
    637        
     637
    638638        /*
    639639         *  FIXME: Why not deal with empty mbufs at at higher level?
     
    651651            txBd->buffer = mtod (m, void *);
    652652            txBd->length = m->m_len;
    653            
     653
    654654            sc->txMbuf[sc->txBdHead] = m;
    655655            nAdded++;
     
    674674            */
    675675        }
    676    
     676
    677677        /*
    678678         * Set the transmit buffer status.
     
    710710    struct mbuf *m;
    711711    rtems_event_set events;
    712    
     712
    713713    cp;
    714714    for (;;) {
     
    716716         * Wait for packet
    717717         */
    718         rtems_bsdnet_event_receive (START_TRANSMIT_EVENT, 
    719                                     RTEMS_EVENT_ANY | RTEMS_WAIT, 
    720                                     RTEMS_NO_TIMEOUT, 
     718        rtems_bsdnet_event_receive (START_TRANSMIT_EVENT,
     719                                    RTEMS_EVENT_ANY | RTEMS_WAIT,
     720                                    RTEMS_NO_TIMEOUT,
    721721                                    &events);
    722722        cp;
     
    747747{
    748748    struct mcf5272_enet_struct *sc = ifp->if_softc;
    749    
     749
    750750    cp;
    751751    rtems_event_send (sc->txDaemonTid, START_TRANSMIT_EVENT);
     
    760760    struct mcf5272_enet_struct *sc = arg;
    761761    struct ifnet *ifp = &sc->arpcom.ac_if;
    762    
     762
    763763    if (sc->txDaemonTid == 0) {
    764        
     764
    765765        /*
    766766         * Set up SCC hardware
    767767         */
    768768        mcf5272_enet_initialize_hardware (sc);
    769        
     769
    770770        /*
    771771         * Start driver tasks
    772772         */
    773         sc->txDaemonTid = rtems_bsdnet_newproc("SCtx", 
    774                                                4096, 
    775                                                mcf5272_enet_txDaemon, 
     773        sc->txDaemonTid = rtems_bsdnet_newproc("SCtx",
     774                                               4096,
     775                                               mcf5272_enet_txDaemon,
    776776                                               sc);
    777         sc->rxDaemonTid = rtems_bsdnet_newproc("SCrx", 
    778                                                4096, 
    779                                                mcf5272_enet_rxDaemon, 
     777        sc->rxDaemonTid = rtems_bsdnet_newproc("SCrx",
     778                                               4096,
     779                                               mcf5272_enet_rxDaemon,
    780780                                               sc);
    781        
    782     }
    783    
     781
     782    }
     783
    784784    /*
    785785     * Set flags appropriately
     
    790790        g_enet_regs->rcr &= ~0x8;
    791791    }
    792  
     792
    793793    /*
    794794     * Tell the world that we're running.
    795795     */
    796796    ifp->if_flags |= IFF_RUNNING;
    797    
     797
    798798    /*
    799799     * Enable receiver and transmitter
     
    807807{
    808808    struct ifnet *ifp = &sc->arpcom.ac_if;
    809    
     809
    810810    ifp->if_flags &= ~IFF_RUNNING;
    811    
     811
    812812    /*
    813813     * Shut down receiver and transmitter
     
    833833    printf ("       Truncated:%-8lu\n", sc->rxTruncated);
    834834/*    printf ("          Discarded:%-8lu\n", (unsigned long)mcf5272.scc1p.un.ethernet.disfc); */
    835    
     835
    836836    printf ("      Tx Interrupts:%-8lu", sc->txInterrupts);
    837837    printf ("        Deferred:%-8lu", sc->txDeferred);
     
    853853    struct mcf5272_enet_struct *sc = ifp->if_softc;
    854854    int error = 0;
    855    
     855
    856856    switch (command) {
    857857    case SIOCGIFADDR:
     
    859859        ether_ioctl (ifp, command, data);
    860860        break;
    861        
     861
    862862    case SIOCSIFFLAGS:
    863863        switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) {
     
    865865            mcf5272_enet_stop (sc);
    866866            break;
    867            
     867
    868868        case IFF_UP:
    869869            mcf5272_enet_init (sc);
    870870            break;
    871            
     871
    872872        case IFF_UP | IFF_RUNNING:
    873873            mcf5272_enet_stop (sc);
    874874            mcf5272_enet_init (sc);
    875875            break;
    876            
     876
    877877        default:
    878878            break;
    879879        }
    880880        break;
    881        
     881
    882882    case SIO_RTEMS_SHOW_STATS:
    883883        enet_stats (sc);
    884884        break;
    885        
     885
    886886        /*
    887887         * FIXME: All sorts of multicast commands need to be added here!
     
    903903    int unitNumber;
    904904    char *unitName;
    905    
     905
    906906    /*
    907907     * Parse driver name
     
    911911        return 0;
    912912    }
    913    
     913
    914914    /*
    915915     * Is driver free?
     
    926926        return 0;
    927927    }
    928    
     928
    929929    /*
    930930     * Process options
     
    955955    }
    956956    sc->acceptBroadcast = !config->ignore_broadcast;
    957    
     957
    958958    /*
    959959     * Set up network interface values
     
    971971        ifp->if_snd.ifq_maxlen = ifqmaxlen;
    972972    }
    973    
     973
    974974    /*
    975975     * Attach the interface
  • c/src/lib/libbsp/m68k/csb360/start/start.S

    r32b8506 rd4b4664b  
    1313 *    Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russia
    1414 *    Author: Victor V. Vengerov <vvv@oktet.ru>
    15  *     
     15 *
    1616 *  Based on work:
    1717 *    David Fiddes, D.J@fiddes.surfaid.org
     
    318318                                        | going here from monitor or with
    319319                                        | BDM interface assistance)
    320        
     320
    321321        /*
    322322         * Remainder of the startup code is handled by C code
     
    356356
    357357
    358        
     358
    359359# Wait forever
    360360_stop:
     
    390390_avec3_int:
    391391        nop
    392         jmp     _unexp_int 
     392        jmp     _unexp_int
    393393
    394394_avec4_int:
  • c/src/lib/libbsp/m68k/csb360/startup/init5272.c

    r32b8506 rd4b4664b  
    2525 *
    2626 *  http://www.rtems.com/license/LICENSE.
    27  * 
     27 *
    2828 *  $Id$
    2929 */
     
    108108    /* Set RAM Base Address register */
    109109    m68k_set_srambar((BSP_RAMBAR & MCF5272_RAMBAR_BA) | MCF5272_RAMBAR_V);
    110    
     110
    111111    /* Set System Control Register:
    112112     * Enet has highest priority, 16384 bus cycles before timeout
    113113     */
    114114    g_sim_regs->scr = (MCF5272_SCR_HWR_16384);
    115    
     115
    116116    /* System Protection Register:
    117117     * Enable Hardware watchdog timer.
     
    137137    }
    138138    m68k_set_vbr(BSP_RAMBAR);
    139    
    140    
     139
     140
    141141    /*
    142142     * Setup ACRs so that if cache turned on, periphal accesses
     
    159159    m68k_set_cacr(MCF5272_CACR_CENB |
    160160                  MCF5272_CACR_DCM);       /* Default is not cached */
    161  
     161
    162162  /*
    163163   * Copy data, clear BSS, switch stacks and call boot_card()
  • c/src/lib/libbsp/m68k/gen68360/include/bsp.h

    r32b8506 rd4b4664b  
    9393 */
    9494#if defined(PGH360)
    95 /* 
     95/*
    9696 * logical SPI addresses of SPI slaves available
    9797 */
     
    100100#define PGH360_SPI_ADDR_DISP4_CTRL 2
    101101
    102 /* 
     102/*
    103103 * Port B bit locations of SPI slave selects
    104104 */
  • c/src/lib/libbsp/m68k/gen68360/spi/m360_spi.c

    r32b8506 rd4b4664b  
    2929static m360_spi_softc_t *m360_spi_softc_ptr;
    3030/*
    31  * this is a dummy receive buffer for sequences, 
     31 * this is a dummy receive buffer for sequences,
    3232 * where only send data are available
    3333 */
     
    140140     * allow interrupts, when receiver is not empty
    141141     */
    142     m360.spim = (M360_SPIE_TXE | M360_SPIE_TXB | 
     142    m360.spim = (M360_SPIE_TXE | M360_SPIE_TXB |
    143143                 M360_SPIE_BSY | M360_SPIE_MME);
    144144
     
    166166
    167167  act_status = m360.spie;
    168   if ((act_status  & (M360_SPIE_TXE | M360_SPIE_TXB | 
     168  if ((act_status  & (M360_SPIE_TXE | M360_SPIE_TXB |
    169169                      M360_SPIE_BSY | M360_SPIE_MME))!= M360_SPIE_TXB) {
    170170#if defined(DEBUG)
     
    200200{
    201201  m360_spi_softc_t *softc_ptr = m360_spi_softc_ptr;
    202  
    203   /*
    204    * disable interrupt mask 
     202
     203  /*
     204   * disable interrupt mask
    205205   */
    206206  m360.spim = 0;
    207207  if (softc_ptr->initialized) {
    208208    rtems_semaphore_release(softc_ptr->irq_sema_id);
    209   } 
     209  }
    210210}
    211211
     
    240240    rc = rtems_semaphore_create(rtems_build_name('s','p','i','s'),
    241241                                0,
    242                                 RTEMS_FIFO 
     242                                RTEMS_FIFO
    243243                                | RTEMS_SIMPLE_BINARY_SEMAPHORE,
    244244                                0,
     
    287287  }
    288288}
    289  
     289
    290290/*=========================================================================*\
    291291| Function:                                                                 |
     
    308308  m360_spi_softc_t *softc_ptr = &(((m360_spi_desc_t *)(bh))->softc);
    309309  rtems_status_code rc = RTEMS_SUCCESSFUL;
    310  
     310
    311311#if defined(DEBUG)
    312312  printk("m360_spi_init called... ");
     
    318318   * FIXME: set default mode in SPMODE
    319319   */
    320  
     320
    321321  /*
    322322   * allocate BDs (1x RX, 1x TX)
     
    338338  m360.spip.tfcr  = M360_RFCR_MOT | M360_RFCR_DMA_SPACE;
    339339  m360.spip.mrblr = 2;
    340  
     340
    341341  /*
    342342   * issue "InitRxTx" Command to CP
     
    355355     * LINE      PAR  DIR  DAT
    356356     * -----------------------
    357      * MOSI       1    1    x 
     357     * MOSI       1    1    x
    358358     * MISO       1    1    x
    359359     * CLK        1    1    x
    360360     */
    361    
     361
    362362    /* set Port B Pin Assignment Register... */
    363     m360.pbpar = 
     363    m360.pbpar =
    364364      m360.pbpar
    365       | M360_PB_SPI_MISO_MSK 
    366       | M360_PB_SPI_MOSI_MSK 
     365      | M360_PB_SPI_MISO_MSK
     366      | M360_PB_SPI_MOSI_MSK
    367367      | M360_PB_SPI_CLK_MSK;
    368    
     368
    369369    /* set Port B Data Direction Register... */
    370     m360.pbdir = 
    371       m360.pbdir 
    372       | M360_PB_SPI_MISO_MSK 
    373       | M360_PB_SPI_MOSI_MSK 
     370    m360.pbdir =
     371      m360.pbdir
     372      | M360_PB_SPI_MISO_MSK
     373      | M360_PB_SPI_MOSI_MSK
    374374      | M360_PB_SPI_CLK_MSK;
    375375  }
     
    427427      softc_ptr->rx_bd->buffer = m360_spi_dummy_rxbuf;
    428428      softc_ptr->rx_bd->length = 0;
    429       softc_ptr->rx_bd->status = (M360_BD_EMPTY | M360_BD_WRAP | 
     429      softc_ptr->rx_bd->status = (M360_BD_EMPTY | M360_BD_WRAP |
    430430                                  M360_BD_CONTINUOUS);
    431431    }
     
    447447      softc_ptr->tx_bd->buffer = m360_spi_dummy_rxbuf;
    448448      softc_ptr->tx_bd->length = len;
    449       softc_ptr->tx_bd->status = (M360_BD_READY | M360_BD_WRAP | 
     449      softc_ptr->tx_bd->status = (M360_BD_READY | M360_BD_WRAP |
    450450                                  M360_BD_CONTINUOUS);
    451451    }
     
    567567    }
    568568  }
    569  
     569
    570570  if (rc == RTEMS_SUCCESSFUL) {
    571571    /*
     
    606606  switch(cmd) {
    607607  case RTEMS_LIBI2C_IOCTL_SET_TFRMODE:
    608     ret_val = 
     608    ret_val =
    609609      -m360_spi_set_tfr_mode(bh,
    610610                                (const rtems_libi2c_tfr_mode_t *)arg);
    611611    break;
    612612  case RTEMS_LIBI2C_IOCTL_READ_WRITE:
    613     ret_val = 
     613    ret_val =
    614614      m360_spi_read_write_bytes(bh,
    615615                                ((rtems_libi2c_read_write_t *)arg)->rd_buf,
     
    656656   * GPIO1[25] is SPI_A1
    657657   * GPIO1[26] is SPI_A2
    658    * set pins to address 
     658   * set pins to address
    659659   */
    660660  switch(addr) {
     
    663663    break;
    664664  case PGH360_SPI_ADDR_DISP4_DATA:
    665     m360.pbdat = (m360.pbdat 
    666                   & ~(PGH360_PB_SPI_DISP4_CE_MSK | 
     665    m360.pbdat = (m360.pbdat
     666                  & ~(PGH360_PB_SPI_DISP4_CE_MSK |
    667667                      PGH360_PB_SPI_DISP4_RS_MSK));
    668668    break;
    669669  case PGH360_SPI_ADDR_DISP4_CTRL:
    670     m360.pbdat = (m360.pbdat 
    671                   & ~(PGH360_PB_SPI_DISP4_CE_MSK) 
     670    m360.pbdat = (m360.pbdat
     671                  & ~(PGH360_PB_SPI_DISP4_CE_MSK)
    672672                  |   PGH360_PB_SPI_DISP4_RS_MSK);
    673673    break;
     
    722722#endif
    723723#if defined(PGH360)
    724     m360.pbdat = (m360.pbdat 
     724    m360.pbdat = (m360.pbdat
    725725                  | PGH360_PB_SPI_DISP4_CE_MSK
    726726                  | PGH360_PB_SPI_EEP_CE_MSK);
     
    789789   * init port pins used to address/select SPI devices
    790790   */
    791  
     791
    792792#if defined(PGH360)
    793793
     
    800800   * DISP4_RS   0    1 active
    801801   */
    802  
     802
    803803  /* set Port B Pin Assignment Register... */
    804   m360.pbpar = 
    805     (m360.pbpar 
    806      & ~(PGH360_PB_SPI_EEP_CE_MSK 
     804  m360.pbpar =
     805    (m360.pbpar
     806     & ~(PGH360_PB_SPI_EEP_CE_MSK
    807807         | PGH360_PB_SPI_DISP4_CE_MSK
    808808         | PGH360_PB_SPI_DISP4_RS_MSK));
    809  
     809
    810810    /* set Port B Data Direction Register... */
    811   m360.pbdir = 
    812     m360.pbdir 
    813     | PGH360_PB_SPI_EEP_CE_MSK 
     811  m360.pbdir =
     812    m360.pbdir
     813    | PGH360_PB_SPI_EEP_CE_MSK
    814814    | PGH360_PB_SPI_DISP4_CE_MSK
    815815    | PGH360_PB_SPI_DISP4_RS_MSK;
    816  
     816
    817817  /* set Port B Data Register to inactive CE state */
    818   m360.pbdat = 
    819     m360.pbdat 
     818  m360.pbdat =
     819    m360.pbdat
    820820    | PGH360_PB_SPI_DISP4_CE_MSK
    821821    | PGH360_PB_SPI_DISP4_RS_MSK;
  • c/src/lib/libbsp/m68k/gen68360/spi/m360_spi.h

    r32b8506 rd4b4664b  
    3737
    3838typedef struct {
    39   rtems_libi2c_bus_t  bus_desc; 
     39  rtems_libi2c_bus_t  bus_desc;
    4040  m360_spi_softc_t softc;
    4141} m360_spi_desc_t;
  • c/src/lib/libbsp/m68k/gen68360/startup/init68360.c

    r32b8506 rd4b4664b  
    466466          code_loc = (void *)ramtest_exec;
    467467          if ((ram_base < ram_end) &&
    468             !((ram_base <= code_loc) && (code_loc < ram_end))) {           
     468            !((ram_base <= code_loc) && (code_loc < ram_end))) {
    469469            ramtest_exec(ram_base,ram_end);
    470470          }
     
    478478                M68Kvec[i] = vbr[i];
    479479        m68k_set_vbr (M68Kvec);
    480        
     480
    481481        /*
    482482         * Step 14: More system initialization
  • c/src/lib/libbsp/m68k/genmcf548x/network/network.c

    r32b8506 rd4b4664b  
    6868#define FEC_WATCHDOG_TIMEOUT 5 /* check media every 5 seconds */
    6969/*
    70  * buffer descriptor handling 
     70 * buffer descriptor handling
    7171 */
    7272
     
    116116 * since a single frame often uses four or more buffer descriptors.
    117117 */
    118 #define RX_BUF_COUNT     DMA_BD_RX_NUM 
     118#define RX_BUF_COUNT     DMA_BD_RX_NUM
    119119#define TX_BUF_COUNT     DMA_BD_TX_NUM
    120120#define TX_BD_PER_BUF    1
     
    218218  rtems_id                rxDaemonTid;
    219219  rtems_id                txDaemonTid;
    220  
     220
    221221  /*
    222222   * MDIO/Phy info
     
    275275    m->m_pkthdr.rcvif = ifp;
    276276    sc->rxMbuf[rxBdIndex] = m;
    277     rtems_cache_invalidate_multiple_data_lines(mtod(m,const void *), 
     277    rtems_cache_invalidate_multiple_data_lines(mtod(m,const void *),
    278278                                               ETHER_MAX_LEN);
    279279    SET_BD_BUFFER(sc->rxBd+rxBdIndex,mtod(m, void *));
    280     SET_BD_LENGTH(sc->rxBd+rxBdIndex,ETHER_MAX_LEN); 
     280    SET_BD_LENGTH(sc->rxBd+rxBdIndex,ETHER_MAX_LEN);
    281281    SET_BD_STATUS(sc->rxBd+rxBdIndex,
    282                   MCF548X_FEC_RBD_EMPTY 
     282                  MCF548X_FEC_RBD_EMPTY
    283283                  | MCF548X_FEC_RBD_INT
    284                   | ((rxBdIndex == sc->rxBdCount-1) 
    285                      ? MCF548X_FEC_RBD_WRAP 
     284                  | ((rxBdIndex == sc->rxBdCount-1)
     285                     ? MCF548X_FEC_RBD_WRAP
    286286                     : 0));
    287287  }
     
    402402    * Set physical address
    403403    */
    404     MCF548X_FEC_PALR(chan) = ((mac[0] << 24) + 
    405                               (mac[1] << 16) + 
    406                               (mac[2] <<  8) + 
     404    MCF548X_FEC_PALR(chan) = ((mac[0] << 24) +
     405                              (mac[1] << 16) +
     406                              (mac[2] <<  8) +
    407407                              mac[3]);
    408     MCF548X_FEC_PAUR(chan) = ((mac[4] << 24) 
     408    MCF548X_FEC_PAUR(chan) = ((mac[4] << 24)
    409409                              + (mac[5] << 16)) + 0x8808;
    410410
     
    438438  * programming the FEC's MII data register.
    439439  */
    440   MCF548X_FEC_MMFR(chan) = (MCF548X_FEC_MMFR_ST_01    | 
    441                             MCF548X_FEC_MMFR_OP_READ  | 
    442                             MCF548X_FEC_MMFR_TA_10    | 
    443                             MCF548X_FEC_MMFR_PA(phyAddr) | 
     440  MCF548X_FEC_MMFR(chan) = (MCF548X_FEC_MMFR_ST_01    |
     441                            MCF548X_FEC_MMFR_OP_READ  |
     442                            MCF548X_FEC_MMFR_TA_10    |
     443                            MCF548X_FEC_MMFR_PA(phyAddr) |
    444444                            MCF548X_FEC_MMFR_RA(regAddr));
    445445
     
    495495  int timeout  = 0xffff;
    496496
    497   MCF548X_FEC_MMFR(chan) = (MCF548X_FEC_MMFR_ST_01    | 
    498                             MCF548X_FEC_MMFR_OP_WRITE | 
    499                             MCF548X_FEC_MMFR_TA_10    | 
    500                             MCF548X_FEC_MMFR_PA(phyAddr) | 
    501                             MCF548X_FEC_MMFR_RA(regAddr) | 
     497  MCF548X_FEC_MMFR(chan) = (MCF548X_FEC_MMFR_ST_01    |
     498                            MCF548X_FEC_MMFR_OP_WRITE |
     499                            MCF548X_FEC_MMFR_TA_10    |
     500                            MCF548X_FEC_MMFR_PA(phyAddr) |
     501                            MCF548X_FEC_MMFR_RA(regAddr) |
    502502                            MCF548X_FEC_MMFR_DATA(data));
    503503
     
    547547  MCF548X_FEC_FECRFSR(chan) = ~0;
    548548  MCF548X_FEC_FECTFSR(chan) = ~0;
    549  
     549
    550550  /*
    551551   * reset the FIFOs
     
    556556
    557557  MCF548X_FEC_FRST(chan) = 0x01000000;
    558  
     558
    559559  /*
    560560   * Issue a reset command to the FEC chip
    561561   */
    562562  MCF548X_FEC_ECR(chan) |= MCF548X_FEC_ECR_RESET;
    563  
     563
    564564  /*
    565565   * wait at least 16 clock cycles
    566566   */
    567567  for (delay = 0;delay < 16*4;delay++) {};
    568  
     568
    569569  return true;
    570570}
     
    586586  int            counter = 0xffff;
    587587  int chan     = sc->chan;
    588  
     588
    589589
    590590#if defined(ETH_DEBUG)
     
    648648  MCF548X_FEC_ECR(chan) &= ~(MCF548X_FEC_ECR_ETHER_EN);
    649649
    650   /* 
     650  /*
    651651   * cleanup all buffers
    652652   */
     
    687687    sc->rxOverrun++;
    688688  }
    689   /* 
     689  /*
    690690   * fatal error ocurred?
    691691   */
     
    705705  if(MCDMA_GET_PENDING(sc->rxDmaChan)) {
    706706    MCDMA_CLR_PENDING(sc->rxDmaChan);
    707    
    708     mcdma_glue_irq_disable(sc->rxDmaChan);/*Disable receive ints*/   
     707
     708    mcdma_glue_irq_disable(sc->rxDmaChan);/*Disable receive ints*/
    709709    sc->rxInterrupts++;                 /* Rx int has occurred */
    710710    rtems_event_send(sc->rxDaemonTid, INTERRUPT_EVENT);
     
    723723
    724724    MCDMA_CLR_PENDING(sc->txDmaChan);
    725    
     725
    726726    mcdma_glue_irq_disable(sc->txDmaChan);/*Disable tx ints*/
    727    
     727
    728728    sc->txInterrupts++; /* Tx int has occurred */
    729    
    730     rtems_event_send(sc->txDaemonTid, INTERRUPT_EVENT);   
     729
     730    rtems_event_send(sc->txDaemonTid, INTERRUPT_EVENT);
    731731  }
    732732}
     
    754754   * from fecExceptionHandler(TFINT).
    755755   */
    756  
     756
    757757  while ((sc->txBdActiveCount > 0) &&
    758          (force || 
     758         (force ||
    759759          ((MCF548X_FEC_TBD_READY & GET_BD_STATUS(sc->txBd+sc->txBdTail))
    760760           == 0x0))) {
     
    769769    if(++sc->txBdTail >= sc->txBdCount) {
    770770      sc->txBdTail = 0;
    771     }   
     771    }
    772772  }
    773773}
     
    805805    */
    806806    if((sc->txBdActiveCount + nAdded) == sc->txBdCount) {
    807      
     807
    808808      /*
    809809       * Clear old events
    810810       */
    811       MCDMA_CLR_PENDING(sc->txDmaChan);     
     811      MCDMA_CLR_PENDING(sc->txDmaChan);
    812812      /*
    813813       * Wait for buffer descriptor to become available.
     
    823823       */
    824824      mcf548x_fec_retire_tbd(sc,false);
    825      
     825
    826826      while((sc->txBdActiveCount + nAdded) == sc->txBdCount) {
    827827        mcdma_glue_irq_enable(sc->txDmaChan);
    828         rtems_bsdnet_event_receive(INTERRUPT_EVENT, 
    829                                    RTEMS_WAIT | RTEMS_EVENT_ANY, 
     828        rtems_bsdnet_event_receive(INTERRUPT_EVENT,
     829                                   RTEMS_WAIT | RTEMS_EVENT_ANY,
    830830                                   RTEMS_NO_TIMEOUT, &events);
    831831        mcf548x_fec_retire_tbd(sc,false);
     
    839839      struct mbuf *n;
    840840      MFREE(m, n);
    841       m = n;     
     841      m = n;
    842842      if(l != NULL) {
    843843        l->m_next = m;
     
    848848       * Flush the buffer for this descriptor
    849849       */
    850       rtems_cache_flush_multiple_data_lines((const void *)mtod(m, void *), 
     850      rtems_cache_flush_multiple_data_lines((const void *)mtod(m, void *),
    851851                                            m->m_len);
    852852      /*
     
    860860       * doing this every quarter of BDs is much more efficent
    861861       */
    862       status = (((m->m_next == NULL) 
     862      status = (((m->m_next == NULL)
    863863                 ? MCF548X_FEC_TBD_LAST | MCF548X_FEC_TBD_INT
    864864                 : 0)
    865865                | ((sc->txBdHead == sc->txBdCount-1)
    866866                   ? MCF548X_FEC_TBD_WRAP
    867                    :0 ));     
     867                   :0 ));
    868868      /*
    869869       * Don't set the READY flag till the
     
    875875      else {
    876876        firstBd = thisBd;
    877       }     
     877      }
    878878
    879879      data_ptr = mtod(m, void *);
     
    899899    if(m == NULL) {
    900900      if(nAdded) {
    901         SET_BD_STATUS(firstBd, 
     901        SET_BD_STATUS(firstBd,
    902902                      GET_BD_STATUS(firstBd) | MCF548X_FEC_TBD_READY);
    903903        MCD_continDma(sc->txDmaChan);
    904         sc->txBdActiveCount += nAdded; 
     904        sc->txBdActiveCount += nAdded;
    905905      }
    906906      break;
     
    925925    */
    926926    mcdma_glue_irq_enable(sc->txDmaChan);
    927     rtems_bsdnet_event_receive(START_TRANSMIT_EVENT|INTERRUPT_EVENT, 
    928                                RTEMS_EVENT_ANY | RTEMS_WAIT, 
    929                                RTEMS_NO_TIMEOUT, 
     927    rtems_bsdnet_event_receive(START_TRANSMIT_EVENT|INTERRUPT_EVENT,
     928                               RTEMS_EVENT_ANY | RTEMS_WAIT,
     929                               RTEMS_NO_TIMEOUT,
    930930                               &events);
    931931
     
    975975   */
    976976  rxBdIndex = 0;
    977  
     977
    978978  for (;;) {
    979979    /*
     
    987987    status = GET_BD_STATUS( bd );
    988988    len    = GET_BD_LENGTH( bd );
    989      
     989
    990990    /*
    991991     * Loop through BDs until we find an empty one. This indicates that
     
    993993     */
    994994    while( !(status & MCF548X_FEC_RBD_EMPTY) ) {
    995    
     995
    996996      /*
    997997       * Remember the data pointer from this transfer.
     
    999999      dptr = GET_BD_BUFFER(bd);
    10001000      m    = sc->rxMbuf[rxBdIndex];
    1001       m->m_len = m->m_pkthdr.len = (len 
    1002                                     - sizeof(uint32_t) 
     1001      m->m_len = m->m_pkthdr.len = (len
     1002                                    - sizeof(uint32_t)
    10031003                                    - sizeof(struct ether_header));
    10041004      eh = mtod(m, struct ether_header *);
    10051005      m->m_data += sizeof(struct ether_header);
    10061006      ether_input(ifp, eh, m);
    1007        
     1007
    10081008      /*
    10091009       * Done w/ the BD. Clean it.
    10101010       */
    10111011      sc->rxMbuf[rxBdIndex] = NULL;
    1012        
     1012
    10131013      /*
    10141014       * Add a new buffer to the ring.
     
    10201020
    10211021      sc->rxMbuf[rxBdIndex] = m;
    1022       rtems_cache_invalidate_multiple_data_lines(mtod(m,const void *), 
     1022      rtems_cache_invalidate_multiple_data_lines(mtod(m,const void *),
    10231023                                                 size);
    1024      
     1024
    10251025      SET_BD_BUFFER(bd,mtod(m, void *));
    10261026      SET_BD_LENGTH(bd,size);
     
    10321032                      : 0)
    10331033                    );
    1034        
     1034
    10351035      /*
    10361036       * advance to next BD
     
    10501050     */
    10511051    mcdma_glue_irq_enable(sc->rxDmaChan);
    1052      
    1053     rtems_bsdnet_event_receive (INTERRUPT_EVENT | FATAL_INT_EVENT, 
    1054                                 RTEMS_WAIT | RTEMS_EVENT_ANY, 
     1052
     1053    rtems_bsdnet_event_receive (INTERRUPT_EVENT | FATAL_INT_EVENT,
     1054                                RTEMS_WAIT | RTEMS_EVENT_ANY,
    10551055                                RTEMS_NO_TIMEOUT, &events);
    10561056    if (events & FATAL_INT_EVENT) {
     
    11011101                           | MCF548X_FEC_RCR_FCE
    11021102                           | MCF548X_FEC_RCR_MII_MODE);
    1103  
     1103
    11041104  /*
    11051105   * Set FEC-Lite transmit control register (X_CNTRL)
     
    11841184       * Enable the SmartDMA receive task.
    11851185       */
    1186       mcdma_rc = MCD_startDma 
     1186      mcdma_rc = MCD_startDma
    11871187        (sc->rxDmaChan, /* the channel on which to run the DMA */
    11881188         (void *)sc->rxBd, /* the address to move data from, or buffer-descriptor addr */
     
    12081208        rtems_panic("FEC: cannot start rx DMA");
    12091209      }
    1210       mcdma_rc = MCD_startDma 
     1210      mcdma_rc = MCD_startDma
    12111211        (sc->txDmaChan, /* the channel on which to run the DMA */
    12121212         (void *)sc->txBd, /* the address to move data from, or buffer-descriptor addr */
     
    12511251      sc->rxBd =  SRAM_RXBD_BASE(_SysSramBase,chan);
    12521252      sc->txBd =  SRAM_TXBD_BASE(_SysSramBase,chan);
    1253      
     1253
    12541254      if(!sc->rxBd || !sc->txBd)
    12551255        rtems_panic ("No memory for BDs");
     
    12621262       * Allocate a set of mbuf pointers
    12631263       */
    1264       sc->rxMbuf = 
     1264      sc->rxMbuf =
    12651265        malloc(sc->rxBdCount * sizeof *sc->rxMbuf, M_MBUF, M_NOWAIT);
    1266       sc->txMbuf = 
     1266      sc->txMbuf =
    12671267        malloc(sc->txBdCount * sizeof *sc->txMbuf, M_MBUF, M_NOWAIT);
    1268      
     1268
    12691269      if(!sc->rxMbuf || !sc->txMbuf)
    12701270        rtems_panic ("No memory for mbuf pointers");
     
    12901290      }
    12911291
    1292       MCF548X_INTC_ICRn(MCF548X_FEC_IRQ_VECTOR(chan) % 64) =   
     1292      MCF548X_INTC_ICRn(MCF548X_FEC_IRQ_VECTOR(chan) % 64) =
    12931293        MCF548X_INTC_ICRn_IL(FEC_IRQ_LEVEL) |
    12941294        MCF548X_INTC_ICRn_IP(FEC_IRQ_PRIORITY);
     
    13091309      txTaskName[3] = '0'+chan;
    13101310      rxTaskName[3] = '0'+chan;
    1311       sc->txDaemonTid = rtems_bsdnet_newproc(txTaskName, 4096, 
     1311      sc->txDaemonTid = rtems_bsdnet_newproc(txTaskName, 4096,
    13121312                                             mcf548x_fec_txDaemon, sc);
    1313       sc->rxDaemonTid = rtems_bsdnet_newproc(rxTaskName, 4096, 
     1313      sc->rxDaemonTid = rtems_bsdnet_newproc(rxTaskName, 4096,
    13141314                                             mcf548x_fec_rxDaemon, sc);
    13151315      /*
     
    13181318      MCDMA_CLR_PENDING(sc->rxDmaChan );
    13191319      MCDMA_CLR_PENDING(sc->txDmaChan );
    1320    
     1320
    13211321      /*
    13221322       * start the DMA channels
     
    13601360  printf ("         Overrun:%-8lu", sc->rxOverrun);
    13611361  printf ("       Collision:%-8lu\n", sc->rxCollision);
    1362  
     1362
    13631363  printf ("      Tx Interrupts:%-8lu", sc->txInterrupts);
    13641364  printf ("        Deferred:%-8lu", sc->txDeferred);
     
    13721372/*
    13731373 * restart the driver, reinit the fec
    1374  * this function is responsible to reinitialize the FEC in case a fatal 
     1374 * this function is responsible to reinitialize the FEC in case a fatal
    13751375 * error has ocurred. This is needed, wen a RxFIFO Overrun or a TxFIFO underrun
    13761376 * has ocurred. In these cases, the FEC is automatically disabled, and
    13771377 * both FIFOs must be reset and the BestComm tasks must be restarted
    13781378 *
    1379  * Note: the daemon tasks will continue to run 
     1379 * Note: the daemon tasks will continue to run
    13801380 * (in fact this function will be called in the context of the rx daemon task)
    13811381 */
     
    14311431   */
    14321432  MCDMA_CLR_PENDING( sc->rxDmaChan );
    1433  
     1433
    14341434  /*
    14351435   * start the DMA channels again
     
    14921492                  ? ether_addmulti(ifr, &sc->arpcom)
    14931493                  : ether_delmulti(ifr, &sc->arpcom);
    1494        
     1494
    14951495       if (error == ENETRESET) {
    14961496         if (ifp->if_flags & IFF_RUNNING)
     
    16141614  else {
    16151615    MCF548X_FEC_TCR(chan) |=  MCF548X_FEC_TCR_FDEN;
    1616   }   
     1616  }
    16171617  /*
    16181618   * store current media state for future compares
     
    16301630{
    16311631  mcf548x_fec_mode_adapt(ifp);
    1632   ifp->if_timer    = FEC_WATCHDOG_TIMEOUT; 
     1632  ifp->if_timer    = FEC_WATCHDOG_TIMEOUT;
    16331633}
    16341634
  • c/src/lib/libbsp/m68k/genmcf548x/start/start.S

    r32b8506 rd4b4664b  
    5656.extern _CoreSramBase1
    5757.extern _CoreSramSize1
    58 .extern mcf548x_init 
     58.extern mcf548x_init
    5959.extern boot_card
    6060.extern _SpInit
     
    6565
    6666.global interrupt_vector_table
    67 .global spurious_int_count 
     67.global spurious_int_count
    6868.global start
    6969
     
    340340    move.w      #0x3700,sr              /* disable interrupts */
    341341    jmp         start_init
    342    
     342
    343343/*===============================================================*\
    344344| Sspurious interrupt counter                                     |
     
    346346.align 4
    347347.data                                   /* begin of data section */
    348 PUBLIC (spurious_int_count) 
     348PUBLIC (spurious_int_count)
    349349SYM(spurious_int_count):
    350350    .long   0                           /* spurious interrupt counter */
     
    354354+-----------------------------------------------------------------+
    355355| - stop and disable all interrupts                               |
    356 | - loop forever                                                  | 
     356| - loop forever                                                  |
    357357\*===============================================================*/
    358358.text                                   /* start of text section */
     
    360360PUBLIC (asm_default_interrupt)
    361361SYM(asm_default_interrupt):
    362     nop                                 
    363     stop    #0x3700                     /* stop */ 
     362    nop
     363    stop    #0x3700                     /* stop */
    364364    bra.w   asm_default_interrupt       /* loop forever */
    365365
     
    373373SYM(asm_spurious_interrupt):
    374374    add.l   #1,spurious_int_count
    375     rte 
    376    
     375    rte
     376
    377377/*===============================================================*\
    378378| Function: start_init                                            |
    379379+-----------------------------------------------------------------+
    380 | - Disable all intterupts                                        | 
     380| - Disable all intterupts                                        |
    381381| - Setup the internal SRAM                                       |
    382382| - Initialize mcf548x peripherals                                |
    383383| - Set initial stack pointer                                     |
    384 | - Boot RTEMS                   
     384| - Boot RTEMS
    385385\*===============================================================*/
    386386.align 4
    387387PUBLIC (start_init)
    388388SYM(start_init):
    389    
     389
    390390    move.l  #0x01040100,d0              /* invalidate instruction/data/branch cache, disable all caches */
    391391    movec   d0,cacr
    392    
     392
    393393    move.l  #_CoreSramBase0,d0          /* initialize RAMBAR0 */
    394394    add.l   #0x21,d0                    /* for code & data    */
    395395    movec   d0,rambar0
    396    
     396
    397397    move.l  #_CoreSramBase1,d0          /* initialize RAMBAR1 */
    398398    add.l   #0x21,d0                    /* for code & data    */
     
    401401    move.l  #__MBAR,d0                  /* initialize MBAR */
    402402    movec   d0,mbar
    403      
     403
    404404    move.l  #_CoreSramBase1,d0          /* set sp to end of Core SRAM temporarily */
    405405    add.l   #_CoreSramSize1,d0
    406406    move.l  d0,sp
    407    
     407
    408408    move.l  #0,d0                       /* initialize frame pointer */
    409     movea.l d0,a6 
    410    
     409    movea.l d0,a6
     410
    411411    jsr     mcf548x_init                /* Initialize mcf548x peripherals */
    412412
    413     move.l  #_SpInit,sp                 /* relocate sp */ 
    414      
     413    move.l  #_SpInit,sp                 /* relocate sp */
     414
    415415    clrl    d0                          /* clear d0 */
    416416    movel   d0,a7@-                     /* command line == 0 */
    417  
     417
    418418    jsr     boot_card                   /* boot rtems */
    419419
     
    423423    nop
    424424    nop
    425     halt                               
    426     bra     exit_multitasking 
    427 
    428 .end                                    /* end of start.S module */     
    429    
    430 
    431  
     425    halt
     426    bra     exit_multitasking
     427
     428.end                                    /* end of start.S module */
     429
     430
     431
  • c/src/lib/libbsp/m68k/idp/timer/timer.c

    r32b8506 rd4b4664b  
    1 /* 
     1/*
    22 *  Code Modified for the MC68230 by Doug McBride, Colorado Space Grant College
    33 *
  • c/src/lib/libbsp/m68k/mcf5206elite/i2c/i2c.c

    r32b8506 rd4b4664b  
    7373    if (sc != RTEMS_SUCCESSFUL)
    7474        return I2C_RESOURCE_NOT_AVAILABLE;
    75     sc = i2c_transfer(bus, nmsg, msg, 
     75    sc = i2c_transfer(bus, nmsg, msg,
    7676                      i2c_transfer_sema_done_func, &sema);
    7777    if (sc != RTEMS_SUCCESSFUL)
     
    108108    rtems_status_code sc;
    109109    poll_done_flag = false;
    110     sc = i2c_transfer(bus, nmsg, msg, 
     110    sc = i2c_transfer(bus, nmsg, msg,
    111111                      i2c_transfer_poll_done_func,(void *)&poll_done_flag);
    112112    if (sc != RTEMS_SUCCESSFUL)
  • c/src/lib/libbsp/m68k/mcf5206elite/i2c/i2cdrv.c

    r32b8506 rd4b4664b  
    120120            mcfmbus_select_clock_divider(&mbus, i2cdrv_bus_clock_div_current);
    121121        }
    122         sc = mcfmbus_i2c_transfer(&mbus, qel->nmsg, qel->msg, 
     122        sc = mcfmbus_i2c_transfer(&mbus, qel->nmsg, qel->msg,
    123123                                  i2cdrv_done,qel);
    124124        if (sc != RTEMS_SUCCESSFUL)
  • c/src/lib/libbsp/m68k/mcf52235/console/console.c

    r32b8506 rd4b4664b  
    136136   value and sets it. At the moment this just sets the baud rate.
    137137
    138    Note: The highest baudrate is 115200 as this stays within 
     138   Note: The highest baudrate is 115200 as this stays within
    139139   an error of +/- 5% at 25MHz processor clock
    140140 ***************************************************************************/
     
    335335   Function : IntUartInterruptWrite
    336336
    337    Description : This writes a single character to the appropriate uart 
     337   Description : This writes a single character to the appropriate uart
    338338   channel. This is either called during an interrupt or in the user's task
    339    to initiate a transmit sequence. Calling this routine enables Tx 
     339   to initiate a transmit sequence. Calling this routine enables Tx
    340340   interrupts.
    341341 ***************************************************************************/
     
    455455   Function : IntUartPollRead
    456456
    457    Description : This reads a character from the internal uart. It returns 
     457   Description : This reads a character from the internal uart. It returns
    458458   to the caller without blocking if not character is waiting.
    459459 ***************************************************************************/
     
    469469   Function : IntUartPollWrite
    470470
    471    Description : This writes out each character in the buffer to the 
    472    appropriate internal uart channel waiting till each one is sucessfully 
     471   Description : This writes out each character in the buffer to the
     472   appropriate internal uart channel waiting till each one is sucessfully
    473473   transmitted.
    474474 ***************************************************************************/
     
    531531   Function : console_open
    532532
    533    Description : This actually opens the device depending on the minor 
     533   Description : This actually opens the device depending on the minor
    534534   number set during initialisation. The device specific access routines are
    535535   passed to termios when the devices is opened depending on whether it is
  • c/src/lib/libbsp/m68k/mcf52235/include/bsp.h

    r32b8506 rd4b4664b  
    22 *  mcf52235 BSP header file
    33 */
    4  
     4
    55#ifndef _BSP_H
    66#define _BSP_H
     
    2323/**  Hardware data structure headers                                      **/
    2424#include <mcf5223x/mcf5223x.h>
    25    
     25
    2626/* Declare base address of peripherals area */
    27 #define __IPSBAR ((vuint8 *) 0x40000000)   
     27#define __IPSBAR ((vuint8 *) 0x40000000)
    2828
    2929/***************************************************************************/
  • c/src/lib/libbsp/m68k/mcf52235/start/start.S

    r32b8506 rd4b4664b  
    2323
    2424BEGIN_CODE
    25    
     25
    2626    PUBLIC (_INTERRUPT_VECTOR)
    2727SYM(_INTERRUPT_VECTOR):
     
    314314.align 4
    315315    PUBLIC (_uhoh)
    316 SYM(_uhoh): 
     316SYM(_uhoh):
    317317    nop                     | Leave spot for breakpoint
    318     stop    #0x2700         | Stop with interrupts disabled 
     318    stop    #0x2700         | Stop with interrupts disabled
    319319    bra.w   SYM(_uhoh)      | Stuck forever
    320320
    321 /* 
     321/*
    322322 * Spurious Interrupt Handler
    323323 */
     
    328328    rte
    329329
    330 /* 
     330/*
    331331 * Write VBR Register
    332332 */
     
    335335SYM(_wr_vbr):
    336336    move.l  4(sp), d0
    337     movec   d0, vbr 
     337    movec   d0, vbr
    338338    nop
    339     rts 
    340 
    341 /* 
     339    rts
     340
     341/*
    342342 * Board startup
    343343 * Disable watchdog, interrupts
     
    360360    movec   d0, %rambar
    361361
    362     /* Locate Stack Pointer */ 
     362    /* Locate Stack Pointer */
    363363    move.l  #_StackInit, sp
    364364
     
    372372_continue_startup:
    373373
    374     /* Locate Stack Pointer */ 
     374    /* Locate Stack Pointer */
    375375    move.l  #_StackInit, sp
    376376
     
    386386
    387387_change_flashbar:
    388     /* 
    389     * The following sequence is used to set FLASHBAR. Since we may 
     388    /*
     389    * The following sequence is used to set FLASHBAR. Since we may
    390390    * be executing from Flash, we must put the routine into SRAM for
    391391    * execution and then jump back to Flash using the new address.
     
    403403    * (0x00000000) is used.
    404404    *
    405     * If running in SRAM, change_flashbar should not be executed 
     405    * If running in SRAM, change_flashbar should not be executed
    406406    */
    407407
  • c/src/lib/libbsp/m68k/mcf52235/startup/bspgetcpuclockspeed.c

    r32b8506 rd4b4664b  
    66 *  found in the file LICENSE in this distribution or at
    77 *  http://www.rtems.com/license/LICENSE.
    8  * 
     8 *
    99 *  $Id$
    1010 */
  • c/src/lib/libbsp/m68k/mcf52235/startup/cfinit.c

    r32b8506 rd4b4664b  
    22* Initialisation Code for ColdFire MCF52235 Processor                *
    33**********************************************************************
    4  Generated by ColdFire Initialisation Utility 2.10.8 
    5  Fri May 23 14:39:00 2008 
    6    
    7  MicroAPL Ltd makes no warranties in respect of the suitability 
    8  of this code for any particular purpose, and accepts 
    9  no liability for any loss arising out of its use. The person or 
    10  persons making use of this file must make the final evaluation 
    11  as to its suitability and correctness for a particular application. 
    12    
     4 Generated by ColdFire Initialisation Utility 2.10.8
     5 Fri May 23 14:39:00 2008
     6
     7 MicroAPL Ltd makes no warranties in respect of the suitability
     8 of this code for any particular purpose, and accepts
     9 no liability for any loss arising out of its use. The person or
     10 persons making use of this file must make the final evaluation
     11 as to its suitability and correctness for a particular application.
     12
    1313*/
    1414
     
    113113static void init_clock_config(void)
    114114{
    115   /* Clock source is 25.0000 MHz external crystal 
    116      Clock mode: Normal PLL mode 
    117      Processor/Bus clock frequency = 60.00 MHz 
    118      Loss of clock detection disabled 
    119      Reset on loss of lock disabled 
     115  /* Clock source is 25.0000 MHz external crystal
     116     Clock mode: Normal PLL mode
     117     Processor/Bus clock frequency = 60.00 MHz
     118     Loss of clock detection disabled
     119     Reset on loss of lock disabled
    120120   */
    121121
     
    138138static void init_ipsbar(void)
    139139{
    140   /* Base address of internal peripherals (IPSBAR) = 0x40000000 
    141 
    142      Note: Processor powers up with IPS base address = 0x40000000 
    143      Write to IPS base + 0x00000000 to set new value 
     140  /* Base address of internal peripherals (IPSBAR) = 0x40000000
     141
     142     Note: Processor powers up with IPS base address = 0x40000000
     143     Write to IPS base + 0x00000000 to set new value
    144144   */
    145145  *(vuint32 *) 0x40000000 = (vuint32) __IPSBAR + 1;     /* +1 for Enable */
     
    151151static void init_flash_controller(void)
    152152{
    153   /* Internal Flash module enabled, address = $00000000 
    154      Flash state machine clock = 197.37 kHz 
    155      All access types except CPU space/interrupt acknowledge cycle allowed 
    156      Flash is Write-Protected 
    157      All interrupts disabled 
     153  /* Internal Flash module enabled, address = $00000000
     154     Flash state machine clock = 197.37 kHz
     155     All access types except CPU space/interrupt acknowledge cycle allowed
     156     Flash is Write-Protected
     157     All interrupts disabled
    158158   */
    159159  MCF_CFM_CFMCLKD = MCF_CFM_CFMCLKD_PRDIV8 | MCF_CFM_CFMCLKD_DIV(0x12);
    160160  MCF_CFM_CFMMCR = 0;
    161161
    162   /* WARNING: Setting FLASHBAR[6]=1 in order to turn off address speculation 
    163      This is a workaround for a hardware problem whereby a speculative 
    164      access to the Flash occuring at the same time as an SRAM access 
    165      can return corrupt data. 
    166 
    167      This workaround can result in a 4% - 9% performance penalty. Other workarounds 
    168      are possible for certain applications. 
    169 
    170      For example, if you know that you will not be using the top 32 KB of the Flash 
    171      you can place the SRAM base address at 0x20038000 
    172 
    173      See Device Errata for further details 
     162  /* WARNING: Setting FLASHBAR[6]=1 in order to turn off address speculation
     163     This is a workaround for a hardware problem whereby a speculative
     164     access to the Flash occuring at the same time as an SRAM access
     165     can return corrupt data.
     166
     167     This workaround can result in a 4% - 9% performance penalty. Other workarounds
     168     are possible for certain applications.
     169
     170     For example, if you know that you will not be using the top 32 KB of the Flash
     171     you can place the SRAM base address at 0x20038000
     172
     173     See Device Errata for further details
    174174   */
    175175  asm("move.l   #0x00000161,%d0");
     
    212212static void init_bus_config(void)
    213213{
    214   /* Use round robin arbitration scheme 
    215      Assigned priorities (highest first): 
    216      Ethernet 
    217      DMA Controller 
    218      ColdFire Core 
    219      DMA bandwidth control disabled 
    220      Park on last active bus master 
     214  /* Use round robin arbitration scheme
     215     Assigned priorities (highest first):
     216     Ethernet
     217     DMA Controller
     218     ColdFire Core
     219     DMA bandwidth control disabled
     220     Park on last active bus master
    221221   */
    222222  MCF_SCM_MPARK = MCF_SCM_MPARK_M3PRTY(0x3) |
     
    229229static void init_sram(void)
    230230{
    231   /* Internal SRAM module enabled, address = $20000000 
    232      DMA access to SRAM block disabled 
    233      All access types (supervisor and user) allowed 
     231  /* Internal SRAM module enabled, address = $20000000
     232     DMA access to SRAM block disabled
     233     All access types (supervisor and user) allowed
    234234   */
    235235  asm("move.l   #0x20000001,%d0");
     
    242242static void init_power_management(void)
    243243{
    244   /* On executing STOP instruction, processor enters RUN mode 
    245      Mode is exited when an interrupt of level 1 or higher is received 
     244  /* On executing STOP instruction, processor enters RUN mode
     245     Mode is exited when an interrupt of level 1 or higher is received
    246246   */
    247247  MCF_PMM_LPICR = MCF_PMM_LPICR_ENBSTOP;
     
    280280static void init_gp_timer(void)
    281281{
    282   /*   
    283      GPT disabled (GPTASCR1[GPTEN] = 0) 
    284      Channel 0 configured as GPIO input 
    285      Channel 1 configured as GPIO input 
    286      Channel 2 configured as GPIO input 
    287      Channel 3 configured as GPIO input 
     282  /*
     283     GPT disabled (GPTASCR1[GPTEN] = 0)
     284     Channel 0 configured as GPIO input
     285     Channel 1 configured as GPIO input
     286     Channel 2 configured as GPIO input
     287     Channel 3 configured as GPIO input
    288288   */
    289289  MCF_GPT_GPTSCR1 = 0;
     
    326326static void init_interrupt_controller(void)
    327327{
    328   /* Configured interrupt sources in order of priority... 
    329      Level 7:  External interrupt /IRQ7, (initially masked) 
    330      Level 6:  External interrupt /IRQ6, (initially masked) 
    331      Level 5:  External interrupt /IRQ5, (initially masked) 
    332      Level 4:  External interrupt /IRQ4, (initially masked) 
    333      Level 3:  External interrupt /IRQ3, (initially masked) 
    334      Level 2:  External interrupt /IRQ2, (initially masked) 
    335      Level 1:  External interrupt /IRQ1, (initially masked) 
     328  /* Configured interrupt sources in order of priority...
     329     Level 7:  External interrupt /IRQ7, (initially masked)
     330     Level 6:  External interrupt /IRQ6, (initially masked)
     331     Level 5:  External interrupt /IRQ5, (initially masked)
     332     Level 4:  External interrupt /IRQ4, (initially masked)
     333     Level 3:  External interrupt /IRQ3, (initially masked)
     334     Level 2:  External interrupt /IRQ2, (initially masked)
     335     Level 1:  External interrupt /IRQ1, (initially masked)
    336336   */
    337337  MCF_INTC0_ICR1 = 0;
     
    427427static void init_pin_assignments(void)
    428428{
    429   /* Pin assignments for port NQ 
    430      Pins NQ7-NQ1 : EdgePort GPIO/IRQ 
     429  /* Pin assignments for port NQ
     430     Pins NQ7-NQ1 : EdgePort GPIO/IRQ
    431431   */
    432432  MCF_GPIO_DDRNQ = 0;
     
    438438    MCF_GPIO_PNQPAR_PNQPAR2(0x1) | MCF_GPIO_PNQPAR_PNQPAR1(0x1);
    439439
    440   /* Pin assignments for port GP 
    441      Pins PG7-PG0 : EdgePort GPIO/IRQ 
     440  /* Pin assignments for port GP
     441     Pins PG7-PG0 : EdgePort GPIO/IRQ
    442442   */
    443443  MCF_GPIO_DDRGP = 0;
     
    450450    MCF_GPIO_PGPPAR_PGPPAR1 | MCF_GPIO_PGPPAR_PGPPAR0;
    451451
    452   /* Pin assignments for port DD 
    453      Pin DD7 : DDATA[3] 
    454      Pin DD6 : DDATA[2] 
    455      Pin DD5 : DDATA[1] 
    456      Pin DD4 : DDATA[0] 
    457      Pin DD3 : PST[3] 
    458      Pin DD2 : PST[2] 
    459      Pin DD1 : PST[1] 
    460      Pin DD0 : PST[0] 
    461      CCON[PSTEN] = 1 to enable PST/DDATA function 
     452  /* Pin assignments for port DD
     453     Pin DD7 : DDATA[3]
     454     Pin DD6 : DDATA[2]
     455     Pin DD5 : DDATA[1]
     456     Pin DD4 : DDATA[0]
     457     Pin DD3 : PST[3]
     458     Pin DD2 : PST[2]
     459     Pin DD1 : PST[1]
     460     Pin DD0 : PST[0]
     461     CCON[PSTEN] = 1 to enable PST/DDATA function
    462462   */
    463463  MCF_GPIO_DDRDD = 0;
     
    471471  MCF_CIM_CCON = 0x0021;
    472472
    473   /* Pin assignments for port AN 
    474      Pins are all GPIO inputs 
     473  /* Pin assignments for port AN
     474     Pins are all GPIO inputs
    475475   */
    476476  MCF_GPIO_DDRAN = 0;
    477477  MCF_GPIO_PANPAR = 0;
    478478
    479   /* Pin assignments for port AS 
    480      Pins are all GPIO inputs 
     479  /* Pin assignments for port AS
     480     Pins are all GPIO inputs
    481481   */
    482482  MCF_GPIO_DDRAS = 0;
    483483  MCF_GPIO_PASPAR = 0;
    484484
    485   /* Pin assignments for port LD 
    486      Pins are all GPIO inputs 
     485  /* Pin assignments for port LD
     486     Pins are all GPIO inputs
    487487   */
    488488  MCF_GPIO_DDRLD = 0;
    489489  MCF_GPIO_PLDPAR = 0;
    490490
    491   /* Pin assignments for port QS 
    492      Pins are all GPIO inputs 
     491  /* Pin assignments for port QS
     492     Pins are all GPIO inputs
    493493   */
    494494  MCF_GPIO_DDRQS = 0;
    495495  MCF_GPIO_PQSPAR = 0;
    496496
    497   /* Pin assignments for port TA 
    498      Pins are all GPIO inputs 
     497  /* Pin assignments for port TA
     498     Pins are all GPIO inputs
    499499   */
    500500  MCF_GPIO_DDRTA = 0;
    501501  MCF_GPIO_PTAPAR = 0;
    502502
    503   /* Pin assignments for port TC 
    504      Pins are all GPIO inputs 
     503  /* Pin assignments for port TC
     504     Pins are all GPIO inputs
    505505   */
    506506  MCF_GPIO_DDRTC = 0;
    507507  MCF_GPIO_PTCPAR = 0;
    508508
    509   /* Pin assignments for port TD 
    510      Pins are all GPIO inputs 
     509  /* Pin assignments for port TD
     510     Pins are all GPIO inputs
    511511   */
    512512  MCF_GPIO_DDRTD = 0;
    513513  MCF_GPIO_PTDPAR = 0;
    514514
    515   /* Pin assignments for port UA 
    516      Pin UA3 : UART 0 clear-to-send, UCTS0 
    517      Pin UA2 : UART 0 request-to-send, URTS0 
    518      Pin UA1 : UART 0 receive data, URXD0 
    519      Pin UA0 : UART 0 transmit data, UTXD0 
     515  /* Pin assignments for port UA
     516     Pin UA3 : UART 0 clear-to-send, UCTS0
     517     Pin UA2 : UART 0 request-to-send, URTS0
     518     Pin UA1 : UART 0 receive data, URXD0
     519     Pin UA0 : UART 0 transmit data, UTXD0
    520520   */
    521521  MCF_GPIO_DDRUA = 0;
     
    524524    MCF_GPIO_PUAPAR_PUAPAR1(0x1) | MCF_GPIO_PUAPAR_PUAPAR0(0x1);
    525525
    526   /* Pin assignments for port UB 
    527      Pin UB3 : UART 1 clear-to-send, UCTS1 
    528      Pin UB2 : UART 1 request-to-send, URTS1 
    529      Pin UB1 : UART 1 receive data, URXD1 
    530      Pin UB0 : UART 1 transmit data, UTXD1 
     526  /* Pin assignments for port UB
     527     Pin UB3 : UART 1 clear-to-send, UCTS1
     528     Pin UB2 : UART 1 request-to-send, URTS1
     529     Pin UB1 : UART 1 receive data, URXD1
     530     Pin UB0 : UART 1 transmit data, UTXD1
    531531   */
    532532  MCF_GPIO_DDRUB = 0;
     
    535535    MCF_GPIO_PUBPAR_PUBPAR1(0x1) | MCF_GPIO_PUBPAR_PUBPAR0(0x1);
    536536
    537   /* Pin assignments for port UC 
    538      Pin UC3 : UART 2 clear-to-send, UCTS2 
    539      Pin UC2 : UART 2 request-to-send, URTS2 
    540      Pin UC1 : UART 2 receive data, URXD2 
    541      Pin UC0 : UART 2 transmit data, UTXD2 
     537  /* Pin assignments for port UC
     538     Pin UC3 : UART 2 clear-to-send, UCTS2
     539     Pin UC2 : UART 2 request-to-send, URTS2
     540     Pin UC1 : UART 2 receive data, URXD2
     541     Pin UC0 : UART 2 transmit data, UTXD2
    542542   */
    543543  MCF_GPIO_DDRUC = 0;
  • c/src/lib/libbsp/m68k/mcf52235/startup/init52235.c

    r32b8506 rd4b4664b  
    3131  register uint8_t *dbp, *sbp;
    3232
    33   /* 
     33  /*
    3434   * Initialize the hardware
    3535   */
    3636  init_main();
    3737
    38   /* 
    39    * Copy the vector table to RAM 
     38  /*
     39   * Copy the vector table to RAM
    4040   */
    4141
     
    5050  _wr_vbr((uint32_t) _VBR);
    5151
    52   /* 
    53    * Move initialized data from ROM to RAM. 
     52  /*
     53   * Move initialized data from ROM to RAM.
    5454   */
    5555  if (_data_src_start != _data_dest_start) {
     
    6161  }
    6262
    63   /* 
    64    * Zero uninitialized data 
     63  /*
     64   * Zero uninitialized data
    6565   */
    6666
  • c/src/lib/libbsp/m68k/mcf5235/console/console.c

    r32b8506 rd4b4664b  
    2828static void
    2929_BSP_null_char( char c )
    30 { 
     30{
    3131        int level;
    3232
     
    156156   value and sets it. At the moment this just sets the baud rate.
    157157
    158    Note: The highest baudrate is 115200 as this stays within 
     158   Note: The highest baudrate is 115200 as this stays within
    159159   an error of +/- 5% at 25MHz processor clock
    160160 ***************************************************************************/
     
    386386   Function : IntUartInterruptWrite
    387387
    388    Description : This writes a single character to the appropriate uart 
     388   Description : This writes a single character to the appropriate uart
    389389   channel. This is either called during an interrupt or in the user's task
    390    to initiate a transmit sequence. Calling this routine enables Tx 
     390   to initiate a transmit sequence. Calling this routine enables Tx
    391391   interrupts.
    392392 ***************************************************************************/
     
    495495        while ( ( index < count ) && ( index < RX_BUFFER_SIZE ) )
    496496        {
    497                 /* copy data byte */ 
     497                /* copy data byte */
    498498                buffer[index] = info->rx_buffer[info->rx_out];
    499499                index++;
     
    522522   Function : IntUartPollRead
    523523
    524    Description : This reads a character from the internal uart. It returns 
     524   Description : This reads a character from the internal uart. It returns
    525525   to the caller without blocking if not character is waiting.
    526526 ***************************************************************************/
     
    538538   Function : IntUartPollWrite
    539539
    540    Description : This writes out each character in the buffer to the 
    541    appropriate internal uart channel waiting till each one is sucessfully 
     540   Description : This writes out each character in the buffer to the
     541   appropriate internal uart channel waiting till each one is sucessfully
    542542   transmitted.
    543543 ***************************************************************************/
     
    576576        /* set io modes for the different channels and initialize device */
    577577    IntUartInfo[minor].iomode = TERMIOS_IRQ_DRIVEN;
    578         IntUartInitialize(); 
     578        IntUartInitialize();
    579579
    580580        /* Register the console port */
     
    609609   Function : console_open
    610610
    611    Description : This actually opens the device depending on the minor 
     611   Description : This actually opens the device depending on the minor
    612612   number set during initialisation. The device specific access routines are
    613613   passed to termios when the devices is opened depending on whether it is
  • c/src/lib/libbsp/m68k/mcf5235/include/bsp.h

    r32b8506 rd4b4664b  
    22 *  mcf5235 BSP header file
    33 */
    4  
     4
    55#ifndef _BSP_H
    66#define _BSP_H
  • c/src/lib/libbsp/m68k/mcf5235/network/network.c

    r32b8506 rd4b4664b  
    108108{
    109109    MCF5235_FEC_EIR = MCF5235_FEC_EIR_RXF;
    110     MCF5235_FEC_EIMR &= ~MCF5235_FEC_EIMR_RXF;   
     110    MCF5235_FEC_EIMR &= ~MCF5235_FEC_EIMR_RXF;
    111111    enet_driver[0].rxInterrupts++;
    112112    rtems_event_send(enet_driver[0].rxDaemonTid, RX_INTERRUPT_EVENT);
     
    117117{
    118118    MCF5235_FEC_EIR = MCF5235_FEC_EIR_TXF;
    119     MCF5235_FEC_EIMR &= ~MCF5235_FEC_EIMR_TXF;   
     119    MCF5235_FEC_EIMR &= ~MCF5235_FEC_EIMR_TXF;
    120120    enet_driver[0].txInterrupts++;
    121121    rtems_event_send(enet_driver[0].txDaemonTid, TX_INTERRUPT_EVENT);
     
    241241     *   No loopback
    242242     */
    243     MCF5235_FEC_RCR = MCF5235_FEC_RCR_MAX_FL(MAX_MTU_SIZE) | 
     243    MCF5235_FEC_RCR = MCF5235_FEC_RCR_MAX_FL(MAX_MTU_SIZE) |
    244244                      MCF5235_FEC_RCR_MII_MODE;
    245245
     
    322322  hwaddr[2] = (addr >>  8) & 0xff;
    323323  hwaddr[3] = (addr >>  0) & 0xff;
    324  
     324
    325325  addr = MCF5235_FEC_PAUR;
    326  
     326
    327327  hwaddr[4] = (addr >> 24) & 0xff;
    328328  hwaddr[5] = (addr >> 16) & 0xff;
    329329}
    330                    
     330
    331331
    332332/*
     
    486486    nAdded = 0;
    487487    firstTxBd = sc->txBdBase + sc->txBdHead;
    488    
     488
    489489    for (;;) {
    490         /* 
     490        /*
    491491         * Wait for buffer descriptor to become available
    492492         */
     
    509509
    510510                rtems_interrupt_disable(level);
    511                 MCF5235_FEC_EIMR |= MCF5235_FEC_EIMR_TXF;   
     511                MCF5235_FEC_EIMR |= MCF5235_FEC_EIMR_TXF;
    512512                rtems_interrupt_enable(level);
    513513                sc->txRawWait++;
     
    519519            }
    520520        }
    521    
     521
    522522        /*
    523523         * Don't set the READY flag on the first fragment
     
    525525         */
    526526        status = nAdded ? MCF5235_FEC_TxBD_R : 0;
    527    
     527
    528528        /*
    529529         * The IP fragmentation routine in ip_output
     
    596596         * Wait for packet
    597597         */
    598         rtems_bsdnet_event_receive(START_TRANSMIT_EVENT, 
    599                                     RTEMS_EVENT_ANY | RTEMS_WAIT, 
    600                                     RTEMS_NO_TIMEOUT, 
     598        rtems_bsdnet_event_receive(START_TRANSMIT_EVENT,
     599                                    RTEMS_EVENT_ANY | RTEMS_WAIT,
     600                                    RTEMS_NO_TIMEOUT,
    601601                                    &events);
    602602
  • c/src/lib/libbsp/m68k/mcf5235/start/start.S

    r32b8506 rd4b4664b  
    2525BEGIN_CODE
    2626#define INITIAL_STACK __SRAMBASE+SRAM_SIZE-4
    27        
     27
    2828        PUBLIC (INTERRUPT_VECTOR)
    2929SYM(INTERRUPT_VECTOR):
    30     .long   INITIAL_STACK   |   0: Initial 'SSP'   
     30    .long   INITIAL_STACK   |   0: Initial 'SSP'
    3131    .long   start           |   1: Initial PC
    3232    .long   SYM(_uhoh)      |   2: Bus error
     
    291291.align 4
    292292    PUBLIC (_uhoh)
    293 SYM(_uhoh): 
     293SYM(_uhoh):
    294294    nop                         | Leave spot for breakpoint
    295     stop    #0x2700             | Stop with interrupts disabled 
     295    stop    #0x2700             | Stop with interrupts disabled
    296296    bra.w   SYM(_uhoh)          | Stuck forever
    297297
     
    319319    movec   d0,%rambar              | ...so we have a stack
    320320
    321     move.l  #0x20000201, d0 
     321    move.l  #0x20000201, d0
    322322    move.l   d0,(0x40000008)        | set up 2nd RAMBAR to make 2nd port avail to FEC
    323323
    324324    move.l  #__IPSBAR+1,d0          | Enable the MCF5235 internal peripherals
    325325    move.l  d0,DEFAULT_IPSBAR
    326        
     326
    327327    /*
    328328     * Remainder of the startup code is handled by C code
     
    333333   Function : CopyDataClearBSSAndStart
    334334
    335    Description : Copy DATA segment, Copy SRAM segment, clear BSS segment, 
     335   Description : Copy DATA segment, Copy SRAM segment, clear BSS segment,
    336336   start C program. Assume that DATA and BSS sizes are multiples of 4.
    337337 ***************************************************************************/
     
    341341SYM(CopyDataClearBSSAndStart):
    342342    lea SYM(_data_dest_start),a0        | Get start of DATA in RAM
    343     lea SYM(_data_src_start),a2     | Get start of DATA in ROM 
     343    lea SYM(_data_src_start),a2     | Get start of DATA in ROM
    344344    cmpl    a0,a2                   | Are they the same?
    345345    beq.s   NODATACOPY              | Yes, no copy necessary
     
    352352    bcs.s   DATACOPYLOOP                | No, skip
    353353NODATACOPY:
    354        
     354
    355355/* Now, clear BSS */
    356356        lea _clear_start,a0     | Get start of BSS
     
    376376        nop
    377377        trap    #14
    378         bra     MULTI_TASK_EXIT 
    379        
     378        bra     MULTI_TASK_EXIT
     379
    380380END_CODE
    381381
  • c/src/lib/libbsp/m68k/mcf5235/startup/bspgetcpuclockspeed.c

    r32b8506 rd4b4664b  
    77 *
    88 *  http://www.rtems.com/license/LICENSE.
    9  * 
     9 *
    1010 *  $Id$
    1111 */
    1212
    1313#include <bsp.h>
    14  
     14
    1515extern char _CPUClockSpeed[];
    1616
  • c/src/lib/libbsp/m68k/mcf5235/startup/bspstart.c

    r32b8506 rd4b4664b  
    77 *
    88 *  http://www.rtems.com/license/LICENSE.
    9  * 
     9 *
    1010 *  $Id$
    1111 */
    1212
    1313#include <bsp.h>
    14  
     14
    1515/*
    1616 * Read/write copy of common cache
  • c/src/lib/libbsp/m68k/mcf5235/startup/init5235.c

    r32b8506 rd4b4664b  
    33 *  has been provided by the start.S code. No normal C or RTEMS
    44 *  functions can be called from here.
    5  * 
     5 *
    66 * This routine is pretty simple for the uC5235 because all the hard
    77 * work has been done by the bootstrap dBUG code.
     
    2222 * do need to initialize the SDRAM.
    2323 */
    24  
    25  
     24
     25
    2626extern uint32_t MCF5235_BSP_START_FROM_FLASH;
    2727
     
    3232    volatile int temp = 0;
    3333    int *address_of_MCF5235_BSP_START_FROM_FLASH;
    34    
     34
    3535    /*Setup the GPIO Registers */
    3636    MCF5235_GPIO_UART=0x3FFF;
    3737    MCF5235_GPIO_PAR_AD=0xE1;
    38    
     38
    3939    /*Setup the Chip Selects so CS0 is flash */
    4040    MCF5235_CS_CSAR0 =(0xFFE00000 & 0xffff0000)>>16;
    4141    MCF5235_CS_CSMR0 = 0x001f0001;
    4242    MCF5235_CS_CSCR0 = 0x1980;
    43    
     43
    4444    address_of_MCF5235_BSP_START_FROM_FLASH = (int *) & MCF5235_BSP_START_FROM_FLASH;
    4545    if ( (int)address_of_MCF5235_BSP_START_FROM_FLASH == 1) {
     
    5757        }
    5858        /* set ip ( bit 3 ) in dacr */
    59         MCF5235_SDRAMC_DACR0 |= (0x00000008) ; 
     59        MCF5235_SDRAMC_DACR0 |= (0x00000008) ;
    6060        /* init precharge */
    6161        *((unsigned long *)MM_SDRAM_BASE) = 0xDEADBEEF;
    6262        /* set RE in dacr */
    63         MCF5235_SDRAMC_DACR0 |= (0x00008000); 
     63        MCF5235_SDRAMC_DACR0 |= (0x00008000);
    6464        /* wait */
    6565        for(x=0; x<20000; x++)
     
    7171        *((short *)MM_SDRAM_BASE) = 0;
    7272        for(x=0; x<60000; x++)
    73         { 
     73        {
    7474                temp +=1;
    7575        }
    7676        *((unsigned long*)MM_SDRAM_BASE)=0x12345678;
    7777    } /* we have finished setting up the sdram */
    78        
     78
    7979    /* Copy the interrupt vector table to address 0x0 in SDRAM */
    8080    {
  • c/src/lib/libbsp/m68k/mcf5329/clock/clock.c

    r32b8506 rd4b4664b  
    8282
    8383  MCF_INTC1_ICR46 = MCF_INTC_ICR_IL(PIT3_IRQ_LEVEL);
    84  
     84
    8585  rtems_interrupt_disable(level);
    8686  MCF_INTC1_IMRH &= ~MCF_INTC_IMRH_INT_MASK46;
  • c/src/lib/libbsp/m68k/mcf5329/console/console.c

    r32b8506 rd4b4664b  
    153153   value and sets it. At the moment this just sets the baud rate.
    154154
    155    Note: The highest baudrate is 115200 as this stays within 
     155   Note: The highest baudrate is 115200 as this stays within
    156156   an error of +/- 5% at 25MHz processor clock
    157157 ***************************************************************************/
     
    349349   Function : IntUartInterruptWrite
    350350
    351    Description : This writes a single character to the appropriate uart 
     351   Description : This writes a single character to the appropriate uart
    352352   channel. This is either called during an interrupt or in the user's task
    353    to initiate a transmit sequence. Calling this routine enables Tx 
     353   to initiate a transmit sequence. Calling this routine enables Tx
    354354   interrupts.
    355355 ***************************************************************************/
     
    469469   Function : IntUartPollRead
    470470
    471    Description : This reads a character from the internal uart. It returns 
     471   Description : This reads a character from the internal uart. It returns
    472472   to the caller without blocking if not character is waiting.
    473473 ***************************************************************************/
     
    483483   Function : IntUartPollWrite
    484484
    485    Description : This writes out each character in the buffer to the 
    486    appropriate internal uart channel waiting till each one is sucessfully 
     485   Description : This writes out each character in the buffer to the
     486   appropriate internal uart channel waiting till each one is sucessfully
    487487   transmitted.
    488488 ***************************************************************************/
     
    545545   Function : console_open
    546546
    547    Description : This actually opens the device depending on the minor 
     547   Description : This actually opens the device depending on the minor
    548548   number set during initialisation. The device specific access routines are
    549549   passed to termios when the devices is opened depending on whether it is
  • c/src/lib/libbsp/m68k/mcf5329/include/bsp.h

    r32b8506 rd4b4664b  
    22 *  mcf52235 BSP header file
    33 */
    4  
     4
    55#ifndef _BSP_H
    66#define _BSP_H
     
    2424typedef volatile unsigned char vuint8;
    2525typedef volatile unsigned short vuint16;
    26 typedef volatile unsigned long vuint32;   
    27    
     26typedef volatile unsigned long vuint32;
     27
    2828/***************************************************************************/
    2929/**  Network driver configuration                                         **/
  • c/src/lib/libbsp/m68k/mcf5329/network/network.c

    r32b8506 rd4b4664b  
    474474
    475475  for (;;) {
    476     /* 
     476    /*
    477477     * Wait for buffer descriptor to become available
    478478     */
     
    540540      txBd->buffer = p;
    541541      txBd->length = m->m_len;
    542      
     542
    543543      rtems_cache_flush_multiple_data_lines(txBd->buffer, txBd->length);
    544      
     544
    545545      sc->txMbuf[sc->txBdHead] = m;
    546546      nAdded++;
  • c/src/lib/libbsp/m68k/mcf5329/start/start.S

    r32b8506 rd4b4664b  
    2323
    2424BEGIN_CODE
    25    
     25
    2626    PUBLIC (_INTERRUPT_VECTOR)
    2727SYM(_INTERRUPT_VECTOR):
     
    299299.align 4
    300300    PUBLIC (_uhoh)
    301 SYM(_uhoh): 
     301SYM(_uhoh):
    302302    nop                     | Leave spot for breakpoint
    303     stop    #0x2700         | Stop with interrupts disabled 
     303    stop    #0x2700         | Stop with interrupts disabled
    304304    bra.w   SYM(_uhoh)      | Stuck forever
    305305
    306 /* 
     306/*
    307307 * Spurious Interrupt Handler
    308308 */
     
    313313    rte
    314314
    315 /* 
     315/*
    316316 * Write VBR Register
    317317 */
     
    320320SYM(_wr_vbr):
    321321    move.l  4(sp), d0
    322     movec   d0, vbr 
     322    movec   d0, vbr
    323323    nop
    324     rts 
    325 
    326 /* 
     324    rts
     325
     326/*
    327327 * Board startup
    328328 * Disable watchdog, interrupts
     
    345345    movec   d0,%rambar
    346346
    347     /* Save off intial D0 and D1 to RAM */ 
     347    /* Save off intial D0 and D1 to RAM */
    348348    move.l  d6, SYM(_d0_reset)
    349349    move.l  d7, SYM(_d1_reset)
    350350
    351     /* Locate Stack Pointer */ 
     351    /* Locate Stack Pointer */
    352352    move.l  #_StackInit,sp
    353353
  • c/src/lib/libbsp/m68k/mcf5329/startup/bspstart.c

    r32b8506 rd4b4664b  
    1717 *  found in the file LICENSE in this distribution or at
    1818 *  http://www.rtems.com/license/LICENSE.
    19  * 
     19 *
    2020 *  $Id$
    2121 */
  • c/src/lib/libbsp/m68k/mcf5329/startup/cfinit.c

    r32b8506 rd4b4664b  
    33* Initialisation Code for ColdFire MCF5329 Processor                 *
    44**********************************************************************
    5  Generated by ColdFire Initialisation Utility 2.10.8 
    6  Wed Jul 02 14:26:25 2008 
    7    
    8  MicroAPL Ltd makes no warranties in respect of the suitability 
    9  of this code for any particular purpose, and accepts 
    10  no liability for any loss arising out of its use. The person or 
    11  persons making use of this file must make the final evaluation 
    12  as to its suitability and correctness for a particular application. 
     5 Generated by ColdFire Initialisation Utility 2.10.8
     6 Wed Jul 02 14:26:25 2008
     7
     8 MicroAPL Ltd makes no warranties in respect of the suitability
     9 of this code for any particular purpose, and accepts
     10 no liability for any loss arising out of its use. The person or
     11 persons making use of this file must make the final evaluation
     12 as to its suitability and correctness for a particular application.
    1313
    1414 $Id$
    15    
     15
    1616*/
    1717
    18 /* External reference frequency is 16.0000 MHz 
    19  Internal bus clock frequency = 80.00 MHz 
    20  Processor core frequency = 240.00 MHz 
     18/* External reference frequency is 16.0000 MHz
     19 Internal bus clock frequency = 80.00 MHz
     20 Processor core frequency = 240.00 MHz
    2121*/
    2222
     
    5050static void init_edma(void);
    5151static void init_pin_assignments(void);
    52 extern void init_sdram_controller(void) 
     52extern void init_sdram_controller(void)
    5353  __attribute__ ((section(".ram_code")));
    5454static void init_interrupt_controller(void);
     
    128128void init_clock_config(void)
    129129{
    130   /* Clock module uses normal PLL mode with 16.0000 MHz external reference 
    131      Bus clock frequency = 80.00 MHz 
    132      Processor clock frequency = 3 x bus clock = 240.00 MHz 
    133      Dithering disabled 
    134    */
    135 
    136   /* Check to see if the SDRAM has already been initialized 
    137      by a run control tool. If it has, put SDRAM into self-refresh mode before 
    138      initializing the PLL 
     130  /* Clock module uses normal PLL mode with 16.0000 MHz external reference
     131     Bus clock frequency = 80.00 MHz
     132     Processor clock frequency = 3 x bus clock = 240.00 MHz
     133     Dithering disabled
     134   */
     135
     136  /* Check to see if the SDRAM has already been initialized
     137     by a run control tool. If it has, put SDRAM into self-refresh mode before
     138     initializing the PLL
    139139   */
    140140  if (MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF)
    141141    MCF_SDRAMC_SDCR &= ~MCF_SDRAMC_SDCR_CKE;
    142142
    143   /* Temporarily switch to LIMP mode 
    144      NOTE: Ensure that this code is not executing from SDRAM, since the 
    145      SDRAM Controller is disabled in LIMP mode 
     143  /* Temporarily switch to LIMP mode
     144     NOTE: Ensure that this code is not executing from SDRAM, since the
     145     SDRAM Controller is disabled in LIMP mode
    146146   */
    147147  MCF_CCM_CDR = (MCF_CCM_CDR & 0xf0ff) | MCF_CCM_CDR_LPDIV(0x2);
     
    158158  while ((MCF_CCM_MISCCR & MCF_CCM_MISCCR_PLL_LOCK) == 0) ;
    159159
    160   /* From the Device Errata: 
    161 
    162      "After exiting LIMP mode, the value of 0x40000000 should be written 
    163      to address 0xFC0B8080 before attempting to initialize the SDRAMC 
    164      or exit the SDRAM from self-refresh mode." 
     160  /* From the Device Errata:
     161
     162     "After exiting LIMP mode, the value of 0x40000000 should be written
     163     to address 0xFC0B8080 before attempting to initialize the SDRAMC
     164     or exit the SDRAM from self-refresh mode."
    165165   */
    166166  *(vuint32 *) 0xfc0b8080 = 0x40000000;
     
    176176static void init_cache(void)
    177177{
    178   /* ACR0: Cache accesses to 32 MB memory region at address $40000000 
    179      CACR: Don't cache accesses to the rest of memory 
     178  /* ACR0: Cache accesses to 32 MB memory region at address $40000000
     179     CACR: Don't cache accesses to the rest of memory
    180180   */
    181181  /*
     
    185185  asm("move.l   #0xa0000600,%d0");
    186186  asm("movec    %d0,%CACR");
    187 #endif 
     187#endif
    188188  asm("move.l   #0x4001c020,%d0");
    189189  asm("movec    %d0,%ACR0");
     
    197197static void init_crossbar(void)
    198198{
    199   /* XBS settings for FlexBus/SDRAM Controller slave: 
    200      Fixed priority (Core, LCD, eDMA, FEC, USB Host, USB OTG), park on ColdFire Core 
     199  /* XBS settings for FlexBus/SDRAM Controller slave:
     200     Fixed priority (Core, LCD, eDMA, FEC, USB Host, USB OTG), park on ColdFire Core
    201201   */
    202202  MCF_XBS_PRS1 = MCF_XBS_PRS_M6(0x5) |
     
    205205  MCF_XBS_CRS1 = 0;
    206206
    207   /* XBS settings for SRAM Backdoor slave: 
    208      Fixed priority (Core, eDMA, FEC, LCD, USB Host, USB OTG), park on ColdFire Core 
     207  /* XBS settings for SRAM Backdoor slave:
     208     Fixed priority (Core, eDMA, FEC, LCD, USB Host, USB OTG), park on ColdFire Core
    209209   */
    210210  MCF_XBS_PRS4 = MCF_XBS_PRS_M6(0x5) |
     
    213213  MCF_XBS_CRS4 = 0;
    214214
    215   /* XBS settings for Cryptography Modules slave: 
    216      Fixed priority (Core, eDMA, FEC, LCD, USB Host, USB OTG), park on ColdFire Core 
     215  /* XBS settings for Cryptography Modules slave:
     216     Fixed priority (Core, eDMA, FEC, LCD, USB Host, USB OTG), park on ColdFire Core
    217217   */
    218218  MCF_XBS_PRS6 = MCF_XBS_PRS_M6(0x5) |
     
    221221  MCF_XBS_CRS6 = 0;
    222222
    223   /* XBS settings for On-chip Peripherals slave: 
    224      Fixed priority (Core, eDMA, FEC, LCD, USB Host, USB OTG), park on ColdFire Core 
     223  /* XBS settings for On-chip Peripherals slave:
     224     Fixed priority (Core, eDMA, FEC, LCD, USB Host, USB OTG), park on ColdFire Core
    225225   */
    226226  MCF_XBS_PRS7 = MCF_XBS_PRS_M6(0x5) |
     
    250250  MCF_FBCS5_CSMR = 0;
    251251
    252   /* Chip Select 0: 2 MB of Flash at base address $00000000 
    253      Port size = 16 bits 
    254      Assert chip select on first rising clock edge after address is asserted 
    255      Generate internal transfer acknowledge after 7 wait states 
    256      Address is held for 1 clock at end of read and write cycles 
     252  /* Chip Select 0: 2 MB of Flash at base address $00000000
     253     Port size = 16 bits
     254     Assert chip select on first rising clock edge after address is asserted
     255     Generate internal transfer acknowledge after 7 wait states
     256     Address is held for 1 clock at end of read and write cycles
    257257   */
    258258  MCF_FBCS0_CSAR = 0;
     
    294294void init_sdram_controller(void)
    295295{
    296   /* Check to see if the SDRAM has already been initialized 
    297      by a run control tool and skip if so 
     296  /* Check to see if the SDRAM has already been initialized
     297     by a run control tool and skip if so
    298298   */
    299299  if (MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF)
    300300    return;
    301301
    302   /* Ensure that there is a delay from processor reset of the time recommended in 
    303      the SDRAM data sheet (typically 100-200 microseconds) until the following 
    304      code so that the SDRAM is ready for commands... 
    305    */
    306 
    307   /* SDRAM controller configured for Double-data rate (DDR) SDRAM 
    308      Bus width = 16 bits 
    309      SDRAM specification: 
    310      SDRAM clock frequency = 80.00 MHz 
    311      CASL = 2.5 
    312      ACTV-to-read/write delay, tRCD = 20.0 nanoseconds 
    313      Write recovery time, tWR = 15.0 nanoseconds 
    314      Precharge comand to ACTV command, tRP = 20.0 nanoseconds 
    315      Auto refresh command period, tRFC = 75.0 nanoseconds 
    316      Average periodic refresh interval, tREFI = 7.8 microseconds 
    317    */
    318 
    319   /* Memory block 0 enabled - 32 MBytes at address $40000000 
    320      Block consists of 1 device x 256 MBits (13 rows x 9 columns x 4 banks) 
     302  /* Ensure that there is a delay from processor reset of the time recommended in
     303     the SDRAM data sheet (typically 100-200 microseconds) until the following
     304     code so that the SDRAM is ready for commands...
     305   */
     306
     307  /* SDRAM controller configured for Double-data rate (DDR) SDRAM
     308     Bus width = 16 bits
     309     SDRAM specification:
     310     SDRAM clock frequency = 80.00 MHz
     311     CASL = 2.5
     312     ACTV-to-read/write delay, tRCD = 20.0 nanoseconds
     313     Write recovery time, tWR = 15.0 nanoseconds
     314     Precharge comand to ACTV command, tRP = 20.0 nanoseconds
     315     Auto refresh command period, tRFC = 75.0 nanoseconds
     316     Average periodic refresh interval, tREFI = 7.8 microseconds
     317   */
     318
     319  /* Memory block 0 enabled - 32 MBytes at address $40000000
     320     Block consists of 1 device x 256 MBits (13 rows x 9 columns x 4 banks)
    321321   */
    322322  MCF_SDRAMC_SDCS0 = MCF_SDRAMC_SDCS_BASE(0x400) | MCF_SDRAMC_SDCS_CSSZ(0x18);
     
    325325  MCF_SDRAMC_SDCS1 = 0;
    326326
    327   /* Initialise SDCFG1 register with delay and timing values 
    328      SRD2RWP = 4, SWT2RWP = 3, RD_LAT = 7, ACT2RW = 2 
    329      PRE2ACT = 2, REF2ACT = 6, WT_LAT = 3 
     327  /* Initialise SDCFG1 register with delay and timing values
     328     SRD2RWP = 4, SWT2RWP = 3, RD_LAT = 7, ACT2RW = 2
     329     PRE2ACT = 2, REF2ACT = 6, WT_LAT = 3
    330330   */
    331331  MCF_SDRAMC_SDCFG1 = MCF_SDRAMC_SDCFG1_SRD2RW(0x4) |
     
    336336    MCF_SDRAMC_SDCFG1_REF2ACT(0x6) | MCF_SDRAMC_SDCFG1_WTLAT(0x3);
    337337
    338   /* Initialise SDCFG2 register with delay and timing values 
    339      BRD2RP = 5, BWT2RWP = 6, BRD2W = 6, BL = 7 
     338  /* Initialise SDCFG2 register with delay and timing values
     339     BRD2RP = 5, BWT2RWP = 6, BRD2W = 6, BL = 7
    340340   */
    341341  MCF_SDRAMC_SDCFG2 = MCF_SDRAMC_SDCFG2_BRD2PRE(0x5) |
     
    362362  MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IPALL;
    363363
    364   /* Refresh sequence... 
    365      (check the number of refreshes required by the SDRAM manufacturer) 
     364  /* Refresh sequence...
     365     (check the number of refreshes required by the SDRAM manufacturer)
    366366   */
    367367  MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IREF;
     
    437437static void init_watchdog_timers(void)
    438438{
    439   /* Watchdog Timer disabled (WCR[EN]=0) 
    440      NOTE: WCR and WMR cannot be written again until after the 
    441      processor is reset. 
     439  /* Watchdog Timer disabled (WCR[EN]=0)
     440     NOTE: WCR and WMR cannot be written again until after the
     441     processor is reset.
    442442   */
    443443  MCF_WTM_WCR = MCF_WTM_WCR_WAIT | MCF_WTM_WCR_DOZE | MCF_WTM_WCR_HALTED;
     
    564564static void init_pin_assignments(void)
    565565{
    566   /* Pin assignments for port BUSCTL 
    567      Pin BUSCTL3 : External bus output enable, /OE 
    568      Pin BUSCTL2 : External bus transfer acknowledge, /TA 
    569      Pin BUSCTL1 : External bus read/write, R/W 
    570      Pin BUSCTL0 : External bus transfer start, /TS 
     566  /* Pin assignments for port BUSCTL
     567     Pin BUSCTL3 : External bus output enable, /OE
     568     Pin BUSCTL2 : External bus transfer acknowledge, /TA
     569     Pin BUSCTL1 : External bus read/write, R/W
     570     Pin BUSCTL0 : External bus transfer start, /TS
    571571   */
    572572  MCF_GPIO_PDDR_BUSCTL = 0;
     
    575575    MCF_GPIO_PAR_BUSCTL_PAR_RWB | MCF_GPIO_PAR_BUSCTL_PAR_TS(0x3);
    576576
    577   /* Pin assignments for port BE 
    578      Pin BE3 : External bus byte enable BW/BWE3 
    579      Pin BE2 : External bus byte enable BW/BWE2 
    580      Pin BE1 : External bus byte enable BW/BWE1 
    581      Pin BE0 : External bus byte enable BW/BWE0 
     577  /* Pin assignments for port BE
     578     Pin BE3 : External bus byte enable BW/BWE3
     579     Pin BE2 : External bus byte enable BW/BWE2
     580     Pin BE1 : External bus byte enable BW/BWE1
     581     Pin BE0 : External bus byte enable BW/BWE0
    582582   */
    583583  MCF_GPIO_PDDR_BE = 0;
     
    586586    MCF_GPIO_PAR_BE_PAR_BE1 | MCF_GPIO_PAR_BE_PAR_BE0;
    587587
    588   /* Pin assignments for port CS 
    589      Pin CS5 : Flex bus chip select /FB_CS5 
    590      Pin CS4 : Flex bus chip select /FB_CS4 
    591      Pin CS3 : Flex bus chip select /FB_CS3 
    592      Pin CS2 : Flex bus chip select /FB_CS2 
    593      Pin CS1 : Flex bus chip select /FB_CS1 
     588  /* Pin assignments for port CS
     589     Pin CS5 : Flex bus chip select /FB_CS5
     590     Pin CS4 : Flex bus chip select /FB_CS4
     591     Pin CS3 : Flex bus chip select /FB_CS3
     592     Pin CS2 : Flex bus chip select /FB_CS2
     593     Pin CS1 : Flex bus chip select /FB_CS1
    594594   */
    595595  MCF_GPIO_PDDR_CS = 0;
     
    599599    MCF_GPIO_PAR_CS_PAR_CS2 | MCF_GPIO_PAR_CS_PAR_CS1;
    600600
    601   /* Pin assignments for port FECI2C 
    602      Pin FECI2C3 : FEC management data clock, FEC_MDC 
    603      Pin FECI2C2 : FEC management data, FEC_MDIO 
    604      Pin FECI2C1 : GPIO input 
    605      Pin FECI2C0 : GPIO input 
     601  /* Pin assignments for port FECI2C
     602     Pin FECI2C3 : FEC management data clock, FEC_MDC
     603     Pin FECI2C2 : FEC management data, FEC_MDIO
     604     Pin FECI2C1 : GPIO input
     605     Pin FECI2C0 : GPIO input
    606606   */
    607607  MCF_GPIO_PDDR_FECI2C = 0;
     
    609609    MCF_GPIO_PAR_FECI2C_PAR_MDIO(0x3);
    610610
    611   /* Pin assignments for ports FECH and FECL 
    612      Pin FECH7 : FEC transmit clock, FEC_TXCLK 
    613      Pin FECH6 : FEC transmit enable, FEC_TXEN 
    614      Pin FECH5 : FEC transmit data 0, FEC_TXD0 
    615      Pin FECH4 : FEC collision, FEC_COL 
    616      Pin FECH3 : FEC receive clock, FEC_RXCLK 
    617      Pin FECH2 : FEC receive data valid, FEC_RXDV 
    618      Pin FECH1 : FEC receive data 0, FEC_RXD0 
    619      Pin FECH0 : FEC carrier receive sense, FEC_CRS 
    620      Pin FECL7 : FEC transmit data 3, FEC_TXD3 
    621      Pin FECL6 : FEC transmit data 2, FEC_TXD2 
    622      Pin FECL5 : FEC transmit data 1, FEC_TXD1 
    623      Pin FECL4 : FEC transmit error, FEC_TXER 
    624      Pin FECL3 : FEC receive data 3, FEX_RXD3 
    625      Pin FECL2 : FEC receive data 2, FEX_RXD2 
    626      Pin FECL1 : FEC receive data 1, FEX_RXD1 
    627      Pin FECL0 : FEC receive error, FEC_RXER 
     611  /* Pin assignments for ports FECH and FECL
     612     Pin FECH7 : FEC transmit clock, FEC_TXCLK
     613     Pin FECH6 : FEC transmit enable, FEC_TXEN
     614     Pin FECH5 : FEC transmit data 0, FEC_TXD0
     615     Pin FECH4 : FEC collision, FEC_COL
     616     Pin FECH3 : FEC receive clock, FEC_RXCLK
     617     Pin FECH2 : FEC receive data valid, FEC_RXDV
     618     Pin FECH1 : FEC receive data 0, FEC_RXD0
     619     Pin FECH0 : FEC carrier receive sense, FEC_CRS
     620     Pin FECL7 : FEC transmit data 3, FEC_TXD3
     621     Pin FECL6 : FEC transmit data 2, FEC_TXD2
     622     Pin FECL5 : FEC transmit data 1, FEC_TXD1
     623     Pin FECL4 : FEC transmit error, FEC_TXER
     624     Pin FECL3 : FEC receive data 3, FEX_RXD3
     625     Pin FECL2 : FEC receive data 2, FEX_RXD2
     626     Pin FECL1 : FEC receive data 1, FEX_RXD1
     627     Pin FECL0 : FEC receive error, FEC_RXER
    628628   */
    629629  MCF_GPIO_PDDR_FECH = 0;
     
    632632    MCF_GPIO_PAR_FEC_PAR_FEC_MII(0x3);
    633633
    634   /* Pin assignments for port IRQ 
    635      Pins are all used for EdgePort GPIO/IRQ 
     634  /* Pin assignments for port IRQ
     635     Pins are all used for EdgePort GPIO/IRQ
    636636   */
    637637  MCF_GPIO_PAR_IRQ = 0;
    638638
    639   /* Pin assignments for port LCDDATAH 
    640      Pins are all GPIO inputs 
     639  /* Pin assignments for port LCDDATAH
     640     Pins are all GPIO inputs
    641641   */
    642642  MCF_GPIO_PDDR_LCDDATAH = 0;
    643643  MCF_GPIO_PAR_LCDDATA = 0;
    644644
    645   /* Pin assignments for port LCDDATAM 
    646      Port LCDDATAM pins are all GPIO inputs 
     645  /* Pin assignments for port LCDDATAM
     646     Port LCDDATAM pins are all GPIO inputs
    647647   */
    648648  MCF_GPIO_PDDR_LCDDATAM = 0;
    649649
    650   /* Pin assignments for port LCDDATAL 
    651      Port LCDDATAL pins are all GPIO inputs 
     650  /* Pin assignments for port LCDDATAL
     651     Port LCDDATAL pins are all GPIO inputs
    652652   */
    653653  MCF_GPIO_PDDR_LCDDATAL = 0;
    654654
    655   /* Pin assignments for port LCDCTLH 
    656      Pins are all GPIO inputs 
     655  /* Pin assignments for port LCDCTLH
     656     Pins are all GPIO inputs
    657657   */
    658658  MCF_GPIO_PDDR_LCDCTLH = 0;
    659659  MCF_GPIO_PAR_LCDCTL = 0;
    660660
    661   /* Pin assignments for port LCDCTLL 
    662      Pins are all GPIO inputs 
     661  /* Pin assignments for port LCDCTLL
     662     Pins are all GPIO inputs
    663663   */
    664664  MCF_GPIO_PDDR_LCDCTLL = 0;
    665665
    666   /* Pin assignments for port PWM 
    667      Pins are all GPIO inputs 
     666  /* Pin assignments for port PWM
     667     Pins are all GPIO inputs
    668668   */
    669669  MCF_GPIO_PDDR_PWM = 0;
    670670  MCF_GPIO_PAR_PWM = 0;
    671671
    672   /* Pin assignments for port QSPI 
    673      Pins are all GPIO inputs 
     672  /* Pin assignments for port QSPI
     673     Pins are all GPIO inputs
    674674   */
    675675  MCF_GPIO_PDDR_QSPI = 0;
    676676  MCF_GPIO_PAR_QSPI = 0;
    677677
    678   /* Pin assignments for port SSI 
    679      Pins are all GPIO inputs 
     678  /* Pin assignments for port SSI
     679     Pins are all GPIO inputs
    680680   */
    681681  MCF_GPIO_PDDR_SSI = 0;
    682682  MCF_GPIO_PAR_SSI = 0;
    683683
    684   /* Pin assignments for port TIMER 
    685      Pins are all GPIO outputs 
     684  /* Pin assignments for port TIMER
     685     Pins are all GPIO outputs
    686686   */
    687687  MCF_GPIO_PDDR_TIMER = MCF_GPIO_PDDR_TIMER_PDDR_TIMER3 |
     
    690690  MCF_GPIO_PAR_TIMER = 0;
    691691
    692   /* Pin assignments for port UART 
    693      Pin UART7 : UART 1 clear-to-send, /U1CTS 
    694      Pin UART6 : UART 1 request-to-send, /U1RTS 
    695      Pin UART5 : UART 1 transmit data, U1TXD 
    696      Pin UART4 : UART 1 receive data, U1RXD 
    697      Pin UART3 : UART 0 clear-to-send, /U0CTS 
    698      Pin UART2 : UART 0 request-to-send, /U0RTS 
    699      Pin UART1 : UART 0 transmit data, U0TXD 
    700      Pin UART0 : UART 0 receive data, U0RXD 
     692  /* Pin assignments for port UART
     693     Pin UART7 : UART 1 clear-to-send, /U1CTS
     694     Pin UART6 : UART 1 request-to-send, /U1RTS
     695     Pin UART5 : UART 1 transmit data, U1TXD
     696     Pin UART4 : UART 1 receive data, U1RXD
     697     Pin UART3 : UART 0 clear-to-send, /U0CTS
     698     Pin UART2 : UART 0 request-to-send, /U0RTS
     699     Pin UART1 : UART 0 transmit data, U0TXD
     700     Pin UART0 : UART 0 receive data, U0RXD
    701701   */
    702702  MCF_GPIO_PDDR_UART = 0;
  • c/src/lib/libbsp/m68k/mcf5329/startup/init5329.c

    r32b8506 rd4b4664b  
    3232  register uint32_t *dp, *sp;
    3333
    34   /* 
     34  /*
    3535   * Initialize the hardware
    3636   */
    3737  init_main();
    3838
    39   /* 
    40    * Copy the vector table to RAM 
     39  /*
     40   * Copy the vector table to RAM
    4141   */
    4242
     
    5151  _wr_vbr((uint32_t) _VBR);
    5252
    53   /* 
    54    * Move initialized data from ROM to RAM. 
     53  /*
     54   * Move initialized data from ROM to RAM.
    5555   */
    5656  if (_data_src_start != _data_dest_start) {
     
    6262  }
    6363
    64   /* 
    65    * Zero uninitialized data 
     64  /*
     65   * Zero uninitialized data
    6666   */
    6767
  • c/src/lib/libbsp/m68k/mrm332/console/sci.c

    r32b8506 rd4b4664b  
    3737*
    3838*****************************************************************************/
    39 
    4039
    4140/*****************************************************************************
     
    7877
    7978
    80 
    8179/*****************************************************************************
    8280  Section A - Include Files
     
    9492
    9593
    96 
    9794/*****************************************************************************
    9895  Section B - Manifest Constants
     
    121118
    122119
    123 
    124120/*****************************************************************************
    125121  Section C - External Data
     
    128124
    129125
    130 
    131126/*****************************************************************************
    132127  Section D - External Functions
    133128*****************************************************************************/
    134 
    135129
    136130
     
    208202
    209203
    210 
    211204/*****************************************************************************
    212205  Section F - Local Variables
     
    245238static const char SciIdent[]="$Id$";
    246239#endif
    247 
    248240
    249241
     
    267259
    268260static uint16_t  SciRcvBufCount = 0;   /* how many bytes are in the buffer */
    269 
    270261
    271262
     
    304295
    305296
    306 
    307297/*
    308298 *                              SECTION 0
     
    329319
    330320
    331 
    332321/****************************************************************************
    333322* Func:     SciGetTermiosHandlers
     
    351340    }
    352341}
    353 
    354342
    355343
     
    414402
    415403
    416 
    417404/*
    418405 *                              SECTION 1
     
    456443
    457444
    458 
    459445/****************************************************************************
    460446* Func:     SciRcvBufPutChar
     
    491477
    492478
    493 
    494479/****************************************************************************
    495480* Func:     SciRcvBufFlush
     
    521506}
    522507#endif
    523 
    524508
    525509
     
    598582
    599583
    600 
    601584/****************************************************************************
    602585* Func:     SciInterruptClose
     
    622605
    623606
    624 
    625607/****************************************************************************
    626608* Func:     SciInterruptWrite
     
    666648    return 1;                                   /* return success */
    667649}
    668 
    669650
    670651
     
    757738
    758739
    759 
    760740/*
    761741 *
     
    819799
    820800
    821 
    822801/****************************************************************************
    823802* Func:     SciPolledClose
     
    843822
    844823
    845 
    846824/****************************************************************************
    847825* Func:     SciPolledRead
     
    869847    return -1;                              /* return error */
    870848}
    871 
    872849
    873850
     
    913890    return written;                             /* return count */
    914891}
    915 
    916892
    917893
     
    963939    return RTEMS_SUCCESSFUL;
    964940}
    965 
    966941
    967942
     
    1009984
    1010985
    1011 
    1012986/****************************************************************************
    1013987* Func:     SciClose
     
    10471021
    10481022
    1049 
    10501023/****************************************************************************
    10511024* Func:     SciRead
     
    11061079    return RTEMS_SUCCESSFUL;
    11071080}
    1108 
    11091081
    11101082
     
    11581130
    11591131
    1160 
    11611132/****************************************************************************
    11621133* Func:     SciControl
     
    12181189
    12191190
    1220 
    12211191/*
    12221192 *
     
    12641234
    12651235
    1266 
    12671236/****************************************************************************
    12681237* Func:     SciSetParity
     
    13051274
    13061275
    1307 
    13081276/****************************************************************************
    13091277* Func:     SciSetDataBits
     
    13391307    return;
    13401308}
    1341 
    13421309
    13431310
     
    13811348
    13821349
    1383 
    13841350/****************************************************************************
    13851351* Func:     SciEnableTransmitter, SciDisableTransmitter
     
    14111377    *SCCR1 &= SCI_DISABLE_RCVR;
    14121378}
    1413 
    14141379
    14151380
     
    14701435
    14711436
    1472 
    14731437/****************************************************************************
    14741438* Func:     SciReadCharWait
     
    15251489
    15261490
    1527 
    15281491/****************************************************************************
    15291492* Func:     SciCharAvailable
     
    15411504
    15421505
    1543 
    15441506/****************************************************************************
    15451507* Func:     SciSendBreak
     
    15661528    return;
    15671529}
    1568 
    15691530
    15701531
     
    16071568}
    16081569#endif
    1609 
    16101570
    16111571
  • c/src/lib/libbsp/m68k/mrm332/console/sci.h

    r32b8506 rd4b4664b  
    4343#define SCI_IOCTL_MODE_9600             0x81    /* 9600,n,8,1 download mode */
    4444#define SCI_IOCTL_MODE_9_BIT            0x82    /* 9600,forced,8,1 command mode */
    45 
    4645
    4746
     
    8786
    8887
    89 
    9088/*  SCI Control Register 1  (SCCR1)  $FFFC0A
    9189
     
    112110    | +---------------------------------------  14 loop mode
    113111    +-----------------------------------------  15 unused
    114  
     112
    115113    0 0 0 0 - 0 0 0 0 - 0 0 0 0 - 0 0 0 0       reset value
    116114*/
     
    152150#define SCI_LOOPBACK_MODE       0x4000          /* 0100-0000-0000-0000 */
    153151#define SCI_SCCR1_UNUSED        0x8000          /* 1000-0000-0000-0000 */
    154 
    155152
    156153
     
    179176    | +---------------------------------------  14 always zero
    180177    +-----------------------------------------  15 always zero
    181  
     178
    182179    0 0 0 0 - 0 0 0 1 - 1 0 0 0 - 0 0 0 0       reset value
    183180*/
     
    203200
    204201
    205 
    206202/*******************************************************************************
    207203  Function prototypes
  • c/src/lib/libbsp/m68k/mvme167/network/network.c

    r32b8506 rd4b4664b  
    18511851    #endif
    18521852  }
    1853  
     1853
    18541854  /*
    18551855   * In case the ISR discovers there are no resources it reclaims
  • c/src/lib/libbsp/m68k/ods68302/startup/m68k-stub.c

    r32b8506 rd4b4664b  
    167167               FPCONTROL,FPSTATUS,FPIADDR
    168168              };
    169 
    170169
    171170
  • c/src/lib/libbsp/m68k/shared/gdbstub/m68k-stub.c

    r32b8506 rd4b4664b  
    152152#define highhex(x) gdb_hexchars [(x >> 4) & 0xf]
    153153#define lowhex(x) gdb_hexchars [x & 0xf]
    154 
    155154
    156155
  • c/src/lib/libbsp/m68k/uC5282/console/console.c

    r32b8506 rd4b4664b  
    3838static void
    3939_BSP_null_char( char c )
    40 { 
     40{
    4141        int level;
    4242
     
    170170   value and sets it. At the moment this just sets the baud rate.
    171171
    172    Note: The highest baudrate is 115200 as this stays within 
     172   Note: The highest baudrate is 115200 as this stays within
    173173   an error of +/- 5% at 25MHz processor clock
    174174 ***************************************************************************/
     
    402402   Function : IntUartInterruptWrite
    403403
    404    Description : This writes a single character to the appropriate uart 
     404   Description : This writes a single character to the appropriate uart
    405405   channel. This is either called during an interrupt or in the user's task
    406    to initiate a transmit sequence. Calling this routine enables Tx 
     406   to initiate a transmit sequence. Calling this routine enables Tx
    407407   interrupts.
    408408 ***************************************************************************/
     
    530530        while ( ( index < count ) && ( index < RX_BUFFER_SIZE ) )
    531531        {
    532                 /* copy data byte */ 
     532                /* copy data byte */
    533533                buffer[index] = info->rx_buffer[info->rx_out];
    534534                index++;
     
    557557   Function : IntUartPollRead
    558558
    559    Description : This reads a character from the internal uart. It returns 
     559   Description : This reads a character from the internal uart. It returns
    560560   to the caller without blocking if not character is waiting.
    561561 ***************************************************************************/
     
    573573   Function : IntUartPollWrite
    574574
    575    Description : This writes out each character in the buffer to the 
    576    appropriate internal uart channel waiting till each one is sucessfully 
     575   Description : This writes out each character in the buffer to the
     576   appropriate internal uart channel waiting till each one is sucessfully
    577577   transmitted.
    578578 ***************************************************************************/
     
    612612        for ( chan = 0; chan < MAX_UART_INFO; chan++ )
    613613                IntUartInfo[chan].iomode = TERMIOS_IRQ_DRIVEN;
    614         IntUartInitialize(); 
     614        IntUartInitialize();
    615615
    616616        /* Register the console port */
     
    650650   Function : console_open
    651651
    652    Description : This actually opens the device depending on the minor 
     652   Description : This actually opens the device depending on the minor
    653653   number set during initialisation. The device specific access routines are
    654654   passed to termios when the devices is opened depending on whether it is
  • c/src/lib/libbsp/m68k/uC5282/include/bsp.h

    r32b8506 rd4b4664b  
    1111 *  http://www.rtems.com/license/LICENSE.
    1212 */
    13  
     13
    1414#ifndef _BSP_H
    1515#define _BSP_H
  • c/src/lib/libbsp/m68k/uC5282/network/network.c

    r32b8506 rd4b4664b  
    163163{
    164164    MCF5282_FEC_EIR = MCF5282_FEC_EIR_RXF;
    165     MCF5282_FEC_EIMR &= ~MCF5282_FEC_EIMR_RXF;   
     165    MCF5282_FEC_EIMR &= ~MCF5282_FEC_EIMR_RXF;
    166166    enet_driver[0].rxInterrupts++;
    167167    rtems_event_send(enet_driver[0].rxDaemonTid, RX_INTERRUPT_EVENT);
     
    172172{
    173173    MCF5282_FEC_EIR = MCF5282_FEC_EIR_TXF;
    174     MCF5282_FEC_EIMR &= ~MCF5282_FEC_EIMR_TXF;   
     174    MCF5282_FEC_EIMR &= ~MCF5282_FEC_EIMR_TXF;
    175175    enet_driver[0].txInterrupts++;
    176176    rtems_event_send(enet_driver[0].txDaemonTid, TX_INTERRUPT_EVENT);
     
    277277     *   No loopback
    278278     */
    279     MCF5282_FEC_RCR = MCF5282_FEC_RCR_MAX_FL(MAX_MTU_SIZE) | 
     279    MCF5282_FEC_RCR = MCF5282_FEC_RCR_MAX_FL(MAX_MTU_SIZE) |
    280280                      MCF5282_FEC_RCR_MII_MODE;
    281281
     
    548548    nAdded = 0;
    549549    firstTxBd = sc->txBdBase + sc->txBdHead;
    550    
     550
    551551    while (m != NULL) {
    552         /* 
     552        /*
    553553         * Wait for buffer descriptor to become available
    554554         */
     
    571571
    572572                rtems_interrupt_disable(level);
    573                 MCF5282_FEC_EIMR |= MCF5282_FEC_EIMR_TXF;   
     573                MCF5282_FEC_EIMR |= MCF5282_FEC_EIMR_TXF;
    574574                rtems_interrupt_enable(level);
    575575                sc->txRawWait++;
     
    581581            }
    582582        }
    583    
     583
    584584        /*
    585585         * Don't set the READY flag on the first fragment
     
    587587         */
    588588        status = nAdded ? MCF5282_FEC_TxBD_R : 0;
    589    
     589
    590590        /*
    591591         * The IP fragmentation routine in ip_output
     
    666666         * Wait for packet
    667667         */
    668         rtems_bsdnet_event_receive(START_TRANSMIT_EVENT, 
    669                                     RTEMS_EVENT_ANY | RTEMS_WAIT, 
    670                                     RTEMS_NO_TIMEOUT, 
     668        rtems_bsdnet_event_receive(START_TRANSMIT_EVENT,
     669                                    RTEMS_EVENT_ANY | RTEMS_WAIT,
     670                                    RTEMS_NO_TIMEOUT,
    671671                                    &events);
    672672
     
    837837                                            fixed ? "fixed" : "auto-negotiate",
    838838                                            speed,
    839                                             full ? "full" : "half"); 
     839                                            full ? "full" : "half");
    840840    }
    841841    printf(" EIR:%8.8lx  ",  MCF5282_FEC_EIR);
  • c/src/lib/libbsp/m68k/uC5282/start/start.S

    r32b8506 rd4b4664b  
    299299.align 4
    300300    PUBLIC (_uhoh)
    301 SYM(_uhoh): 
     301SYM(_uhoh):
    302302    nop                 | Leave spot for breakpoint
    303     stop    #0x2700             | Stop with interrupts disabled 
     303    stop    #0x2700             | Stop with interrupts disabled
    304304    bra.w   SYM(_uhoh)          | Stuck forever
    305305
     
    337337    sub.l  #1,d0
    338338    bne.s  vectcpy
    339      
     339
    340340    /*
    341341     * Remainder of the startup code is handled by C code
    342342     */
    343343    jmp SYM(Init5282)       | Start C code (which never returns)
    344    
     344
    345345/***************************************************************************
    346346   Function : CopyDataClearBSSAndStart
    347347
    348    Description : Copy DATA segment, Copy SRAM segment, clear BSS segment, 
     348   Description : Copy DATA segment, Copy SRAM segment, clear BSS segment,
    349349   start C program. Assume that DATA and BSS sizes are multiples of 4.
    350350 ***************************************************************************/
     
    355355    lea SYM(_data_dest_start),a0        | Get start of DATA in RAM
    356356    lea SYM(_data_src_start),a2     | Get start of DATA in ROM
    357         sub.l   #SYM(_header_offset),a2          | Change source by the amount of the header offset 
     357        sub.l   #SYM(_header_offset),a2          | Change source by the amount of the header offset
    358358    cmpl    a0,a2                   | Are they the same?
    359359    beq.s   NODATACOPY              | Yes, no copy necessary
     
    366366    bcs.s   DATACOPYLOOP                | No, skip
    367367NODATACOPY:
    368        
     368
    369369/* Now, clear BSS */
    370370        lea _clear_start,a0     | Get start of BSS
     
    390390        nop
    391391        trap    #14
    392         bra     MULTI_TASK_EXIT     
     392        bra     MULTI_TASK_EXIT
    393393
    394394
  • c/src/lib/libbsp/m68k/uC5282/startup/bspstart.c

    r32b8506 rd4b4664b  
    1515 *  found in the file LICENSE in this distribution or at
    1616 *  http://www.rtems.com/license/LICENSE.
    17  * 
     17 *
    1818 *  $Id$
    1919 */
     
    2222#include <rtems/error.h>
    2323#include <errno.h>
    24  
     24
    2525/*
    2626 * Location of 'VME' access
     
    5454 * and only a partial clear will be done (INVI = BIT 21 or INVD = BIT 20 set),
    5555 * then cache corruption may  occur.
    56  * 
     56 *
    5757 * 6.2 Workaround
    5858 * All loads of the CACR that perform a cache clear operation (CINV = BIT 24)
     
    6464 * Buffered writes must be disabled as described in "MCF5282 Chip Errata",
    6565 * MCF5282DE, Rev. 6, 5/2009:
    66  *   SECF124: Buffered Write May Be Executed Twice 
    67  *   Errata type: Silicon 
    68  *   Affected component: Cache 
     66 *   SECF124: Buffered Write May Be Executed Twice
     67 *   Errata type: Silicon
     68 *   Affected component: Cache
    6969 *   Description: If buffered writes are enabled using the CACR or ACR
    7070 *                registers, the imprecise write transaction generated
    71  *                by a buffered write may be executed twice. 
    72  *   Workaround: Do not enable buffered writes in the CACR or ACR registers: 
    73  *               CACR[8] = DBWE (default buffered write enable) must be 0 
    74  *               ACRn[5] = BUFW (buffered write enable) must be 0 
    75  *   Fix plan: Currently, there are no plans to fix this. 
     71 *                by a buffered write may be executed twice.
     72 *   Workaround: Do not enable buffered writes in the CACR or ACR registers:
     73 *               CACR[8] = DBWE (default buffered write enable) must be 0
     74 *               ACRn[5] = BUFW (buffered write enable) must be 0
     75 *   Fix plan: Currently, there are no plans to fix this.
    7676 */
    7777#define m68k_set_cacr_nop(_cacr) asm volatile ("movec %0,%%cacr\n\tnop" : : "d" (_cacr))
     
    283283   */
    284284  MCF5282_CS1_CSAR = MCF5282_CS_CSAR_BA(VME_ONE_BASE);
    285   MCF5282_CS1_CSMR = MCF5282_CS_CSMR_BAM_16M | 
     285  MCF5282_CS1_CSMR = MCF5282_CS_CSMR_BAM_16M |
    286286                     MCF5282_CS_CSMR_CI |
    287287                     MCF5282_CS_CSMR_SC |
     
    291291  MCF5282_CS1_CSCR = MCF5282_CS_CSCR_PS_16;
    292292  MCF5282_CS2_CSAR = MCF5282_CS_CSAR_BA(VME_TWO_BASE);
    293   MCF5282_CS2_CSMR = MCF5282_CS_CSMR_BAM_16M | 
     293  MCF5282_CS2_CSMR = MCF5282_CS_CSMR_BAM_16M |
    294294                     MCF5282_CS_CSMR_CI |
    295295                     MCF5282_CS_CSMR_SC |
     
    512512trampoline (rtems_vector_number v)
    513513{
    514     if (handlerTab[v].func) 
     514    if (handlerTab[v].func)
    515515        (*handlerTab[v].func)(handlerTab[v].arg, (unsigned long)v);
    516516}
     
    606606                        MCF5282_EPORT_EPIER |= 1 << source;
    607607                    else
    608                         *(&MCF5282_INTC0_ICR1 + (source - 1)) = 
     608                        *(&MCF5282_INTC0_ICR1 + (source - 1)) =
    609609                                                       MCF5282_INTC_ICR_IL(l) |
    610610                                                       MCF5282_INTC_ICR_IP(p);
     
    692692  size_t i;
    693693  const char *cp;
    694    
     694
    695695  if (buf == NULL)
    696696    return;
     
    710710        default:                     cp = "??";                 break;
    711711      }
    712       i += snprintf(buf+i, capacity-i, cp); 
     712      i += snprintf(buf+i, capacity-i, cp);
    713713      if (i >= capacity)
    714714        break;
     
    716716      if (rsr == 0)
    717717        break;
    718       i += snprintf(buf+i, capacity-i, ", "); 
     718      i += snprintf(buf+i, capacity-i, ", ");
    719719      if (i >= capacity)
    720720        break;
  • c/src/lib/libbsp/m68k/uC5282/startup/init5282.c

    r32b8506 rd4b4664b  
    33 * has been provided by the start.S code. No normal C or RTEMS
    44 * functions can be called from here.
    5  * 
     5 *
    66 * This routine is pretty simple for the uC5282 because all the hard
    77 * work has been done by the bootstrap dBUG code.
     
    2727{
    2828    extern void CopyDataClearBSSAndStart (void);
    29    
     29
    3030    /*
    3131     * Copy data, clear BSS and call boot_card()
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