Changeset d49e8f8 in rtems


Ignore:
Timestamp:
Sep 27, 2004, 9:57:50 PM (15 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Children:
df5f3ca
Parents:
a3fab15
Message:

2004-09-27 Greg Menke <gregory.menke@…>

PR 606/bsps

  • bootloader/pci.c: Fixed IO remapping so buses >= 1 are remapped. Reduced PCI space to match bat2. Fixed incorrect region size calculation in pci_read_bases. Set PCI latency timers to known sane values. Changed bridge PCI settings to minimum sane instead of whatever sounded neat in the PCI spec. Force pf regions to memory mapped to preserve byte access.
Location:
c/src/lib/libbsp/powerpc/shared
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/powerpc/shared/ChangeLog

    ra3fab15 rd49e8f8  
    1 2003-11-01      Greg Menke <gregory.menke@gsfc.nasa.gov>
     12004-09-27      Greg Menke <gregory.menke@gsfc.nasa.gov>
    22
    33        PR 606/bsps
     
    99        memory mapped to preserve byte access.
    1010
     11
     122004-09-27      Greg Menke <gregory.menke@gsfc.nasa.gov>
     13
     14        PR 606/bsps
     15        * bootloader/pci.c: Fixed IO remapping so buses >= 1 are remapped.
     16        Reduced PCI space to match bat2.  Fixed incorrect region size
     17        calculation in pci_read_bases.  Set PCI latency timers to known
     18        sane values.  Changed bridge PCI settings to minimum sane instead
     19        of whatever sounded neat in the PCI spec.  Force pf regions to
     20        memory mapped to preserve byte access.
     21
    11222003-07-16      Greg Menke <gregory.menke@gsfc.nasa.gov>
     23
    1224        PR 432/bsps
    1325        * bootloader/pci.c: Re-instated code that prevents remapping small
  • c/src/lib/libbsp/powerpc/shared/bootloader/pci.c

    ra3fab15 rd49e8f8  
    1313 *  http://www.rtems.com/license/LICENSE.
    1414 *
    15  * $Id$
     15 * pci.c,v 1.3 2003/06/13 17:39:44 joel Exp
    1616 */
    1717
     
    2626#include <bsp/consoleIo.h>
    2727
    28 
    29 
    3028typedef unsigned int u32;
    31 
    3229
    3330/*
     
    3532#define PCI_DEBUG
    3633*/
    37 
    3834
    3935/* Used to reorganize PCI space on stupid machines which spread resources
     
    235231   **
    236232   ** Gregm, 7/16/2003
     233   **
     234   ** Gregm, changed 11/2003 so IO devices only on bus 0 zero are not
     235   ** remapped.  This covers the builtin pc-like io devices- but
     236   ** properly maps IO devices on higher busses.
    237237   */
    238    if( r->dev->bus->number <= 1 )
     238   if( r->dev->bus->number == 0 )
    239239   {
    240240   if ((r->type==PCI_BASE_ADDRESS_SPACE_IO)
     
    509509#define BUS0_IO_END             0x1ffff
    510510#define BUS0_MEM_START          0x1000000
    511 #define BUS0_MEM_END            0xaffffff
     511#define BUS0_MEM_END            0x3f00000
    512512
    513513#define BUSREST_IO_START        0x20000
    514514#define BUSREST_IO_END          0x7ffff
    515 #define BUSREST_MEM_START       0xb000000
     515#define BUSREST_MEM_START       0x4000000
    516516#define BUSREST_MEM_END        0x10000000
    517517
     
    571571           PCI_BASE_ADDRESS_MEM_TYPE_64)) {
    572572         pci_write_config_dword(r->dev,
    573                                 PCI_BASE_ADDRESS_1+
    574                                 (r->reg<<2),
     573                                PCI_BASE_ADDRESS_1+(r->reg<<2),
    575574                                0);
    576575      }
     
    810809         r->type = l&~PCI_BASE_ADDRESS_IO_MASK;
    811810         r->base = l&PCI_BASE_ADDRESS_IO_MASK;
    812          r->size = ~(ml&PCI_BASE_ADDRESS_IO_MASK)+1;
     811         /* r->size = ~(ml&PCI_BASE_ADDRESS_IO_MASK)+1; */
    813812      } else {
    814813         r->type = l&~PCI_BASE_ADDRESS_MEM_MASK;
    815814         r->base = l&PCI_BASE_ADDRESS_MEM_MASK;
    816          r->size = ~(ml&PCI_BASE_ADDRESS_MEM_MASK)+1;
    817       }
     815         /* r->size = ~(ml&PCI_BASE_ADDRESS_MEM_MASK)+1; */
     816      }
     817
     818      /* find the first bit set to one after the base
     819         address type bits to find length of region */
     820      {
     821         unsigned int c= 16 , val= 0;
     822         while( !(val= ml & c) ) c <<= 1;
     823         r->size = val;
     824      }
     825
     826#ifdef PCI_DEBUG
     827      printk("   readbase bus %d, (%04x:%04x), base %08x, size %08x, type %d\n",
     828             r->dev->bus->number,
     829             r->dev->vendor,
     830             r->dev->device,
     831             r->base,
     832             r->size,
     833             r->type );
     834#endif
     835
    818836      /* Check for the blacklisted entries */
    819837      insert_resource(r);
     
    11781196      pdev= childbus->self;
    11791197
     1198      pcibios_write_config_byte(pdev->bus->number, pdev->devfn, PCI_LATENCY_TIMER,     0x80 );
     1199      pcibios_write_config_byte(pdev->bus->number, pdev->devfn, PCI_SEC_LATENCY_TIMER, 0x80 );
     1200
    11801201      {
    11811202         struct _addr_start   addrhold;
     
    12011222
    12021223         /*
    1203          **use the current values & the saved ones to figure out
     1224         ** use the current values & the saved ones to figure out
    12041225         ** the address spaces for the bridge
    12051226         */
     
    12541275
    12551276
     1277
    12561278         if( astart.start_prefetch == addrhold.start_prefetch )
    12571279         {
     
    12731295         pcibios_write_config_dword(pdev->bus->number, pdev->devfn, PCI_PREF_LIMIT_UPPER32, 0);
    12741296         pcibios_write_config_word(pdev->bus->number, pdev->devfn, PCI_PREF_MEMORY_LIMIT, limit16 );
    1275 
    12761297#endif
    12771298
    12781299#ifdef WRITE_BRIDGE_ENABLE
    1279          pcibios_write_config_word(pdev->bus->number, pdev->devfn, PCI_BRIDGE_CONTROL, (unsigned16)( PCI_BRIDGE_CTL_PARITY |
    1280                                                                                                      PCI_BRIDGE_CTL_SERR ));
    1281 
    1282          pcibios_write_config_word(pdev->bus->number, pdev->devfn, PCI_COMMAND, (unsigned16)( PCI_COMMAND_IO |
     1300         pcibios_write_config_word(pdev->bus->number,
     1301                                   pdev->devfn,
     1302                                   PCI_BRIDGE_CONTROL,
     1303                                   (unsigned16)( 0 ));
     1304
     1305         pcibios_write_config_word(pdev->bus->number,
     1306                                   pdev->devfn,
     1307                                   PCI_COMMAND,
     1308                                   (unsigned16)( PCI_COMMAND_IO |
    12831309                                                                                              PCI_COMMAND_MEMORY |
    1284                                                                                               PCI_COMMAND_MASTER |
    1285                                                                                               PCI_COMMAND_PARITY |
    1286                                                                                               PCI_COMMAND_SERR ));
     1310                                                 PCI_COMMAND_MASTER ));
    12871311#endif
    12881312      }
     
    13201344            while( (r= enum_device_resources( pdev, i++ )) )
    13211345            {
    1322                if( r->type & PCI_BASE_ADDRESS_MEM_PREFETCH )
     1346               /*
     1347               ** Force all memory spaces to be non-prefetchable because
     1348               ** on the pci bus, byte-wise reads against prefetchable
     1349               ** memory are applied as 32 bit reads, which is a pain
     1350               ** when you're trying to talk to hardware.  This is a
     1351               ** little sub-optimal because the algorithm doesn't sort
     1352               ** the address regions to pack them in, OTOH, perhaps its
     1353               ** not so bad because the inefficient packing will help
     1354               ** avoid buffer overflow/underflow problems.
     1355               */
     1356#if 0
     1357               if( (r->type & PCI_BASE_ADDRESS_MEM_PREFETCH) )
    13231358               {
    13241359                  /* prefetchable space */
     
    13341369#endif
    13351370               }
    1336                else if( r->type & PCI_BASE_ADDRESS_SPACE_IO )
     1371#endif
     1372               if( r->type & PCI_BASE_ADDRESS_SPACE_IO )
    13371373               {
    13381374                  /* io space */
     
    14371473
    14381474   print_pci_resources("Allocated PCI resources:\n");
     1475
     1476#if 0
     1477   print_pci_info();
     1478#endif
    14391479}
    14401480
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