Changeset d4316537 in rtems


Ignore:
Timestamp:
Jul 3, 2016, 3:26:50 PM (3 years ago)
Author:
Pavel Pisa <pisa@…>
Branches:
master
Children:
2b885d6
Parents:
abea02a8
git-author:
Pavel Pisa <pisa@…> (07/03/16 15:26:50)
git-committer:
Pavel Pisa <pisa@…> (07/04/16 13:55:57)
Message:

bsps/arm: Change code to explicit selection of cache implementation for ARM BSPs.

The original ARM architecture wide cache_.h is changed to dummy version
for targets not implementing/enablig cache at all.

The ARM targets equipped by cache should include
appropriate implementation.

Next options are available for now

c/src/lib/libbsp/arm/shared/armv467ar-basic-cache/cache_.h

basic ARM cache integrated on the CPU core directly
which requires only CP15 oparations

c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h

support for case where ARM L2C-310 cache controller
is used. It is accessible as mmaped peripheral.

c/src/lib/libbsp/arm/shared/armv7m/include/cache_.h

Cortex-M specific cache support

Location:
c/src/lib
Files:
1 added
9 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/arm/beagle/Makefile.am

    rabea02a8 rd4316537  
    127127# Cache
    128128libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
    129 libbsp_a_SOURCES += ../../../libcpu/arm/shared/include/cache_.h
    130 libbsp_a_CPPFLAGS += -I$(srcdir)/../../../libcpu/arm/shared/include
     129libbsp_a_SOURCES += ../shared/include/arm-cache-l1.h
     130libbsp_a_SOURCES += ../shared/armv467ar-basic-cache/cache_.h
     131libbsp_a_CPPFLAGS += -I$(srcdir)/../shared/armv467ar-basic-cache
    131132
    132133###############################################################################
  • c/src/lib/libbsp/arm/csb336/Makefile.am

    rabea02a8 rd4316537  
    1111
    1212include_bsp_HEADERS =
     13libbsp_a_CPPFLAGS =
    1314
    1415nodist_include_HEADERS = include/bspopts.h
     
    5253# Cache
    5354libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
    54 libbsp_a_SOURCES += ../../shared/include/cache_.h
    55 libbsp_a_CPPFLAGS = -I$(srcdir)/../../shared/include
     55libbsp_a_SOURCES += ../shared/include/arm-cache-l1.h
     56libbsp_a_SOURCES += ../shared/armv467ar-basic-cache/cache_.h
     57libbsp_a_CPPFLAGS += -I$(srcdir)/../shared/armv467ar-basic-cache
    5658
    5759if HAS_NETWORKING
  • c/src/lib/libbsp/arm/csb337/Makefile.am

    rabea02a8 rd4316537  
    1414
    1515include_bsp_HEADERS =
     16libbsp_a_CPPFLAGS =
    1617
    1718if ENABLE_UMON
     
    8990# Cache
    9091libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
    91 libbsp_a_SOURCES += ../../shared/include/cache_.h
    92 libbsp_a_CPPFLAGS = -I$(srcdir)/../../shared/include
     92libbsp_a_SOURCES += ../shared/include/arm-cache-l1.h
     93libbsp_a_SOURCES += ../shared/armv467ar-basic-cache/cache_.h
     94libbsp_a_CPPFLAGS += -I$(srcdir)/../shared/armv467ar-basic-cache
    9395
    9496if HAS_NETWORKING
  • c/src/lib/libbsp/arm/lpc32xx/Makefile.am

    rabea02a8 rd4316537  
    143143# Cache
    144144libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
    145 libbsp_a_SOURCES += ../../../libcpu/arm/shared/include/cache_.h
    146 libbsp_a_CPPFLAGS += -I$(srcdir)/../../../libcpu/arm/shared/include
     145libbsp_a_SOURCES += ../shared/include/arm-cache-l1.h
     146libbsp_a_SOURCES += ../shared/armv467ar-basic-cache/cache_.h
     147libbsp_a_CPPFLAGS += -I$(srcdir)/../shared/armv467ar-basic-cache
     148
    147149
    148150# Start hooks
  • c/src/lib/libbsp/arm/raspberrypi/Makefile.am

    rabea02a8 rd4316537  
    5656include_bsp_HEADERS += console/fbcons.h
    5757
    58 include_libcpu_HEADERS = ../../../libcpu/arm/shared/include/cache_.h \
    59     ../../../libcpu/arm/shared/include/arm-cp15.h
     58include_libcpu_HEADERS =  ../../../libcpu/arm/shared/include/arm-cp15.h
    6059
    6160###############################################################################
     
    154153# Cache
    155154libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
    156 libbsp_a_SOURCES += ../../../libcpu/arm/shared/include/cache_.h
    157 libbsp_a_CPPFLAGS += -I$(srcdir)/../../../libcpu/arm/shared/include
     155libbsp_a_SOURCES += ../shared/include/arm-cache-l1.h
     156libbsp_a_SOURCES += ../shared/armv467ar-basic-cache/cache_.h
     157libbsp_a_CPPFLAGS += -I$(srcdir)/../shared/armv467ar-basic-cache
    158158
    159159# Start hooks
  • c/src/lib/libbsp/arm/raspberrypi/preinstall.am

    rabea02a8 rd4316537  
    163163PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/fbcons.h
    164164
    165 $(PROJECT_INCLUDE)/libcpu/cache_.h: ../../../libcpu/arm/shared/include/cache_.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp)
    166         $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/cache_.h
    167 PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/cache_.h
    168 
    169165$(PROJECT_INCLUDE)/libcpu/arm-cp15.h: ../../../libcpu/arm/shared/include/arm-cp15.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp)
    170166        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/arm-cp15.h
  • c/src/lib/libbsp/arm/realview-pbx-a9/Makefile.am

    rabea02a8 rd4316537  
    123123# Cache
    124124libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
    125 libbsp_a_SOURCES += ../../../libcpu/arm/shared/include/cache_.h
    126 libbsp_a_CPPFLAGS += -I$(srcdir)/../../../libcpu/arm/shared/include
     125libbsp_a_SOURCES += ../shared/include/arm-cache-l1.h
     126libbsp_a_SOURCES += ../shared/armv467ar-basic-cache/cache_.h
     127libbsp_a_CPPFLAGS += -I$(srcdir)/../shared/armv467ar-basic-cache
    127128
    128129# Start hooks
  • c/src/lib/libbsp/arm/smdk2410/Makefile.am

    rabea02a8 rd4316537  
    1212
    1313include_bsp_HEADERS =
     14libbsp_a_CPPFLAGS =
    1415
    1516nodist_include_HEADERS = include/bspopts.h
     
    6566# Cache
    6667libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
    67 libbsp_a_SOURCES += ../../shared/include/cache_.h
    68 libbsp_a_CPPFLAGS = -I$(srcdir)/../../shared/include
     68libbsp_a_SOURCES += ../shared/include/arm-cache-l1.h
     69libbsp_a_SOURCES += ../shared/armv467ar-basic-cache/cache_.h
     70libbsp_a_CPPFLAGS += -I$(srcdir)/../shared/armv467ar-basic-cache
    6971
    7072libbsp_a_LIBADD = ../../../libcpu/@RTEMS_CPU@/shared/arm920.rel \
  • c/src/lib/libcpu/arm/shared/include/cache_.h

    rabea02a8 rd4316537  
    44 * @ingroup arm
    55 *
    6  * @brief ARM cache defines and implementation.
     6 * @brief ARM cache dummy include for chips without cache
    77 */
    88
     
    2424#define LIBCPU_ARM_CACHE__H
    2525
    26 #ifdef __ARM_ARCH_5TEJ__
    27   #include <libcpu/arm-cp15.h>
     26/*
     27 * The ARM targets equipped by cache should include
     28 * which kind and implementation they support.
     29 * Next options are available
     30 *
     31 * c/src/lib/libbsp/arm/shared/armv467ar-basic-cache/cache_.h
     32 *   basic ARM cache integrated on the CPU core directly
     33 *   which requires only CP15 oparations
     34 *
     35 * c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h
     36 *   support for case where ARM L2C-310 cache controller
     37 *   is used. It is accessible as mmaped peripheral.
     38 *
     39 * c/src/lib/libbsp/arm/shared/armv7m/include/cache_.h
     40 *   Cortex-M specific cache support
     41 *
     42 * Cache support should be included in BSP Makefile.am
     43 *
     44 * Example how to include cache support
     45 *
     46 * # Cache
     47 * libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
     48 * libbsp_a_SOURCES += ../shared/include/arm-cache-l1.h
     49 * libbsp_a_SOURCES += ../shared/armv467ar-basic-cache/cache_.h
     50 * libbsp_a_CPPFLAGS += -I$(srcdir)/../shared/armv467ar-basic-cache
     51 */
    2852
    29   #define CPU_DATA_CACHE_ALIGNMENT 32
    30   #define CPU_INSTRUCTION_CACHE_ALIGNMENT 32
    31 
    32   static inline void _CPU_cache_flush_1_data_line(const void *d_addr)
    33   {
    34     arm_cp15_data_cache_clean_line(d_addr);
    35   }
    36 
    37   static inline void _CPU_cache_invalidate_1_data_line(const void *d_addr)
    38   {
    39     arm_cp15_data_cache_invalidate_line(d_addr);
    40   }
    41 
    42   static inline void _CPU_cache_freeze_data(void)
    43   {
    44     /* TODO */
    45   }
    46 
    47   static inline void _CPU_cache_unfreeze_data(void)
    48   {
    49     /* TODO */
    50   }
    51 
    52   static inline void _CPU_cache_invalidate_1_instruction_line(const void *d_addr)
    53   {
    54     arm_cp15_instruction_cache_invalidate_line(d_addr);
    55   }
    56 
    57   static inline void _CPU_cache_freeze_instruction(void)
    58   {
    59     /* TODO */
    60   }
    61 
    62   static inline void _CPU_cache_unfreeze_instruction(void)
    63   {
    64     /* TODO */
    65   }
    66 
    67   static inline void _CPU_cache_flush_entire_data(void)
    68   {
    69     arm_cp15_data_cache_test_and_clean();
    70   }
    71 
    72   static inline void _CPU_cache_invalidate_entire_data(void)
    73   {
    74     arm_cp15_data_cache_invalidate();
    75   }
    76 
    77   static inline void _CPU_cache_enable_data(void)
    78   {
    79     rtems_interrupt_level level;
    80     uint32_t ctrl;
    81 
    82     rtems_interrupt_disable(level);
    83     ctrl = arm_cp15_get_control();
    84     ctrl |= ARM_CP15_CTRL_C;
    85     arm_cp15_set_control(ctrl);
    86     rtems_interrupt_enable(level);
    87   }
    88 
    89   static inline void _CPU_cache_disable_data(void)
    90   {
    91     rtems_interrupt_level level;
    92     uint32_t ctrl;
    93 
    94     rtems_interrupt_disable(level);
    95     arm_cp15_data_cache_test_and_clean_and_invalidate();
    96     ctrl = arm_cp15_get_control();
    97     ctrl &= ~ARM_CP15_CTRL_C;
    98     arm_cp15_set_control(ctrl);
    99     rtems_interrupt_enable(level);
    100   }
    101 
    102   static inline void _CPU_cache_invalidate_entire_instruction(void)
    103   {
    104     arm_cp15_instruction_cache_invalidate();
    105   }
    106 
    107   static inline void _CPU_cache_enable_instruction(void)
    108   {
    109     rtems_interrupt_level level;
    110     uint32_t ctrl;
    111 
    112     rtems_interrupt_disable(level);
    113     ctrl = arm_cp15_get_control();
    114     ctrl |= ARM_CP15_CTRL_I;
    115     arm_cp15_set_control(ctrl);
    116     rtems_interrupt_enable(level);
    117   }
    118 
    119   static inline void _CPU_cache_disable_instruction(void)
    120   {
    121     rtems_interrupt_level level;
    122     uint32_t ctrl;
    123 
    124     rtems_interrupt_disable(level);
    125     ctrl = arm_cp15_get_control();
    126     ctrl &= ~ARM_CP15_CTRL_I;
    127     arm_cp15_set_control(ctrl);
    128     rtems_interrupt_enable(level);
    129   }
     53#if defined(__ARM_ARCH_5TEJ__) || defined(__ARM_ARCH_7A__)
     54#warning ARM 5TEJ and ARMv7/Cortex-A cores include usually cache
     55#warning change BSP to include appropriate cache implementation
    13056#endif
    13157
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