Changeset d3c32136 in rtems


Ignore:
Timestamp:
Jul 18, 2008, 3:56:48 PM (11 years ago)
Author:
Thomas Doerfler <Thomas.Doerfler@…>
Branches:
4.10, 4.11, 4.9, master
Children:
6a0898b
Parents:
eb98e4c6
Message:

Changed special purpose register inline functions to macros.
fixed some minors in mpc83xx support
added file for mpc55xx watchdog support

Files:
1 added
12 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/powerpc/ChangeLog

    reb98e4c6 rd3c32136  
     12008-07-18      Sebastian Huber <sebastian.huber@embedded-brains.de>
     2
     3        * shared/clock/clock.c: Update due to powerpc-utilty.h changes.
     4
    152008-07-14      Sebastian Huber <sebastian.huber@embedded-brains.de>
    26
  • c/src/lib/libbsp/powerpc/gen83xx/ChangeLog

    reb98e4c6 rd3c32136  
     12008-07-18      Sebastian Huber <sebastian.huber@embedded-brains.de>
     2
     3        * startup/bspstart.c: Enable cache after CPU initialization.  Clear
     4        only workspace memory area.
     5
    162008-07-18      Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>
    27
  • c/src/lib/libbsp/powerpc/gen83xx/startup/bspstart.c

    reb98e4c6 rd3c32136  
    9292}
    9393
    94 void bsp_calc_mem_layout()
    95 {
    96         size_t workspace_size = rtems_configuration_get_work_space_size();
    97 
    98         /* We clear the workspace here */
    99         Configuration.do_zero_of_workspace = 0;
    100         /*
    101         TODO
    102         mpc83xx_zero_4( bsp_workspace_start, workspace_size);
    103          */
    104         mpc83xx_zero_4( bsp_interrupt_stack_start, bsp_ram_end - bsp_interrupt_stack_start);
    105 
    106         Configuration.work_space_start = bsp_workspace_start;
    107 
    108         BSP_heap_start = (char *) Configuration.work_space_start + workspace_size;
    109 
    110 #ifdef HAS_UBOOT
    111         BSP_heap_end = mpc83xx_uboot_board_info.bi_memstart + mpc83xx_uboot_board_info.bi_memsize;
    112 #else /* HAS_UBOOT */
    113         BSP_heap_end = bsp_ram_end;
    114 #endif /* HAS_UBOOT */
    115 }
    116 
    11794void bsp_start( void)
    11895{
     
    123100        uint32_t interrupt_stack_size = (uint32_t) bsp_interrupt_stack_size;
    124101
     102        size_t workspace_size = rtems_configuration_get_work_space_size();
     103
    125104        /*
    126105         * Get CPU identification dynamically. Note that the get_ppc_cpu_type() function
     
    130109        myCpuRevision = get_ppc_cpu_revision();
    131110
    132         /* Determine heap and workspace placement */
    133         bsp_calc_mem_layout();
     111        /* Basic CPU initialization */
     112        cpu_init();
    134113
    135         cpu_init();
     114        /*
     115         * Enable instruction and data caches. Do not force writethrough mode.
     116         */
     117
     118#if INSTRUCTION_CACHE_ENABLE
     119        rtems_cache_enable_instruction();
     120#endif
     121
     122#if DATA_CACHE_ENABLE
     123        rtems_cache_enable_data();
     124#endif
     125
     126        /* Clear the workspace */
     127        Configuration.do_zero_of_workspace = 0;
     128        mpc83xx_zero_4( bsp_workspace_start, workspace_size);
     129
     130        /* Workspace start */
     131        Configuration.work_space_start = bsp_workspace_start;
     132
     133        /* Heap area */
     134        BSP_heap_start = (char *) Configuration.work_space_start + workspace_size;
     135#ifdef HAS_UBOOT
     136        BSP_heap_end = mpc83xx_uboot_board_info.bi_memstart + mpc83xx_uboot_board_info.bi_memsize;
     137#else /* HAS_UBOOT */
     138        BSP_heap_end = bsp_ram_end;
     139#endif /* HAS_UBOOT */
    136140
    137141        /*
     
    149153
    150154        bsp_clicks_per_usec = BSP_bus_frequency / 4000000;
    151 
    152         /*
    153          * Enable instruction and data caches. Do not force writethrough mode.
    154          */
    155 
    156 #if INSTRUCTION_CACHE_ENABLE
    157         rtems_cache_enable_instruction();
    158 #endif
    159 
    160 #if DATA_CACHE_ENABLE
    161         rtems_cache_enable_data();
    162 #endif
    163155
    164156        /* Initialize exception handler */
  • c/src/lib/libbsp/powerpc/shared/clock/clock.c

    reb98e4c6 rd3c32136  
    125125
    126126        /* Acknowledge decrementer request */
    127         ppc_set_timer_status_register( BOOKE_TSR_DIS);
     127        PPC_SET_SPECIAL_PURPOSE_REGISTER( BOOKE_TSR, BOOKE_TSR_DIS);
    128128
    129129        /* Increment clock ticks */
     
    177177rtems_device_driver Clock_initialize( rtems_device_major_number major, rtems_device_minor_number minor, void *arg)
    178178{
    179         rtems_interrupt_level level;
    180 
    181179        /* Current CPU type */
    182180        ppc_cpu_id_t cpu_type = get_ppc_cpu_type();
     
    212210        if (ppc_cpu_is_bookE()) {
    213211                /* Set decrementer auto-reload value */
    214                 ppc_set_decrementer_auto_reload_register( ppc_clock_decrementer_value);
     212                PPC_SET_SPECIAL_PURPOSE_REGISTER( BOOKE_DECAR, ppc_clock_decrementer_value);
    215213
    216214                /* Install exception handler */
     
    218216
    219217                /* Enable decrementer and auto-reload */
    220                 rtems_interrupt_disable( level);
    221                 ppc_set_timer_control_register( ppc_timer_control_register() | BOOKE_TCR_DIE | BOOKE_TCR_ARE);
    222                 rtems_interrupt_enable( level);
     218                PPC_SET_SPECIAL_PURPOSE_REGISTER_BITS( BOOKE_TCR, BOOKE_TCR_DIE | BOOKE_TCR_ARE);
    223219        } else if (cpu_type == PPC_e300c2 || cpu_type == PPC_e300c3) {
    224220                /* TODO: Not tested for e300c2 */
    225221
    226222                /* Enable auto-reload */
    227                 rtems_interrupt_disable( level);
    228                 ppc_set_hardware_implementation_dependent_register_0( ppc_hardware_implementation_dependent_register_0() | 0x00000040);
    229                 rtems_interrupt_enable( level);
     223                PPC_SET_SPECIAL_PURPOSE_REGISTER_BITS( HID0, 0x00000040);
    230224
    231225                /* Install exception handler */
     
    235229                ++ppc_clock_decrementer_value;
    236230
    237                 rtems_interrupt_disable( level);
    238 
    239231                /* Initialize next time base */
    240232                ppc_clock_next_time_base = ppc_time_base() + ppc_clock_decrementer_value;
     
    242234                /* Install exception handler */
    243235                ppc_exc_set_handler( ASM_DEC_VECTOR, ppc_clock_exception_handler);
    244 
    245                 rtems_interrupt_enable( level);
    246236        }
    247237
     
    258248        if (io == NULL) {
    259249                return RTEMS_SUCCESSFUL;
    260         } else if (ppc_clock_tick == NULL) {
    261                 Clock_initialize( major, minor, 0);
    262250        }
    263251
     
    265253                ppc_clock_tick();
    266254        } else if (io->command == rtems_build_name( 'N', 'E', 'W', ' ')) {
    267                 ppc_clock_tick = io->buffer;
     255                if (io->buffer != NULL) {
     256                        ppc_clock_tick = io->buffer;
     257                } else {
     258                        ppc_clock_tick = ppc_clock_no_tick;
     259                }
    268260        }
    269261
  • c/src/lib/libcpu/powerpc/ChangeLog

    reb98e4c6 rd3c32136  
     12008-07-18      Sebastian Huber <sebastian.huber@embedded-brains.de>
     2
     3        * shared/include/powerpc-utility.h: Changed special purpose register
     4        inline functions to macros.  Added macros to set and clear bits for
     5        SPRs and DCRs.
     6
     7        * new-exceptions/raw_exception.c: The watchdog exception for e200 is
     8        now asynchronous.
     9
     10        * mpc83xx/gtm/gtm.c: Bugfix for some value assignments.
     11
     12        * mpc55xx/include/watchdog.h: New file.
     13
     14        * Makefile.am: Install mpc55xx/include/watchdog.h for MPC55XX.
     15
    1162008-07-18      Thomas Doerfler <thomas.doerfler@embedded-brains.de>
    217
  • c/src/lib/libcpu/powerpc/Makefile.am

    reb98e4c6 rd3c32136  
    430430        mpc55xx/include/edma.h \
    431431        mpc55xx/include/mpc55xx.h \
    432         mpc55xx/include/esci.h
    433 
     432        mpc55xx/include/esci.h \
     433        mpc55xx/include/watchdog.h
    434434
    435435# IRQ
  • c/src/lib/libcpu/powerpc/mpc83xx/gtm/gtm.c

    reb98e4c6 rd3c32136  
    201201        MPC83XX_GTM_CHECK_INDEX( timer);
    202202
    203         reference = mpc83xx.gtm [module].gt_tim_regs [high].gtrfr [low];
     203        *reference = mpc83xx.gtm [module].gt_tim_regs [high].gtrfr [low];
    204204
    205205        return RTEMS_SUCCESSFUL;
     
    223223        MPC83XX_GTM_CHECK_INDEX( timer);
    224224
    225         prescale = mpc83xx.gtm [module].gtpsr [module_timer];
     225        *prescale = mpc83xx.gtm [module].gtpsr [module_timer];
    226226
    227227        return RTEMS_SUCCESSFUL;
  • c/src/lib/libcpu/powerpc/new-exceptions/raw_exception.c

    reb98e4c6 rd3c32136  
    267267        [ASM_BOOKE_DEC_VECTOR]            = PPC_EXC_CLASSIC | PPC_EXC_ASYNC,
    268268        [ASM_BOOKE_FIT_VECTOR]            = PPC_EXC_CLASSIC | PPC_EXC_ASYNC,
    269         [ASM_BOOKE_WDOG_VECTOR]           = PPC_EXC_BOOKE_CRITICAL,
     269        [ASM_BOOKE_WDOG_VECTOR]           = PPC_EXC_BOOKE_CRITICAL | PPC_EXC_ASYNC,
    270270        [ASM_BOOKE_ITLBMISS_VECTOR]       = PPC_EXC_CLASSIC,
    271271        [ASM_BOOKE_DTLBMISS_VECTOR]       = PPC_EXC_CLASSIC,
  • c/src/lib/libcpu/powerpc/preinstall.am

    reb98e4c6 rd3c32136  
    295295        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/mpc55xx/esci.h
    296296PREINSTALL_FILES += $(PROJECT_INCLUDE)/mpc55xx/esci.h
    297 endif
     297
     298$(PROJECT_INCLUDE)/mpc55xx/watchdog.h: mpc55xx/include/watchdog.h $(PROJECT_INCLUDE)/mpc55xx/$(dirstamp)
     299        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/mpc55xx/watchdog.h
     300PREINSTALL_FILES += $(PROJECT_INCLUDE)/mpc55xx/watchdog.h
     301endif
  • c/src/lib/libcpu/powerpc/shared/include/powerpc-utility.h

    reb98e4c6 rd3c32136  
    240240}
    241241
    242 #define PPC_STRINGOF(x) #x
    243 
    244 /* Do not use the following macros.  Use the inline functions instead. */
    245 
    246 #define PPC_INTERNAL_MACRO_RETURN_SPECIAL_PURPOSE_REGISTER( spr) \
    247         uint32_t val; \
    248         asm volatile ( \
    249                 "mfspr %0, " #spr \
    250                 : "=r" (val) \
    251         ); \
     242/**
     243 * @brief Preprocessor magic for stringification of @a x.
     244 */
     245#define PPC_STRINGOF( x) #x
     246
     247/**
     248 * @brief Returns the value of the Special Purpose Register with number @a spr.
     249 *
     250 * @note This macro uses a GNU C extension.
     251 */
     252#define PPC_SPECIAL_PURPOSE_REGISTER( spr) \
     253        ( { \
     254                uint32_t val; \
     255                asm volatile ( \
     256                        "mfspr %0, " PPC_STRINGOF( spr) \
     257                        : "=r" (val) \
     258                ); \
     259                val;\
     260        } )
     261
     262/**
     263 * @brief Sets the Special Purpose Register with number @a spr to the value in
     264 * @a val.
     265 */
     266#define PPC_SET_SPECIAL_PURPOSE_REGISTER( spr, val) \
     267        do { \
     268                asm volatile ( \
     269                        "mtspr " PPC_STRINGOF( spr) ", %0" \
     270                        : \
     271                        : "r" (val) \
     272                ); \
     273        } while (0)
     274
     275/**
     276 * @brief Sets in the Special Purpose Register with number @a spr all bits
     277 * which are set in @a bits.
     278 *
     279 * Interrupts are disabled throughout this operation.
     280 */
     281#define PPC_SET_SPECIAL_PURPOSE_REGISTER_BITS( spr, bits) \
     282        do { \
     283                rtems_interrupt_level level; \
     284                uint32_t val; \
     285                rtems_interrupt_disable( level); \
     286                val = PPC_SPECIAL_PURPOSE_REGISTER( spr); \
     287                val |= bits; \
     288                PPC_SET_SPECIAL_PURPOSE_REGISTER( spr, val); \
     289                rtems_interrupt_enable( level); \
     290        } while (0)
     291
     292/**
     293 * @brief Sets in the Special Purpose Register with number @a spr all bits
     294 * which are set in @a bits.  The previous register value will be masked with
     295 * @a mask.
     296 *
     297 * Interrupts are disabled throughout this operation.
     298 */
     299#define PPC_SET_SPECIAL_PURPOSE_REGISTER_BITS_MASKED( spr, bits, mask) \
     300        do { \
     301                rtems_interrupt_level level; \
     302                uint32_t val; \
     303                rtems_interrupt_disable( level); \
     304                val = PPC_SPECIAL_PURPOSE_REGISTER( spr); \
     305                val &= ~mask; \
     306                val |= bits; \
     307                PPC_SET_SPECIAL_PURPOSE_REGISTER( spr, val); \
     308                rtems_interrupt_enable( level); \
     309        } while (0)
     310
     311/**
     312 * @brief Clears in the Special Purpose Register with number @a spr all bits
     313 * which are set in @a bits.
     314 *
     315 * Interrupts are disabled throughout this operation.
     316 */
     317#define PPC_CLEAR_SPECIAL_PURPOSE_REGISTER_BITS( spr, bits) \
     318        do { \
     319                rtems_interrupt_level level; \
     320                uint32_t val; \
     321                rtems_interrupt_disable( level); \
     322                val = PPC_SPECIAL_PURPOSE_REGISTER( spr); \
     323                val &= ~bits; \
     324                PPC_SET_SPECIAL_PURPOSE_REGISTER( spr, val); \
     325                rtems_interrupt_enable( level); \
     326        } while (0)
     327
     328/**
     329 * @brief Returns the value of the Device Control Register with number @a dcr.
     330 *
     331 * The PowerPC 4XX family has Device Control Registers.
     332 *
     333 * @note This macro uses a GNU C extension.
     334 */
     335#define PPC_DEVICE_CONTROL_REGISTER( dcr) \
     336        ( { \
     337                uint32_t val; \
     338                asm volatile ( \
     339                        "mfdcr %0, " PPC_STRINGOF( dcr) \
     340                        : "=r" (val) \
     341                ); \
     342                val;\
     343        } )
     344
     345/**
     346 * @brief Sets the Device Control Register with number @a dcr to the value in
     347 * @a val.
     348 *
     349 * The PowerPC 4XX family has Device Control Registers.
     350 */
     351#define PPC_SET_DEVICE_CONTROL_REGISTER( dcr, val) \
     352        do { \
     353                asm volatile ( \
     354                        "mtdcr " PPC_STRINGOF( dcr) ", %0" \
     355                        : \
     356                        : "r" (val) \
     357                ); \
     358        } while (0)
     359
     360/**
     361 * @brief Sets in the Device Control Register with number @a dcr all bits
     362 * which are set in @a bits.
     363 *
     364 * Interrupts are disabled throughout this operation.
     365 */
     366#define PPC_SET_DEVICE_CONTROL_REGISTER_BITS( dcr, bits) \
     367        do { \
     368                rtems_interrupt_level level; \
     369                uint32_t val; \
     370                rtems_interrupt_disable( level); \
     371                val = PPC_DEVICE_CONTROL_REGISTER( dcr); \
     372                val |= bits; \
     373                PPC_SET_DEVICE_CONTROL_REGISTER( dcr, val); \
     374                rtems_interrupt_enable( level); \
     375        } while (0)
     376
     377/**
     378 * @brief Sets in the Device Control Register with number @a dcr all bits
     379 * which are set in @a bits.  The previous register value will be masked with
     380 * @a mask.
     381 *
     382 * Interrupts are disabled throughout this operation.
     383 */
     384#define PPC_SET_DEVICE_CONTROL_REGISTER_BITS_MASKED( dcr, bits, mask) \
     385        do { \
     386                rtems_interrupt_level level; \
     387                uint32_t val; \
     388                rtems_interrupt_disable( level); \
     389                val = PPC_DEVICE_CONTROL_REGISTER( dcr); \
     390                val &= ~mask; \
     391                val |= bits; \
     392                PPC_SET_DEVICE_CONTROL_REGISTER( dcr, val); \
     393                rtems_interrupt_enable( level); \
     394        } while (0)
     395
     396/**
     397 * @brief Clears in the Device Control Register with number @a dcr all bits
     398 * which are set in @a bits.
     399 *
     400 * Interrupts are disabled throughout this operation.
     401 */
     402#define PPC_CLEAR_DEVICE_CONTROL_REGISTER_BITS( dcr, bits) \
     403        do { \
     404                rtems_interrupt_level level; \
     405                uint32_t val; \
     406                rtems_interrupt_disable( level); \
     407                val = PPC_DEVICE_CONTROL_REGISTER( dcr); \
     408                val &= ~bits; \
     409                PPC_SET_DEVICE_CONTROL_REGISTER( dcr, val); \
     410                rtems_interrupt_enable( level); \
     411        } while (0)
     412
     413static inline uint32_t ppc_time_base()
     414{
     415        uint32_t val;
     416
     417        CPU_Get_timebase_low( val);
     418
    252419        return val;
    253 
    254 #define PPC_INTERNAL_MACRO_RETURN_SPECIAL_PURPOSE_REGISTER_EXPAND( spr) \
    255         PPC_INTERNAL_MACRO_RETURN_SPECIAL_PURPOSE_REGISTER( spr)
    256 
    257 #define PPC_INTERNAL_MACRO_SET_SPECIAL_PURPOSE_REGISTER( spr, val) \
    258         asm volatile ( \
    259                 "mtspr " #spr ", %0" \
    260                 : \
    261                 : "r" (val) \
    262         );
    263 
    264 #define PPC_INTERNAL_MACRO_SET_SPECIAL_PURPOSE_REGISTER_EXPAND( spr, val) \
    265         PPC_INTERNAL_MACRO_SET_SPECIAL_PURPOSE_REGISTER( spr, val)
    266 
    267 /*
    268  * PPC4xx have Device Control Registers...
    269  */
    270 #define PPC_DEVICE_CONTROL_REGISTER(dcr)                        \
    271   ({uint32_t val;asm volatile ("mfdcr %0," PPC_STRINGOF(dcr)    \
    272                                : "=r" (val)); val;})
    273 
    274 #define PPC_SET_DEVICE_CONTROL_REGISTER(dcr,val)        \
    275   do {                                                  \
    276     asm volatile ("mtdcr " PPC_STRINGOF(dcr)",%0"       \
    277                   :: "r" (val));                        \
    278     } while (0)
    279 
    280 
    281 static inline uint32_t ppc_special_purpose_register_0()
    282 {
    283         PPC_INTERNAL_MACRO_RETURN_SPECIAL_PURPOSE_REGISTER_EXPAND( SPRG0);
    284 }
    285 
    286 static inline void ppc_set_special_purpose_register_0( uint32_t val)
    287 {
    288         PPC_INTERNAL_MACRO_SET_SPECIAL_PURPOSE_REGISTER_EXPAND( SPRG0, val);
    289 }
    290 
    291 static inline uint32_t ppc_special_purpose_register_1()
    292 {
    293         PPC_INTERNAL_MACRO_RETURN_SPECIAL_PURPOSE_REGISTER_EXPAND( SPRG1);
    294 }
    295 
    296 static inline void ppc_set_special_purpose_register_1( uint32_t val)
    297 {
    298         PPC_INTERNAL_MACRO_SET_SPECIAL_PURPOSE_REGISTER_EXPAND( SPRG1, val);
    299 }
    300 
    301 static inline uint32_t ppc_special_purpose_register_2()
    302 {
    303         PPC_INTERNAL_MACRO_RETURN_SPECIAL_PURPOSE_REGISTER_EXPAND( SPRG2);
    304 }
    305 
    306 static inline void ppc_set_special_purpose_register_2( uint32_t val)
    307 {
    308         PPC_INTERNAL_MACRO_SET_SPECIAL_PURPOSE_REGISTER_EXPAND( SPRG2, val);
    309 }
    310 
    311 static inline uint32_t ppc_special_purpose_register_3()
    312 {
    313         PPC_INTERNAL_MACRO_RETURN_SPECIAL_PURPOSE_REGISTER_EXPAND( SPRG3);
    314 }
    315 
    316 static inline void ppc_set_special_purpose_register_3( uint32_t val)
    317 {
    318         PPC_INTERNAL_MACRO_SET_SPECIAL_PURPOSE_REGISTER_EXPAND( SPRG3, val);
    319 }
    320 
    321 static inline uint32_t ppc_special_purpose_register_4()
    322 {
    323         PPC_INTERNAL_MACRO_RETURN_SPECIAL_PURPOSE_REGISTER_EXPAND( SPRG4);
    324 }
    325 
    326 static inline void ppc_set_special_purpose_register_4( uint32_t val)
    327 {
    328         PPC_INTERNAL_MACRO_SET_SPECIAL_PURPOSE_REGISTER_EXPAND( SPRG4, val);
    329 }
    330 
    331 static inline uint32_t ppc_special_purpose_register_5()
    332 {
    333         PPC_INTERNAL_MACRO_RETURN_SPECIAL_PURPOSE_REGISTER_EXPAND( SPRG5);
    334 }
    335 
    336 static inline void ppc_set_special_purpose_register_5( uint32_t val)
    337 {
    338         PPC_INTERNAL_MACRO_SET_SPECIAL_PURPOSE_REGISTER_EXPAND( SPRG5, val);
    339 }
    340 
    341 static inline uint32_t ppc_special_purpose_register_6()
    342 {
    343         PPC_INTERNAL_MACRO_RETURN_SPECIAL_PURPOSE_REGISTER_EXPAND( SPRG6);
    344 }
    345 
    346 static inline void ppc_set_special_purpose_register_6( uint32_t val)
    347 {
    348         PPC_INTERNAL_MACRO_SET_SPECIAL_PURPOSE_REGISTER_EXPAND( SPRG6, val);
    349 }
    350 
    351 static inline uint32_t ppc_special_purpose_register_7()
    352 {
    353         PPC_INTERNAL_MACRO_RETURN_SPECIAL_PURPOSE_REGISTER_EXPAND( SPRG7);
    354 }
    355 
    356 static inline void ppc_set_special_purpose_register_7( uint32_t val)
    357 {
    358         PPC_INTERNAL_MACRO_SET_SPECIAL_PURPOSE_REGISTER_EXPAND( SPRG7, val);
    359 }
    360 
    361 static inline uint32_t ppc_user_special_purpose_register_0()
    362 {
    363         PPC_INTERNAL_MACRO_RETURN_SPECIAL_PURPOSE_REGISTER_EXPAND( USPRG0);
    364 }
    365 
    366 static inline void ppc_set_user_special_purpose_register_0( uint32_t val)
    367 {
    368         PPC_INTERNAL_MACRO_SET_SPECIAL_PURPOSE_REGISTER_EXPAND( USPRG0, val);
    369 }
    370 
    371 static inline uint32_t ppc_timer_control_register()
    372 {
    373         PPC_INTERNAL_MACRO_RETURN_SPECIAL_PURPOSE_REGISTER_EXPAND( BOOKE_TCR);
    374 }
    375 
    376 static inline void ppc_set_timer_control_register( uint32_t val)
    377 {
    378         PPC_INTERNAL_MACRO_SET_SPECIAL_PURPOSE_REGISTER_EXPAND( BOOKE_TCR, val);
    379 }
    380 
    381 static inline uint32_t ppc_timer_status_register()
    382 {
    383         PPC_INTERNAL_MACRO_RETURN_SPECIAL_PURPOSE_REGISTER_EXPAND( BOOKE_TSR);
    384 }
    385 
    386 static inline void ppc_set_timer_status_register( uint32_t val)
    387 {
    388         PPC_INTERNAL_MACRO_SET_SPECIAL_PURPOSE_REGISTER_EXPAND( BOOKE_TSR, val);
    389 }
    390 
    391 static inline uint32_t ppc_decrementer_auto_reload_register()
    392 {
    393         PPC_INTERNAL_MACRO_RETURN_SPECIAL_PURPOSE_REGISTER_EXPAND( BOOKE_DECAR);
    394 }
    395 
    396 static inline void ppc_set_decrementer_auto_reload_register( uint32_t val)
    397 {
    398         PPC_INTERNAL_MACRO_SET_SPECIAL_PURPOSE_REGISTER_EXPAND( BOOKE_DECAR, val);
    399 }
    400 
    401 static inline uint32_t ppc_hardware_implementation_dependent_register_0()
    402 {
    403         PPC_INTERNAL_MACRO_RETURN_SPECIAL_PURPOSE_REGISTER_EXPAND( HID0);
    404 }
    405 
    406 static inline void ppc_set_hardware_implementation_dependent_register_0( uint32_t val)
    407 {
    408         PPC_INTERNAL_MACRO_SET_SPECIAL_PURPOSE_REGISTER_EXPAND( HID0, val);
    409 }
    410 
    411 static inline uint32_t ppc_hardware_implementation_dependent_register_1()
    412 {
    413         PPC_INTERNAL_MACRO_RETURN_SPECIAL_PURPOSE_REGISTER_EXPAND( HID1);
    414 }
    415 
    416 static inline void ppc_set_hardware_implementation_dependent_register_1( uint32_t val)
    417 {
    418         PPC_INTERNAL_MACRO_SET_SPECIAL_PURPOSE_REGISTER_EXPAND( HID1, val);
    419 }
    420 
    421 static inline uint32_t ppc_time_base()
    422 {
    423         uint32_t val;
    424 
    425         CPU_Get_timebase_low( val);
    426 
    427         return val;
    428420}
    429421
    430422static inline void ppc_set_time_base( uint32_t val)
    431423{
    432         PPC_INTERNAL_MACRO_SET_SPECIAL_PURPOSE_REGISTER_EXPAND( TBWL, val);
     424        PPC_SET_SPECIAL_PURPOSE_REGISTER( TBWL, val);
    433425}
    434426
    435427static inline uint32_t ppc_time_base_upper()
    436428{
    437         PPC_INTERNAL_MACRO_RETURN_SPECIAL_PURPOSE_REGISTER_EXPAND( TBRU);
     429        return PPC_SPECIAL_PURPOSE_REGISTER( TBRU);
    438430}
    439431
    440432static inline void ppc_set_time_base_upper( uint32_t val)
    441433{
    442         PPC_INTERNAL_MACRO_SET_SPECIAL_PURPOSE_REGISTER_EXPAND( TBWU, val);
     434        PPC_SET_SPECIAL_PURPOSE_REGISTER( TBWU, val);
    443435}
    444436
     
    458450
    459451.macro LA reg, addr
    460         lis \reg, (\addr)@h
    461         ori \reg, \reg, (\addr)@l
     452        lis     \reg, (\addr)@h
     453        ori     \reg, \reg, (\addr)@l
    462454.endm
    463455
    464456.macro LWI reg, value
    465457        lis \reg, (\value)@h
    466         ori \reg, \reg, (\value)@l
     458        ori     \reg, \reg, (\value)@l
    467459.endm
    468460
    469461.macro LW reg, addr
    470         lis \reg, \addr@ha
    471         lwz \reg, \addr@l(\reg)
     462        lis     \reg, \addr@ha
     463        lwz     \reg, \addr@l(\reg)
    472464.endm
    473465
     
    503495 */
    504496.macro GET_INTERRUPT_MASK mask
    505         mfspr \mask, sprg0
     497        mfspr   \mask, sprg0
    506498.endm
    507499
  • cpukit/score/cpu/powerpc/ChangeLog

    reb98e4c6 rd3c32136  
     12008-07-18      Sebastian Huber <sebastian.huber@embedded-brains.de>
     2
     3        * rtems/powerpc/registers.h: Added masks for BOOKE_TCR fields.
     4
    152008-07-14      Thomas Doerfler <thomas.doerfler@embedded-brains.de>
    26        * rtems/powerpc/registers.h:
  • cpukit/score/cpu/powerpc/rtems/powerpc/registers.h

    reb98e4c6 rd3c32136  
    303303#define BOOKE_TCR       340
    304304#define BOOKE_TCR_WP(x)         (((x)&3)<<30)
     305#define BOOKE_TCR_WP_MASK       (3<<30)
    305306#define BOOKE_TCR_WRC(x)        (((x)&3)<<28)
     307#define BOOKE_TCR_WRC_MASK      (3<<28)
    306308#define BOOKE_TCR_WIE           (1<<27)
    307309#define BOOKE_TCR_DIE           (1<<26)
     
    310312#define BOOKE_TCR_ARE           (1<<22)
    311313#define BOOKE_TCR_WPEXT(x)      (((x)&0xf)<<17)
     314#define BOOKE_TCR_WPEXT_MASK    (0xf<<17)
    312315#define BOOKE_TCR_FPEXT(x)      (((x)&0xf)<<13)
     316#define BOOKE_TCR_FPEXT_MASK    (0xf<<13)
    313317
    314318/**
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