Changeset d389819 in rtems-docs for porting


Ignore:
Timestamp:
Jan 18, 2016, 5:37:40 AM (4 years ago)
Author:
Amar Takhar <amar@…>
Branches:
4.11, master
Children:
f916fca
Parents:
11e1a6f
git-author:
Amar Takhar <amar@…> (01/18/16 05:37:40)
git-committer:
Amar Takhar <verm@…> (05/03/16 00:51:24)
Message:

Convert all Unicode to ASCII(128)

Location:
porting
Files:
9 edited

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Unmodified
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  • porting/code_tuning.rst

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    8888----------------------
    8989
    90 The CPU_ALIGNMENT macro should be set to the CPU’s worst alignment
     90The CPU_ALIGNMENT macro should be set to the CPU's worst alignment
    9191requirement for data types on a byte boundary.  This is typically the
    9292alignment requirement for a C double. This alignment does not take into
  • porting/cpu_init.rst

    r11e1a6f rd389819  
    3939context.  If there is not an easy way to initialize the FP context during
    4040Context_Initialize, then it is usually easier to save an "uninitialized"
    41 FP context here and copy it to the task’s during Context_Initialize.  If
     41FP context here and copy it to the task's during Context_Initialize.  If
    4242this technique is used to initialize the FP contexts, then it is important
    4343to ensure that the state of the floating point unit is in a coherent,
  • porting/cpu_model_variations.rst

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    106106Each of these boards is optimized for a particular project.  The processor
    107107and peripheral set have been chosen to meet a particular set of system
    108 requirements.  The tools in the embedded systems developers’ toolbox must
    109 support their project’s unique board.  RTEMS addresses this issue via the
     108requirements.  The tools in the embedded systems developers toolbox must
     109support their project's unique board.  RTEMS addresses this issue via the
    110110Board Support Package.
    111111
  • porting/idle_thread.rst

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    8787
    8888If the CPU dependent IDLE thread body is implementation centers upon using
    89 a "halt", "idle", or "shutdown" instruction, then don’t forget to put it
     89a "halt", "idle", or "shutdown" instruction, then don't forget to put it
    9090in an infinite loop as the CPU will have to reexecute this instruction
    9191each time the IDLE thread is dispatched.
  • porting/index.rst

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    22RTEMS Porting Guide
    33===================
    4 COPYRIGHT © 1988 - 2015.
     4COPYRIGHT (c) 1988 - 2015.
    55
    66On-Line Applications Research Corporation (OAR).
  • porting/interrupts.rst

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    306306This discussion ignores a lot of the ugly details in a real implementation
    307307such as saving enough registers/state to be able to do something real.
    308 Keep in mind that the goal is to invoke a user’s ISR handler which is
     308Keep in mind that the goal is to invoke a user's ISR handler which is
    309309written in C.  That ISR handler uses a known set of registers thus
    310310allowing the ISR to preserve only those that would normally be corrupted
     
    369369------------------------------
    370370
    371 Does the RTEMS invoke the user’s ISR with the vector number and a pointer
     371Does the RTEMS invoke the user's ISR with the vector number and a pointer
    372372to the saved interrupt frame (1) or just the vector number (0)?
    373373.. code:: c
  • porting/miscellanous.rst

    r11e1a6f rd389819  
    66
    77The ``_CPU_Fatal_halt`` routine is the default fatal error handler. This
    8 routine copies _error into a known place – typically a stack location or
     8routine copies _error into a known place - typically a stack location or
    99a register, optionally disables interrupts, and halts/stops the CPU.  It
    1010is prototyped as follows and is often implemented as a macro:
     
    101101would probably have to be disabled to insure that an interrupt does not
    102102try to access the same "chunk" with the wrong endian.  Another good reason
    103 is that on some CPUs, the endian bit endianness for ALL fetches – both
    104 code and data – so the code will be fetched incorrectly.
     103is that on some CPUs, the endian bit endianness for ALL fetches - both
     104code and data - so the code will be fetched incorrectly.
    105105
    106106The following is an implementation of the ``CPU_swap_u32`` routine that will
     
    143143would probably have to be disabled to insure that an interrupt does not
    144144try to access the same "chunk" with the wrong endian.  Another good reason
    145 is that on some CPUs, the endian bit endianness for ALL fetches – both
    146 code and data – so the code will be fetched incorrectly.
     145is that on some CPUs, the endian bit endianness for ALL fetches - both
     146code and data - so the code will be fetched incorrectly.
    147147
    148148Similarly, here is a portable implementation of the ``CPU_swap_u16``
  • porting/priority_bitmap.rst

    r11e1a6f rd389819  
    8686manner in which a priority is broken into a major and minor components
    8787with the major being the 4 MSB of a priority and minor the 4 LSB.  Thus (0
    88 << 4) + 0 corresponds to priority 0 – the highest priority.  And (15 <<
    89 4) + 14 corresponds to priority 254 – the next to the lowest priority.
     88<< 4) + 0 corresponds to priority 0 - the highest priority.  And (15 <<
     894) + 14 corresponds to priority 254 - the next to the lowest priority.
    9090
    9191If your CPU does not have a "find first bit" instruction, then there are
     
    9595- a series of 16 bit test instructions
    9696
    97 - a "binary search using if’s"
     97- a "binary search using if's"
    9898
    9999- the following algorithm based upon a 16 entry lookup table.  In this pseudo-code, bit_set_table[16] has values which indicate the first bit set:
  • porting/task_context.rst

    r11e1a6f rd389819  
    201201registers assumed to be preserved across subroutine calls
    202202must be preserved.  These registers may be saved in
    203 the task’s context area or on its stack.  However, the
     203the task's context area or on its stack.  However, the
    204204stack pointer and address to resume executing the task
    205205at must be included in the context (normally the subroutine
    206206return address to the caller of ``_Thread_Dispatch``.
    207 The decision of where to store the task’s context is based
     207The decision of where to store the task's context is based
    208208on numerous factors including the capabilities of
    209209the CPU architecture itself and simplicity as well
    210210as external considerations such as debuggers wishing
    211 to examine a task’s context.  In this case, it is
     211to examine a task's context.  In this case, it is
    212212often simpler to save all data in the context area.
    213213
     
    293293indicates whether or not this CPU model has FP support.  For example, the
    294294definition of the i386ex and i386sx CPU models would set I386_HAS_FPU to
    295 FALSE to indicate that these CPU models are i386’s without an i387 and
     295FALSE to indicate that these CPU models are i386's without an i387 and
    296296wish to leave floating point support out of RTEMS when built for the
    297297i386_nofp processor model.  On a CPU with a built-in FPU like the i486,
     
    400400format is not critical for the implementation of the floating point
    401401context switch routines.  In this case, there is no need to figure out the
    402 exact format – only the size.  Of course, although this is enough
     402exact format - only the size.  Of course, although this is enough
    403403information for RTEMS, it is probably not enough for a debugger such as
    404404gdb.  But that is another problem.
     
    417417The CPU_CONTEXT_FP_SIZE macro is set to the size of the floating point
    418418context area. On some CPUs this will not be a "sizeof" because the format
    419 of the floating point area is not defined – only the size is.  This is
     419of the floating point area is not defined - only the size is.  This is
    420420usually on CPUs with a "floating point save context" instruction.  In
    421421general, though it is easier to define the structure as a "sizeof"
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