Index: c/src/lib/libbsp/powerpc/mpc8260ads/ChangeLog
===================================================================
--- c/src/lib/libbsp/powerpc/mpc8260ads/ChangeLog	(revision 7df02840d5efc62e6471e3e1923fec7275246c77)
+++ c/src/lib/libbsp/powerpc/mpc8260ads/ChangeLog	(revision d36d3a3c0c9d1d28ff30d456fb5ea6fce070c27f)
@@ -1,2 +1,7 @@
+2002-11-01	Andy Dachs <a.dachs@sstl.co.uk>
+
+	* irq/irq.c, irq/irq_asm.S, irq/irq_init.c: Per PR288, add support
+	for _ISR_Nest_level.
+
 2002-10-21	Ralf Corsepius <corsepiu@faw.uni-ulm.de>
 
Index: c/src/lib/libbsp/powerpc/mpc8260ads/irq/irq.c
===================================================================
--- c/src/lib/libbsp/powerpc/mpc8260ads/irq/irq.c	(revision 7df02840d5efc62e6471e3e1923fec7275246c77)
+++ c/src/lib/libbsp/powerpc/mpc8260ads/irq/irq.c	(revision d36d3a3c0c9d1d28ff30d456fb5ea6fce070c27f)
@@ -7,5 +7,7 @@
  *  Modified for mpc8260 Andy Dachs <a.dachs@sstl.co.uk>
  *  Surrey Satellite Technology Limited, 2000
- *  Nested exception handlers not working yet.
++  *  	21/4/2002 Added support for nested interrupts and improved
++  *  	masking operations.  Now we compute priority mask based
++  * 		on table in irq_init.c
  *
  *  The license and distribution terms for this file may be
@@ -16,5 +18,4 @@
  */
   
-#include <rtems/system.h>
 #include <bsp.h>
 #include <bsp/irq.h>
@@ -23,7 +24,6 @@
 #include <libcpu/raw_exception.h>
 #include <bsp/vectors.h>
-/*#include <bsp/8xx_immap.h>*/
+#include <libcpu/cpu.h>
 #include <mpc8260.h>
-/*#include <bsp/commproc.h>*/
 
 /*
@@ -45,7 +45,7 @@
 static inline int is_cpm_irq(const rtems_irq_symbolic_name irqLine)
 {
-  return (((int) irqLine <= BSP_CPM_IRQ_MAX_OFFSET) &
-	  ((int) irqLine >= BSP_CPM_IRQ_LOWEST_OFFSET)
-	 );
+	return (((int) irqLine <= BSP_CPM_IRQ_MAX_OFFSET) &
+			((int) irqLine >= BSP_CPM_IRQ_LOWEST_OFFSET)
+	);
 }
 
@@ -55,34 +55,105 @@
 static inline int is_processor_irq(const rtems_irq_symbolic_name irqLine)
 {
-  return (((int) irqLine <= BSP_PROCESSOR_IRQ_MAX_OFFSET) &
-	  ((int) irqLine >= BSP_PROCESSOR_IRQ_LOWEST_OFFSET)
-	 );
-}
-
-
-/*
- * bit in the SIU mask registers (PPC bit numbering) that should
- * be set to enable the relevant interrupt
- *
- */
-const static unsigned int SIU_MaskBit[BSP_CPM_IRQ_NUMBER] =
-{
-     63, 48, 49, 50,  /* err,   i2c,   spi,   rtt   */
-     51, 52, 53, 54,  /* smc1,  smc2,  idma1, idma2 */
-     55, 56, 57, 63,  /* idma3, idma4, sdma,  -     */
-     59, 60, 61, 62,  /* tmr1,  tmr2,  tmr3,  tmr4  */
-     29, 30, 63, 17,  /* pit,   tmcnt, -,     irq1  */
-     18, 19, 20, 21,  /* irq2,  irq3,  irq4,  irq5  */
-     22, 23, 63, 63,  /* irq6,  irq7,  -,     -     */
-     63, 63, 63, 63,  /* -,     -,     -,     -     */
-     32, 33, 34, 35,  /* fcc1,  fcc2,  fcc3,  -     */
-     36, 37, 38, 39,  /* mcc1,  mcc2,  -,     -     */
-     40, 41, 42, 43,  /* scc1,  scc2,  scc3,  scc4  */
-     44, 45, 46, 47,  /* -,     -,     -,     -     */
-     0,  1,   2,  3,  /* pc0,   pc1,   pc2,   pc3   */
-     4,  5,   6,  7,  /* pc4,   pc5,   pc6,   pc7   */
-     8,  9,  10, 11,  /* pc8,   pc9,   pc10,  pc11  */
-     12, 13, 14, 15   /* pc12,  pc13,  pc14,  pc15  */
+	return (((int) irqLine <= BSP_PROCESSOR_IRQ_MAX_OFFSET) &
+			((int) irqLine >= BSP_PROCESSOR_IRQ_LOWEST_OFFSET)
+	);
+}
+
+typedef struct {
+	rtems_unsigned32 mask_h;	/* mask for sipnr_h and simr_h */
+	rtems_unsigned32 mask_l;	/* mask for sipnr_l and simr_l */
+	rtems_unsigned32 priority_h;  /* mask this and lower priority ints */
+	rtems_unsigned32 priority_l;
+} m82xxIrqMasks_t;
+
+/*
+ *  Mask fields should have a '1' in the bit position for that
+ *  interrupt.
+ *	Priority masks calculated later based on priority table
+ */
+
+static m82xxIrqMasks_t SIU_MaskBit[BSP_CPM_IRQ_NUMBER] =
+{
+	{ 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* err */
+	{ 0x00000000, 0x00008000, 0x00000000, 0x00000000 }, /* i2c */
+	{ 0x00000000, 0x00004000, 0x00000000, 0x00000000 }, /* spi */
+	{ 0x00000000, 0x00002000, 0x00000000, 0x00000000 }, /* rtt */
+	{ 0x00000000, 0x00001000, 0x00000000, 0x00000000 }, /* smc1 */
+	{ 0x00000000, 0x00000800, 0x00000000, 0x00000000 }, /* smc2 */
+	{ 0x00000000, 0x00000400, 0x00000000, 0x00000000 }, /* idma1 */
+	{ 0x00000000, 0x00000200, 0x00000000, 0x00000000 }, /* idma2 */
+	{ 0x00000000, 0x00000100, 0x00000000, 0x00000000 }, /* idma3 */
+	{ 0x00000000, 0x00000080, 0x00000000, 0x00000000 }, /* idma4 */
+	{ 0x00000000, 0x00000040, 0x00000000, 0x00000000 }, /* sdma */
+	{ 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
+	{ 0x00000000, 0x00000010, 0x00000000, 0x00000000 }, /* tmr1 */
+	{ 0x00000000, 0x00000008, 0x00000000, 0x00000000 }, /* tmr2 */
+	{ 0x00000000, 0x00000004, 0x00000000, 0x00000000 }, /* tmr3 */
+	{ 0x00000000, 0x00000002, 0x00000000, 0x00000000 }, /* tmr4 */
+	{ 0x00000004, 0x00000000, 0x00000000, 0x00000000 }, /* tmcnt */
+	{ 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* pit */
+	{ 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
+	{ 0x00004000, 0x00000000, 0x00000000, 0x00000000 }, /* irq1 */
+	{ 0x00002000, 0x00000000, 0x00000000, 0x00000000 }, /* irq2 */
+	{ 0x00001000, 0x00000000, 0x00000000, 0x00000000 }, /* irq3 */
+	{ 0x00000800, 0x00000000, 0x00000000, 0x00000000 }, /* irq4 */
+	{ 0x00000400, 0x00000000, 0x00000000, 0x00000000 }, /* irq5 */
+	{ 0x00000200, 0x00000000, 0x00000000, 0x00000000 }, /* irq6 */
+	{ 0x00000100, 0x00000000, 0x00000000, 0x00000000 }, /* irq7 */
+	{ 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
+	{ 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
+	{ 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
+	{ 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
+	{ 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
+	{ 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
+	{ 0x00000000, 0x80000000, 0x00000000, 0x00000000 }, /* fcc1 */
+	{ 0x00000000, 0x40000000, 0x00000000, 0x00000000 }, /* fcc2 */
+	{ 0x00000000, 0x20000000, 0x00000000, 0x00000000 }, /* fcc3 */
+	{ 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
+	{ 0x00000000, 0x08000000, 0x00000000, 0x00000000 }, /* mcc1 */
+	{ 0x00000000, 0x04000000, 0x00000000, 0x00000000 }, /* mcc2 */
+	{ 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
+	{ 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
+	{ 0x00000000, 0x00800000, 0x00000000, 0x00000000 }, /* scc1 */
+	{ 0x00000000, 0x00400000, 0x00000000, 0x00000000 }, /* scc2 */
+	{ 0x00000000, 0x00200000, 0x00000000, 0x00000000 }, /* scc3 */
+	{ 0x00000000, 0x00100000, 0x00000000, 0x00000000 }, /* scc4 */
+	{ 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
+	{ 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
+	{ 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
+	{ 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
+	{ 0x00010000, 0x00000000, 0x00000000, 0x00000000 }, /* pc15 */
+	{ 0x00020000, 0x00000000, 0x00000000, 0x00000000 }, /* pc14 */
+	{ 0x00040000, 0x00000000, 0x00000000, 0x00000000 }, /* pc13 */
+	{ 0x00080000, 0x00000000, 0x00000000, 0x00000000 }, /* pc12 */
+	{ 0x00100000, 0x00000000, 0x00000000, 0x00000000 }, /* pc11 */
+	{ 0x00200000, 0x00000000, 0x00000000, 0x00000000 }, /* pc10 */
+	{ 0x00400000, 0x00000000, 0x00000000, 0x00000000 }, /* pc9 */
+	{ 0x00800000, 0x00000000, 0x00000000, 0x00000000 }, /* pc8 */
+	{ 0x01000000, 0x00000000, 0x00000000, 0x00000000 }, /* pc7 */
+	{ 0x02000000, 0x00000000, 0x00000000, 0x00000000 }, /* pc6 */
+	{ 0x04000000, 0x00000000, 0x00000000, 0x00000000 }, /* pc5 */
+	{ 0x08000000, 0x00000000, 0x00000000, 0x00000000 }, /* pc4 */
+	{ 0x10000000, 0x00000000, 0x00000000, 0x00000000 }, /* pc3 */
+	{ 0x20000000, 0x00000000, 0x00000000, 0x00000000 }, /* pc2 */
+	{ 0x40000000, 0x00000000, 0x00000000, 0x00000000 }, /* pc1 */
+	{ 0x80000000, 0x00000000, 0x00000000, 0x00000000 }, /* pc0 */
+
 };
+
+
+
+void dump_irq_masks(void )
+{
+	int i;
+	for( i=0; i<BSP_CPM_IRQ_NUMBER;i++ )	
+	{
+		printk( "%04d: %08X %08X\n",
+	 		i,
+	 		SIU_MaskBit[i].priority_h,
+		 	SIU_MaskBit[i].priority_l
+		);
+	}
+}
 
 /*
@@ -97,9 +168,22 @@
 static void compute_SIU_IvectMask_from_prio ()
 {
-  /*
-   * In theory this is feasible. No time to code it yet. See i386/shared/irq.c
-   * for an example based on 8259 controller mask. The actual masks defined
-   * correspond to the priorities defined for the SIU in irq_init.c.
-   */
+	/*
+	 * The actual masks defined
+	 * correspond to the priorities defined
+	 * for the SIU in irq_init.c.
+	 */
+	
+	 int i,j;
+	
+	 for( i=0; i<BSP_CPM_IRQ_NUMBER; i++ )
+	 {
+	 	for( j=0;j<BSP_CPM_IRQ_NUMBER; j++ )
+		 	if( internal_config->irqPrioTbl[j] < internal_config->irqPrioTbl[i] )
+		 	{
+				SIU_MaskBit[i].priority_h |= SIU_MaskBit[j].mask_h;
+				SIU_MaskBit[i].priority_l |= SIU_MaskBit[j].mask_l;
+			}		 		
+	 }
+	
 }
 
@@ -111,58 +195,51 @@
 static int isValidInterrupt(int irq)
 {
-  if ( (irq < BSP_LOWEST_OFFSET) || (irq > BSP_MAX_OFFSET) )
-    return 0;
-  return 1;
+	if ( (irq < BSP_LOWEST_OFFSET) || (irq > BSP_MAX_OFFSET) )
+		return 0;
+	return 1;
 }
 
 int BSP_irq_enable_at_cpm(const rtems_irq_symbolic_name irqLine)
 {
-  int cpm_irq_index;
-
-  if (!is_cpm_irq(irqLine))
-    return 1;
-
-  cpm_irq_index = ((int) (irqLine) - BSP_CPM_IRQ_LOWEST_OFFSET);
-
-
-  if( SIU_MaskBit[cpm_irq_index] < 32 )
-     m8260.simr_h |= (0x80000000 >> SIU_MaskBit[cpm_irq_index]);
-  else
-     m8260.simr_l |= (0x80000000 >> (SIU_MaskBit[cpm_irq_index]-32));
-
-  return 0;
+	int cpm_irq_index;
+
+	if (!is_cpm_irq(irqLine))
+		return 1;
+
+	cpm_irq_index = ((int) (irqLine) - BSP_CPM_IRQ_LOWEST_OFFSET);
+
+	m8260.simr_h |= SIU_MaskBit[cpm_irq_index].mask_h;
+	m8260.simr_l |= SIU_MaskBit[cpm_irq_index].mask_l;
+
+	return 0;
 }
 
 int BSP_irq_disable_at_cpm(const rtems_irq_symbolic_name irqLine)
 {
-  int cpm_irq_index;
-  
-  if (!is_cpm_irq(irqLine))
-    return 1;
-  
-  cpm_irq_index = ((int) (irqLine) - BSP_CPM_IRQ_LOWEST_OFFSET);
-
-  if( SIU_MaskBit[cpm_irq_index] < 32 )
-     m8260.simr_h &= ~(0x80000000 >> SIU_MaskBit[cpm_irq_index]);
-  else
-     m8260.simr_l &= ~(0x80000000 >> (SIU_MaskBit[cpm_irq_index]-32));
-
-
-  return 0;
+	int cpm_irq_index;
+  
+	if (!is_cpm_irq(irqLine))
+		return 1;
+  
+	cpm_irq_index = ((int) (irqLine) - BSP_CPM_IRQ_LOWEST_OFFSET);
+
+	m8260.simr_h &= ~(SIU_MaskBit[cpm_irq_index].mask_h);
+	m8260.simr_l &= ~(SIU_MaskBit[cpm_irq_index].mask_l);
+
+
+	return 0;
 }
 
 int BSP_irq_enabled_at_cpm(const rtems_irq_symbolic_name irqLine)
 {
-  int cpm_irq_index;
-  
-  if (!is_cpm_irq(irqLine))
-    return 0;
-  
-  cpm_irq_index = ((int) (irqLine) - BSP_CPM_IRQ_LOWEST_OFFSET);
-
-  if( SIU_MaskBit[cpm_irq_index] < 32 )
-     return m8260.simr_h & (0x80000000 >> SIU_MaskBit[cpm_irq_index]);
-  else
-     return m8260.simr_l & (0x80000000 >> (SIU_MaskBit[cpm_irq_index]-32));
+	int cpm_irq_index;
+  
+	if (!is_cpm_irq(irqLine))
+		return 0;
+  
+	cpm_irq_index = ((int) (irqLine) - BSP_CPM_IRQ_LOWEST_OFFSET);
+
+	return ((m8260.simr_h & SIU_MaskBit[cpm_irq_index].mask_h) ||
+		    (m8260.simr_l & SIU_MaskBit[cpm_irq_index].mask_l));
 }
 
@@ -174,54 +251,56 @@
 int BSP_install_rtems_irq_handler  (const rtems_irq_connect_data* irq)
 {
-    unsigned int level;
-  
-    if (!isValidInterrupt(irq->name)) {
-      printk( "not a valid intr\n" ) ;
-      return 0;
-    }
-    /*
-     * Check if default handler is actually connected. If not issue an error.
-     * You must first get the current handler via i386_get_current_idt_entry
-     * and then disconnect it using i386_delete_idt_entry.
-     * RATIONALE : to always have the same transition by forcing the user
-     * to get the previous handler before accepting to disconnect.
-     */
-    if (rtems_hdl_tbl[irq->name].hdl != default_rtems_entry.hdl) {
-      printk( "Default handler not there\n" );
-      return 0;
-    }
-
-    _CPU_ISR_Disable(level);
-
-    /*
-     * store the data provided by user
-     */
-    rtems_hdl_tbl[irq->name] = *irq;
-    
-    if (is_cpm_irq(irq->name)) {
-      /*
-       * Enable interrupt at PIC level
-       */
-      BSP_irq_enable_at_cpm (irq->name);
-    }
-    
-
-    if (is_processor_irq(irq->name)) {
-      /*
-       * Should Enable exception at processor level but not needed.  Will restore
-       * EE flags at the end of the routine anyway.
-       */
-    }
-    /*
-     * Enable interrupt on device
-     */
-    irq->on(irq);
-    
-    _CPU_ISR_Enable(level);
-
-/*
-    printk( "Enabled\n" );
-*/
-    return 1;
+	unsigned int level;
+
+	if (!isValidInterrupt(irq->name)) {
+		printk( "not a valid intr\n" ) ;
+		return 0;
+	}
+	/*
+	 * Check if default handler is actually connected. If not issue an error.
+	 * You must first get the current handler via i386_get_current_idt_entry
+	 * and then disconnect it using i386_delete_idt_entry.
+	 * RATIONALE : to always have the same transition by forcing the user
+	 * to get the previous handler before accepting to disconnect.
+	 */
+	if (rtems_hdl_tbl[irq->name].hdl != default_rtems_entry.hdl) {
+		printk( "Default handler not there\n" );
+		return 0;
+	}
+
+	_CPU_ISR_Disable(level);
+
+	/*
+	 * store the data provided by user
+	 */
+	rtems_hdl_tbl[irq->name] = *irq;
+	
+	if (is_cpm_irq(irq->name)) {
+	    /*
+	     * Enable interrupt at PIC level
+	     */
+	    BSP_irq_enable_at_cpm (irq->name);
+	}
+
+#if 0
+	if (is_processor_irq(irq->name)) {
+		/*
+		 * Should Enable exception at processor level but not needed.  Will restore
+		 * EE flags at the end of the routine anyway.
+		 */
+	}
+#endif
+
+	/*
+	 * Enable interrupt on device
+	 */
+	irq->on(irq);
+
+	_CPU_ISR_Enable(level);
+
+	/*
+	    printk( "Enabled\n" );
+	*/
+	return 1;
 }
 
@@ -229,56 +308,56 @@
 int BSP_get_current_rtems_irq_handler	(rtems_irq_connect_data* irq)
 {
-     if (!isValidInterrupt(irq->name)) {
-      return 0;
-     }
-     *irq = rtems_hdl_tbl[irq->name];
-     return 1;
+	if (!isValidInterrupt(irq->name)) {
+		return 0;
+	}
+	*irq = rtems_hdl_tbl[irq->name];
+	return 1;
 }
 
 int BSP_remove_rtems_irq_handler  (const rtems_irq_connect_data* irq)
 {
-    unsigned int level;
-  
-    if (!isValidInterrupt(irq->name)) {
-      return 0;
-    }
-    /*
-     * Check if default handler is actually connected. If not issue an error.
-     * You must first get the current handler via i386_get_current_idt_entry
-     * and then disconnect it using i386_delete_idt_entry.
-     * RATIONALE : to always have the same transition by forcing the user
-     * to get the previous handler before accepting to disconnect.
-     */
-    if (rtems_hdl_tbl[irq->name].hdl != irq->hdl) {
-      return 0;
-    }
-    _CPU_ISR_Disable(level);
-
-    if (is_cpm_irq(irq->name)) {
-      /*
-       * disable interrupt at PIC level
-       */
-      BSP_irq_disable_at_cpm (irq->name);
-    }
-
-    if (is_processor_irq(irq->name)) {
-      /*
-       * disable exception at processor level
-       */
-    }    
-
-    /*
-     * Disable interrupt on device
-     */
-    irq->off(irq);
-
-    /*
-     * restore the default irq value
-     */
-    rtems_hdl_tbl[irq->name] = default_rtems_entry;
-
-    _CPU_ISR_Enable(level);
-
-    return 1;
+	unsigned int level;
+  
+	if (!isValidInterrupt(irq->name)) {
+		return 0;
+	}
+	/*
+	 * Check if default handler is actually connected. If not issue an error.
+	 * You must first get the current handler via i386_get_current_idt_entry
+	 * and then disconnect it using i386_delete_idt_entry.
+	 * RATIONALE : to always have the same transition by forcing the user
+	 * to get the previous handler before accepting to disconnect.
+	 */
+	if (rtems_hdl_tbl[irq->name].hdl != irq->hdl) {
+	  return 0;
+	}
+	_CPU_ISR_Disable(level);
+	
+	if (is_cpm_irq(irq->name)) {
+	  /*
+	   * disable interrupt at PIC level
+	   */
+	  BSP_irq_disable_at_cpm (irq->name);
+	}
+	
+	if (is_processor_irq(irq->name)) {
+	  /*
+	   * disable exception at processor level
+	   */
+	}    
+	
+	/*
+	 * Disable interrupt on device
+	 */
+	irq->off(irq);
+	
+	/*
+	 * restore the default irq value
+	 */
+	rtems_hdl_tbl[irq->name] = default_rtems_entry;
+	
+	_CPU_ISR_Enable(level);
+	
+	return 1;
 }
 
@@ -289,47 +368,49 @@
 int BSP_rtems_irq_mngt_set(rtems_irq_global_settings* config)
 {
-    int i;
-    unsigned int level;
-   /*
-    * Store various code accelerators
-    */
-    internal_config 		= config;
-    default_rtems_entry 	= config->defaultEntry;
-    rtems_hdl_tbl 		= config->irqHdlTbl;
-
-    _CPU_ISR_Disable(level);
-    /*
-     * start with CPM IRQ
-     */
-    for (i=BSP_CPM_IRQ_LOWEST_OFFSET; i < BSP_CPM_IRQ_LOWEST_OFFSET + BSP_CPM_IRQ_NUMBER ; i++) {
-      if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) {
-	BSP_irq_enable_at_cpm (i);
-	rtems_hdl_tbl[i].on(&rtems_hdl_tbl[i]);
-      }
-      else {
-	rtems_hdl_tbl[i].off(&rtems_hdl_tbl[i]);
-	BSP_irq_disable_at_cpm (i);
-      }
-    }
-
-    /*
-     * finish with Processor exceptions handled like IRQ
-     */
-    for (i=BSP_PROCESSOR_IRQ_LOWEST_OFFSET; i < BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER; i++) {
-      if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) {
-	rtems_hdl_tbl[i].on(&rtems_hdl_tbl[i]);
-      }
-      else {
-	rtems_hdl_tbl[i].off(&rtems_hdl_tbl[i]);
-      }
-    }
-    _CPU_ISR_Enable(level);
-    return 1;
+	int i;
+	unsigned int level;
+	/*
+	 * Store various code accelerators
+	 */
+	internal_config			= config;
+	default_rtems_entry		= config->defaultEntry;
+	rtems_hdl_tbl       	= config->irqHdlTbl;
+
+	/* Fill in priority masks */
+	compute_SIU_IvectMask_from_prio();
+	
+	_CPU_ISR_Disable(level);
+	/*
+	 * start with CPM IRQ
+	 */
+	for (i=BSP_CPM_IRQ_LOWEST_OFFSET; i < BSP_CPM_IRQ_LOWEST_OFFSET + BSP_CPM_IRQ_NUMBER ; i++) {
+		if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) {
+			BSP_irq_enable_at_cpm (i);
+			rtems_hdl_tbl[i].on(&rtems_hdl_tbl[i]);
+		} else {
+			rtems_hdl_tbl[i].off(&rtems_hdl_tbl[i]);
+			BSP_irq_disable_at_cpm (i);
+		}
+	}
+
+	/*
+	 * finish with Processor exceptions handled like IRQ
+	 */
+	for (i=BSP_PROCESSOR_IRQ_LOWEST_OFFSET; i < BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER; i++) {
+		if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) {
+			rtems_hdl_tbl[i].on(&rtems_hdl_tbl[i]);
+		} else {
+			rtems_hdl_tbl[i].off(&rtems_hdl_tbl[i]);
+		}
+	}
+
+	_CPU_ISR_Enable(level);
+	return 1;
 }
 
 int BSP_rtems_irq_mngt_get(rtems_irq_global_settings** config)
 {
-    *config = internal_config;
-    return 0;
+	*config = internal_config;
+	return 0;
 }
 
@@ -338,4 +419,5 @@
 #endif
 
+
 /*
  * High level IRQ handler called from shared_raw_irq_code_entry
@@ -343,91 +425,85 @@
 void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum)
 {
-  register unsigned int irq;
+	register unsigned int irq;
 #if 0
-  register unsigned oldMask;		      /* old siu pic masks */
+	register unsigned oldMask;		      /* old siu pic masks */
 #endif
-  register unsigned msr;
-  register unsigned new_msr;
+	register unsigned msr;
+	register unsigned new_msr;
+	register unsigned old_simr_h;
+	register unsigned old_simr_l;
 #ifdef DISPATCH_HANDLER_STAT
-  unsigned loopCounter;
+	unsigned loopCounter;
 #endif
 
 
 
-  /*
-   * Handle decrementer interrupt
-   */
-  if (excNum == ASM_DEC_VECTOR) {
-
-/*
-    _BSP_GPLED1_on();
-*/
-    _CPU_MSR_GET(msr);
-    new_msr = msr | MSR_EE;
-    _CPU_MSR_SET(new_msr);
-
-    rtems_hdl_tbl[BSP_DECREMENTER].hdl();
-
-    _CPU_MSR_SET(msr);
-
-/*
-    _BSP_GPLED1_off();
-*/
-    return;
-  }
-
-  /*
-   * Handle external interrupt generated by SIU on PPC core
-   */
+	/*
+	 * Handle decrementer interrupt
+	 */
+	if (excNum == ASM_DEC_VECTOR) {
+		_CPU_MSR_GET(msr);
+		new_msr = msr | MSR_EE;
+		_CPU_MSR_SET(new_msr);
+
+		rtems_hdl_tbl[BSP_DECREMENTER].hdl();
+
+		_CPU_MSR_SET(msr);
+
+		return;
+	}
+
+	/*
+	 * Handle external interrupt generated by SIU on PPC core
+	 */
 #ifdef DISPATCH_HANDLER_STAT
-  loopCounter = 0;
+	loopCounter = 0;
 #endif  
-  while (1) {
-
-    if( ((m8260.sipnr_h & m8260.simr_h) | (m8260.sipnr_l & m8260.simr_l)) == 0 ) {
+
+	while (1) {
+
+		if( ((m8260.sipnr_h & m8260.simr_h) | (m8260.sipnr_l & m8260.simr_l)) == 0 ) {
 #ifdef DISPATCH_HANDLER_STAT
-      if (loopCounter >  maxLoop) maxLoop = loopCounter;
+			if (loopCounter >  maxLoop) maxLoop = loopCounter;
 #endif      
-      break;
-    }
-
-    irq = (m8260.sivec >> 26) + BSP_CPM_IRQ_LOWEST_OFFSET;
-
-/*
-    printk( "dispatching %d\n", irq );
-*/
-
-    /* Clear pending register */
-    if( irq <= BSP_CPM_IRQ_MAX_OFFSET ) {
-      if( SIU_MaskBit[irq] < 32 )
-        m8260.sipnr_h = (0x80000000 >> SIU_MaskBit[irq]);
-      else
-        m8260.sipnr_l = (0x80000000 >> (SIU_MaskBit[irq]-32));
-    }
-
-/*
-    _CPU_MSR_GET(msr);
-    new_msr = msr | MSR_EE;
-    _CPU_MSR_SET(new_msr);
-*/
-    rtems_hdl_tbl[irq].hdl();
-/*
-    _CPU_MSR_SET(msr);
-*/
-
-
-
-#if 0
-    ppc_cached_irq_mask |= (oldMask & ~(SIU_IvectMask[irq]));
-    ((volatile immap_t *)IMAP_ADDR)->im_siu_conf.sc_simask = ppc_cached_irq_mask;
+			break;
+		}
+
+		irq = (m8260.sivec >> 26) + BSP_CPM_IRQ_LOWEST_OFFSET;
+
+		/* Clear mask and pending register */
+		if( irq <= BSP_CPM_IRQ_MAX_OFFSET ) {
+			/* save interrupt masks */
+			old_simr_h = m8260.simr_h;
+			old_simr_l = m8260.simr_l;
+
+			/* mask off current interrupt and lower priority ones */
+			m8260.simr_h &= SIU_MaskBit[irq].priority_h;
+			m8260.simr_l &= SIU_MaskBit[irq].priority_l;
+
+			/* clear pending bit */
+			m8260.sipnr_h |= SIU_MaskBit[irq].mask_h;
+			m8260.sipnr_l |= SIU_MaskBit[irq].mask_l;
+
+			/* re-enable external exceptions */
+			_CPU_MSR_GET(msr);
+			new_msr = msr | MSR_EE;
+			_CPU_MSR_SET(new_msr);
+
+			/* call handler */
+			rtems_hdl_tbl[irq].hdl();
+
+			/* disable exceptions again */
+			_CPU_MSR_SET(msr);
+			
+			/* restore interrupt masks */
+			m8260.simr_h = old_simr_h;
+			m8260.simr_l = old_simr_l;
+			
+		}
+#ifdef DISPATCH_HANDLER_STAT
+		++ loopCounter;
 #endif
-#ifdef DISPATCH_HANDLER_STAT
-    ++ loopCounter;
-#endif    
-  }
-
-
-
-
+	}
 }
 
@@ -436,18 +512,19 @@
 void _ThreadProcessSignalsFromIrq (BSP_Exception_frame* ctx)
 {
-  /*
-   * Process pending signals that have not already been
-   * processed by _Thread_Displatch. This happens quite
-   * unfrequently : the ISR must have posted an action
-   * to the current running thread.
-   */
-  if ( _Thread_Do_post_task_switch_extension ||
-       _Thread_Executing->do_post_task_switch_extension ) {
-    _Thread_Executing->do_post_task_switch_extension = FALSE;
-    _API_extensions_Run_postswitch();
-  }
-  /*
-   * I plan to process other thread related events here.
-   * This will include DEBUG session requested from keyboard...
-   */
-}
+	/*
+	 * Process pending signals that have not already been
+	 * processed by _Thread_Displatch. This happens quite
+	 * unfrequently : the ISR must have posted an action
+	 * to the current running thread.
+	 */
+	if ( _Thread_Do_post_task_switch_extension ||
+		_Thread_Executing->do_post_task_switch_extension ) {
+		_Thread_Executing->do_post_task_switch_extension = FALSE;
+		_API_extensions_Run_postswitch();
+	}
+
+	/*
+	 * I plan to process other thread related events here.
+	 * This will include DEBUG session requested from keyboard...
+	 */
+}
Index: c/src/lib/libbsp/powerpc/mpc8260ads/irq/irq_asm.S
===================================================================
--- c/src/lib/libbsp/powerpc/mpc8260ads/irq/irq_asm.S	(revision 7df02840d5efc62e6471e3e1923fec7275246c77)
+++ c/src/lib/libbsp/powerpc/mpc8260ads/irq/irq_asm.S	(revision d36d3a3c0c9d1d28ff30d456fb5ea6fce070c27f)
@@ -10,13 +10,16 @@
  *  Modifications Copyright (C) 1999 Eric Valette. valette@crf.canon.fr
  *
+ *  Modifications to store nesting level in global _ISR_Nest_level
+ *  variable instead of SPRG0.  Andy Dachs <a.dachs@sstl.co.uk>
  *
  * $Id$
  */
   	
-#include <asm.h>
+#include <bsp/vectors.h>
+#include <rtems/score/cpuopts.h>  /* for PPC_HAS_FPU */
 #include <rtems/score/cpu.h>
-#include <bsp/vectors.h>
+#include <libcpu/cpu.h>
 #include <libcpu/raw_exception.h>
-	
+#include "asm.h"
 
 #define SYNC \
@@ -27,4 +30,5 @@
 	.p2align 5	
 		
+	
 	PUBLIC_VAR(decrementer_exception_vector_prolog_code)
 	
@@ -84,5 +88,4 @@
 	stw	r0, SRR0_FRAME_OFFSET(r1)
 	stw	r2, SRR1_FRAME_OFFSET(r1)
-	
 
 	/*
@@ -107,13 +110,13 @@
 	 * switch to the right stack later.
 	 */
-	stw	r5, GPR5_OFFSET(r1)
-	stw	r6, GPR6_OFFSET(r1)
-	stw	r7, GPR7_OFFSET(r1)
-	stw	r8, GPR8_OFFSET(r1)
-	stw	r9, GPR9_OFFSET(r1)
-	stw	r10, GPR10_OFFSET(r1)
-	stw	r11, GPR11_OFFSET(r1)
-	stw	r12, GPR12_OFFSET(r1)
-	stw	r13, GPR13_OFFSET(r1)
+	stw		r5, GPR5_OFFSET(r1)
+	stw		r6, GPR6_OFFSET(r1)
+	stw		r7, GPR7_OFFSET(r1)
+	stw		r8, GPR8_OFFSET(r1)
+	stw		r9, GPR9_OFFSET(r1)
+	stw		r10, GPR10_OFFSET(r1)
+	stw		r11, GPR11_OFFSET(r1)
+	stw		r12, GPR12_OFFSET(r1)
+	stw		r13, GPR13_OFFSET(r1)
 
 	mfcr	r5
@@ -122,8 +125,8 @@
 	mflr	r8
 	
-	stw	r5,  EXC_CR_OFFSET(r1)
-	stw	r6,  EXC_CTR_OFFSET(r1)
-	stw	r7,  EXC_XER_OFFSET(r1)
-	stw	r8,  EXC_LR_OFFSET(r1)
+	stw		r5,  EXC_CR_OFFSET(r1)
+	stw		r6,  EXC_CTR_OFFSET(r1)
+	stw		r7,  EXC_XER_OFFSET(r1)
+	stw		r8,  EXC_LR_OFFSET(r1)
 
 	/*
@@ -131,6 +134,6 @@
 	 * that will be used when returning from C handler
 	 */
-	stw	r14, GPR14_OFFSET(r1)
-	stw	r15, GPR15_OFFSET(r1)
+	stw		r14, GPR14_OFFSET(r1)
+	stw		r15, GPR15_OFFSET(r1)
 	/*
 	 * save current stack pointer location in R14
@@ -140,14 +143,17 @@
 	 * store part of _Thread_Dispatch_disable_level address in R15
 	 */
-	addis r15,0, _Thread_Dispatch_disable_level@ha
+	addis	r15,0, _Thread_Dispatch_disable_level@ha
 	/*
 	 * Get current nesting level in R2
 	 */
-	mfspr	r2, SPRG0
+/*	mfspr	r2, SPRG0 */
+	addis	r6, 0, _ISR_Nest_level@ha
+	lwz		r2, _ISR_Nest_level@l( r6 )
+	
 	/*
 	 * Check if stack switch is necessary
 	 */
 	cmpwi	r2,0
-	bne	nested
+	bne		nested
 	mfspr	r1, SPRG1
 	
@@ -157,12 +163,16 @@
 	 */
 	addi	r2,r2,1
+	
+	addis	r6, 0, _ISR_Nest_level@ha
+	stw		r2, _ISR_Nest_level@l( r6 )
+	
 	/*
 	 * Start Incrementing _Thread_Dispatch_disable_level R4 = _Thread_Dispatch_disable_level
 	 */
-	lwz	r6,_Thread_Dispatch_disable_level@l(r15)
+	lwz		r6,_Thread_Dispatch_disable_level@l(r15)
 	/*
 	 * store new nesting level in SPRG0
 	 */
-	mtspr	SPRG0, r2
+/*	mtspr	SPRG0, r2 */
 	
 	addi	r6, r6, 1
@@ -171,5 +181,5 @@
 	 * store new _Thread_Dispatch_disable_level value
 	 */
-	stw	r6, _Thread_Dispatch_disable_level@l(r15)
+	stw		r6, _Thread_Dispatch_disable_level@l(r15)
 	/*
 	 * We are now running on the interrupt stack. External and decrementer
@@ -181,6 +191,8 @@
 	 * in case...
 	 */
+	
 	addi	r3, r14, 0x8
-	bl	C_dispatch_irq_handler /* C_dispatch_irq_handler(cpu_interrupt_frame* r3, vector r4) */
+	bl		C_dispatch_irq_handler /* C_dispatch_irq_handler(cpu_interrupt_frame* r3, vector r4) */
+
 	/*
 	 * start decrementing nesting level. Note : do not test result against 0 
@@ -188,13 +200,20 @@
 	 * then _Thread_Dispatch_disable_level > 1
 	 */
-	mfspr	r2, SPRG0
+/*	mfspr	r2, SPRG0 */
+	
+	addis	r6, 0, _ISR_Nest_level@ha
+	lwz		r2, _ISR_Nest_level@l( r6 )
+	
 	/*
 	 * start decrementing _Thread_Dispatch_disable_level
 	 */
-	lwz	r3,_Thread_Dispatch_disable_level@l(r15)
+	lwz		r3,_Thread_Dispatch_disable_level@l(r15)
 	addi	r2, r2, -1	/* Continue decrementing nesting level */
 	addi	r3, r3, -1	/* Continue decrementing _Thread_Dispatch_disable_level */
-	mtspr	SPRG0, r2	/* End decrementing nesting level */
-	stw	r3,_Thread_Dispatch_disable_level@l(r15) /* End decrementing _Thread_Dispatch_disable_level */
+	
+	stw		r2, _ISR_Nest_level@l( r6 )	
+/*	mtspr	SPRG0, r2 */ 	/* End decrementing nesting level */
+	
+	stw		r3,_Thread_Dispatch_disable_level@l(r15) /* End decrementing _Thread_Dispatch_disable_level */
 	cmpwi	r3, 0
 	/*
@@ -203,5 +222,5 @@
 	 */
 	addi	r1, r14, 0
-	bne	easy_exit /* if (_Thread_Dispatch_disable_level != 0) goto easy_exit */
+	bne		easy_exit /* if (_Thread_Dispatch_disable_level != 0) goto easy_exit */
 	/*
 	 * Here we are running again on the thread system stack.
@@ -211,14 +230,14 @@
 	 */
 	addis	r4, 0, _Context_Switch_necessary@ha
-	lwz	r5, _Context_Switch_necessary@l(r4)
+	lwz		r5, _Context_Switch_necessary@l(r4)
 	cmpwi	r5, 0
-	bne	switch
+	bne		switch
 	
 	addis	r6, 0, _ISR_Signals_to_thread_executing@ha
-	lwz	r7, _ISR_Signals_to_thread_executing@l(r6)
+	lwz		r7, _ISR_Signals_to_thread_executing@l(r6)
 	cmpwi	r7, 0
-	li	r8, 0
-	beq	easy_exit
-	stw	r8, _ISR_Signals_to_thread_executing@l(r6)
+	li		r8, 0
+	beq		easy_exit
+	stw		r8, _ISR_Signals_to_thread_executing@l(r6)
 	/*
 	 * going to call _ThreadProcessSignalsFromIrq
@@ -227,16 +246,17 @@
 	stmw	r16, GPR16_OFFSET(r1)
 	addi	r3, r1, 0x8
-        /*
-         * compute SP at exception entry
-         */
-        addi    r2, r1, EXCEPTION_FRAME_END
-        /*
-         * store it at the right place
-         */
-        stw     r2, GPR1_OFFSET(r1)
+	
+    /*
+     * compute SP at exception entry
+     */
+    addi    r2, r1, EXCEPTION_FRAME_END
+    /*
+     * store it at the right place
+     */
+    stw     r2, GPR1_OFFSET(r1)
 	/*
 	 * Call High Level signal handling code
 	 */
-	bl	_ThreadProcessSignalsFromIrq
+	bl		_ThreadProcessSignalsFromIrq
 	
 
@@ -244,8 +264,8 @@
 	 * start restoring exception like frame
 	 */
-	lwz	r31,  EXC_CTR_OFFSET(r1)
-	lwz	r30,  EXC_XER_OFFSET(r1)
-	lwz	r29,  EXC_CR_OFFSET(r1)
-	lwz	r28,  EXC_LR_OFFSET(r1)
+	lwz		r31,  EXC_CTR_OFFSET(r1)
+	lwz		r30,  EXC_XER_OFFSET(r1)
+	lwz		r29,  EXC_CR_OFFSET(r1)
+	lwz		r28,  EXC_LR_OFFSET(r1)
 	
 	mtctr	r31
@@ -255,9 +275,9 @@
 	
 	
-	lmw	r4, GPR4_OFFSET(r1)
-
-	
-	lwz	r2, GPR2_OFFSET(r1)
-	lwz	r0, GPR0_OFFSET(r1)
+	lmw		r4, GPR4_OFFSET(r1)
+
+	
+	lwz		r2, GPR2_OFFSET(r1)
+	lwz		r0, GPR0_OFFSET(r1)
 
 	/*
@@ -272,10 +292,10 @@
 	 */
 		
-	lwz	r3, SRR1_FRAME_OFFSET(r1)
+	lwz		r3, SRR1_FRAME_OFFSET(r1)
 	mtsrr1	r3
-	lwz	r3, SRR0_FRAME_OFFSET(r1)
+	lwz		r3, SRR0_FRAME_OFFSET(r1)
 	mtsrr0	r3
 	
-	lwz	r3, GPR3_OFFSET(r1)
+	lwz		r3, GPR3_OFFSET(r1)
 	addi 	r1,r1, EXCEPTION_FRAME_END
 	SYNC
@@ -283,5 +303,5 @@
 	
 switch:
-	bl	SYM (_Thread_Dispatch)
+	bl		SYM (_Thread_Dispatch)
 	
 easy_exit:	
@@ -289,8 +309,8 @@
 	 * start restoring interrupt frame
 	 */
-	lwz	r3,  EXC_CTR_OFFSET(r1)
-	lwz	r4,  EXC_XER_OFFSET(r1)
-	lwz	r5,  EXC_CR_OFFSET(r1)
-	lwz	r6,  EXC_LR_OFFSET(r1)
+	lwz		r3,  EXC_CTR_OFFSET(r1)
+	lwz		r4,  EXC_XER_OFFSET(r1)
+	lwz		r5,  EXC_CR_OFFSET(r1)
+	lwz		r6,  EXC_LR_OFFSET(r1)
 	
 	mtctr	r3
@@ -299,15 +319,15 @@
 	mtlr	r6
 
-	lwz	r15, GPR15_OFFSET(r1)
-	lwz	r14, GPR14_OFFSET(r1)
-	lwz	r13, GPR13_OFFSET(r1)
-	lwz	r12, GPR12_OFFSET(r1)
-	lwz	r11, GPR11_OFFSET(r1)
-	lwz	r10, GPR10_OFFSET(r1)
-	lwz	r9, GPR9_OFFSET(r1)
-	lwz	r8, GPR8_OFFSET(r1)
-	lwz	r7, GPR7_OFFSET(r1)
-	lwz	r6, GPR6_OFFSET(r1)
-	lwz	r5, GPR5_OFFSET(r1)
+	lwz		r15, GPR15_OFFSET(r1)
+	lwz		r14, GPR14_OFFSET(r1)
+	lwz		r13, GPR13_OFFSET(r1)
+	lwz		r12, GPR12_OFFSET(r1)
+	lwz		r11, GPR11_OFFSET(r1)
+	lwz		r10, GPR10_OFFSET(r1)
+	lwz		r9, GPR9_OFFSET(r1)
+	lwz		r8, GPR8_OFFSET(r1)
+	lwz		r7, GPR7_OFFSET(r1)
+	lwz		r6, GPR6_OFFSET(r1)
+	lwz		r5, GPR5_OFFSET(r1)
 
 	/*
@@ -324,13 +344,13 @@
 	 */
 		 
-	lwz	r4, SRR1_FRAME_OFFSET(r1)
-	lwz	r2, SRR0_FRAME_OFFSET(r1)
-	lwz	r3, GPR3_OFFSET(r1)
-	lwz	r0, GPR0_OFFSET(r1)
+	lwz		r4, SRR1_FRAME_OFFSET(r1)
+	lwz		r2, SRR0_FRAME_OFFSET(r1)
+	lwz		r3, GPR3_OFFSET(r1)
+	lwz		r0, GPR0_OFFSET(r1)
 
 	mtsrr1	r4
 	mtsrr0	r2
-	lwz	r4, GPR4_OFFSET(r1)
-	lwz	r2, GPR2_OFFSET(r1)
+	lwz		r4, GPR4_OFFSET(r1)
+	lwz		r2, GPR2_OFFSET(r1)
 	addi 	r1,r1, EXCEPTION_FRAME_END
 	SYNC
Index: c/src/lib/libbsp/powerpc/mpc8260ads/irq/irq_init.c
===================================================================
--- c/src/lib/libbsp/powerpc/mpc8260ads/irq/irq_init.c	(revision 7df02840d5efc62e6471e3e1923fec7275246c77)
+++ c/src/lib/libbsp/powerpc/mpc8260ads/irq/irq_init.c	(revision d36d3a3c0c9d1d28ff30d456fb5ea6fce070c27f)
@@ -47,10 +47,18 @@
 
 static rtems_irq_connect_data     	rtemsIrq[BSP_IRQ_NUMBER];
-static rtems_irq_global_settings     	initial_config;
+static rtems_irq_global_settings   	initial_config;
 static rtems_irq_connect_data     	defaultIrq = {
-  /* vectorIdex,	 hdl		, on		, off		, isOn */
-  0, 			 nop_func	, nop_func	, nop_func	, not_connected
+  /* vectorIdex,	hdl			, on		, off		, isOn */
+  0, 			 	nop_func	, nop_func	, nop_func	, not_connected
 };
-static rtems_irq_prio irqPrioTable[BSP_IRQ_NUMBER]={
+
+/*
+	List the interrupts is their order of priority (highest first).
+	This does not have to be the same order as the siprr settings but
+	without knowing more about the application they are kept the same.
+*/
+
+
+static rtems_irq_prio irqPrioTable[BSP_CPM_IRQ_NUMBER]={
   /*
    * actual priorities for interrupt :
@@ -61,10 +69,7 @@
   0,  45, 63, 44, 66, 68, 35, 39, 50, 62, 34,  0,  30, 40, 52, 58,
   2,  3,  0,  5,  15, 16, 17, 18, 49, 51,  0,  0,  0,  0,  0,  0,
-  6,  7,  8,  0,  11, 12, 0,  0,  20, 21, 22, 23,  0,  0,  0,  0,
-  29, 31, 33, 37, 38, 41, 47, 48, 55, 56, 57, 60, 64, 65, 69, 70,
-  /*
-   * Processor exceptions handled as interrupts
-   */
-  0
+  6,  7,  8,  0,  11, 12, 0,  0,  20, 21, 22,  23, 0,  0,  0,  0,
+  29, 31, 33, 37, 38, 41, 47, 48, 55, 56, 57,  60, 64, 65, 69, 70,
+
 };
 
@@ -110,8 +115,8 @@
      * Init initial Interrupt management config
      */
-    initial_config.irqNb 	= BSP_IRQ_NUMBER;
+    initial_config.irqNb 		= BSP_IRQ_NUMBER;
     initial_config.defaultEntry = defaultIrq;
     initial_config.irqHdlTbl	= rtemsIrq;
-    initial_config.irqBase	= BSP_ASM_IRQ_VECTOR_BASE;
+    initial_config.irqBase		= BSP_ASM_IRQ_VECTOR_BASE;
     initial_config.irqPrioTbl	= irqPrioTable;
 
@@ -131,7 +136,7 @@
     vectorDesc.hdl.raw_hdl	=	decrementer_exception_vector_prolog_code;
     vectorDesc.hdl.raw_hdl_size	=	(unsigned) &decrementer_exception_vector_prolog_code_size;
-    vectorDesc.on		=	nop_func;
-    vectorDesc.off		=	nop_func;
-    vectorDesc.isOn		=	connected;
+    vectorDesc.on			=	nop_func;
+    vectorDesc.off			=	nop_func;
+    vectorDesc.isOn			=	connected;
     if (!mpc8xx_set_exception (&vectorDesc)) {
       BSP_panic("Unable to initialize RTEMS decrementer raw exception\n");
