Ignore:
Timestamp:
04/22/96 16:30:02 (28 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, 5, master
Children:
f581163a
Parents:
767a6c6
Message:

updartes from Tony Bennett

File:
1 edited

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  • c/src/exec/score/cpu/hppa1.1/cpu_asm.s

    r767a6c6 rd0b7c4e6  
    1 #       @(#)cpu_asm.S   1.7 - 95/09/21
    2 #       
    31#
    42# TODO:
    … …  
    3129#include <rtems/score/cpu_asm.h>
    3230#include <rtems/score/cpu.h>
    33 
    3431#include <rtems/score/offsets.h>
    3532
    … …  
    6562
    6663#  PAGE^L
    67 #  void __Generic_ISR_Handler()
     64#  void _Generic_ISR_Handler()
    6865#
    6966#  This routine provides the RTEMS interrupt management.
    7067#
    71 #  NOTE:
    72 #    Upon entry, the stack will contain a stack frame back to the
    73 #    interrupted task.  If dispatching is enabled, this is the
    74 #    outer most interrupt, (and a context switch is necessary or
    75 #    the current task has signals), then set up the stack to
    76 #    transfer control to the interrupt dispatcher.
    77 #
    78 #
    7968#   We jump here from the interrupt vector.
    80 #   The hardware has done some stuff for us:
     69#   The HPPA hardware has done some stuff for us:
    8170#       PSW saved in IPSW
    8271#       PSW set to 0
    … …  
    9079#                 SHR 0 1 2  3  4  5  6
    9180#
    92 #   Our vector stub did the following
    93 #       placed vector number is in r1
    94 #
    95 #        stub
    96 #            r1 <- vector number
    97 #            save ipsw under rock
    98 #            ipsw = ipsw & ~1    --  disable ints
    99 #            save qregs under rock
    100 #            qra = _Generic_ISR_handler
    101 #            rfi
    102 #
    103 ################################################
    104 
    105 #  Distinct Interrupt Entry Points
    106 #
    107 #  The following macro and the 32 instantiations of the macro
    108 #  are necessary to determine which interrupt vector occurred.
    109 #
    110 #  r9 is loaded with the vector number and then we jump to
    111 #    the first level interrupt handler.  In most cases this
    112 #    is _Generic_ISR_Handler.  In a few cases (such as TLB misc)
    113 #    it may be to some other entry point.
    114 #
    115 
    116 # table for first level interrupt handlers
    117         .import   HPPA_first_level_interrupt_handler, data
    118 
    119 #define THANDLER(vector) \
    120         mtctl   %r9,  isr_r9 ! \
    121         mtctl   %r8,  isr_r8 ! \
    122         ldi     vector, %r9  ! \
    123         ldil    L%HPPA_first_level_interrupt_handler,%r8 ! \
    124         ldo     R%HPPA_first_level_interrupt_handler(%r8),%r8 ! \
    125         ldwx,s  %r9(%r8),%r8 ! \
    126         bv      0(%r8) ! \
    127         mfctl   isr_r8, %r8
    128 
    129         .align 4096
    130         .EXPORT IVA_Table,ENTRY,PRIV_LEV=0
    131 IVA_Table:
    132         .PROC
    133         .CALLINFO FRAME=0,NO_CALLS
    134         .ENTRY
    135 
    136         THANDLER(0)             /* unused */
    137 
    138         THANDLER(HPPA_INTERRUPT_HIGH_PRIORITY_MACHINE_CHECK)
    139 
    140         THANDLER(HPPA_INTERRUPT_POWER_FAIL)
    141 
    142         THANDLER(HPPA_INTERRUPT_RECOVERY_COUNTER)
    143 
    144         THANDLER(HPPA_INTERRUPT_EXTERNAL_INTERRUPT)
    145 
    146         THANDLER(HPPA_INTERRUPT_LOW_PRIORITY_MACHINE_CHECK)
    147 
    148         THANDLER(HPPA_INTERRUPT_INSTRUCTION_TLB_MISS)
    149 
    150         THANDLER(HPPA_INTERRUPT_INSTRUCTION_MEMORY_PROTECTION)
    151 
    152         THANDLER(HPPA_INTERRUPT_ILLEGAL_INSTRUCTION)
    153 
    154         THANDLER(HPPA_INTERRUPT_BREAK_INSTRUCTION)
    155 
    156         THANDLER(HPPA_INTERRUPT_PRIVILEGED_OPERATION)
    157 
    158         THANDLER(HPPA_INTERRUPT_PRIVILEGED_REGISTER)
    159 
    160         THANDLER(HPPA_INTERRUPT_OVERFLOW)
    161 
    162         THANDLER(HPPA_INTERRUPT_CONDITIONAL)
    163 
    164         THANDLER(HPPA_INTERRUPT_ASSIST_EXCEPTION)
    165 
    166         THANDLER(HPPA_INTERRUPT_DATA_TLB_MISS)
    167 
    168         THANDLER(HPPA_INTERRUPT_NON_ACCESS_INSTRUCTION_TLB_MISS)
    169 
    170         THANDLER(HPPA_INTERRUPT_NON_ACCESS_DATA_TLB_MISS)
    171 
    172         THANDLER(HPPA_INTERRUPT_DATA_MEMORY_PROTECTION)
    173 
    174         THANDLER(HPPA_INTERRUPT_DATA_MEMORY_BREAK)
    175 
    176         THANDLER(HPPA_INTERRUPT_TLB_DIRTY_BIT)
    177 
    178         THANDLER(HPPA_INTERRUPT_PAGE_REFERENCE)
    179 
    180         THANDLER(HPPA_INTERRUPT_ASSIST_EMULATION)
    181 
    182         THANDLER(HPPA_INTERRUPT_HIGHER_PRIVILEGE_TRANSFER)
    183 
    184         THANDLER(HPPA_INTERRUPT_LOWER_PRIVILEGE_TRANSFER)
    185 
    186         THANDLER(HPPA_INTERRUPT_TAKEN_BRANCH)
    187 
    188         THANDLER(HPPA_INTERRUPT_DATA_MEMORY_ACCESS_RIGHTS)
    189 
    190         THANDLER(HPPA_INTERRUPT_DATA_MEMORY_PROTECTION_ID)
    191 
    192         THANDLER(HPPA_INTERRUPT_UNALIGNED_DATA_REFERENCE)
    193 
    194         THANDLER(HPPA_INTERRUPT_PERFORMANCE_MONITOR)
    195 
    196         THANDLER(HPPA_INTERRUPT_INSTRUCTION_DEBUG)
    197 
    198         THANDLER(HPPA_INTERRUPT_DATA_DEBUG)
    199 
    200         .EXIT
    201         .PROCEND
    202 
     81#   Our vector stub (in the BSP) MUST have done the following: 
     82#
     83#   a) Saved the original %r9 into %isr_r9 (%cr25)
     84#   b) Placed the vector number in %r9
     85#   c) Was allowed to also destroy $isr_r8 (%cr26),
     86#      but the stub was NOT allowed to destroy any other registers.
     87#
     88#   The typical stub sequence (in the BSP) should look like this:
     89#
     90#   a)     mtctl   %r9,isr_r9     ; (save r9 in cr25)
     91#   b)     ldi     vector,%r9     ; (load constant vector number in r9)
     92#   c)     mtctl   %r8,isr_r8     ; (save r8 in cr26)
     93#   d)     ldil    L%MY_BSP_first_level_interrupt_handler,%r8
     94#   e)     ldo     R%MY_BSP_first_level_interrupt_handler(%r8),%r8
     95#                                 ; (point to BSP raw handler table)
     96#   f)     ldwx,s  %r9(%r8),%r8   ; (load value from raw handler table)
     97#   g)     bv      0(%r8)         ; (call raw handler: _Generic_ISR_Handler)
     98#   h)     mfctl   isr_r8,%r8     ; (restore r8 from cr26 in delay slot)
     99#
     100#   Optionally, steps (c) thru (h) _could_ be replaced with a single
     101#          bl,n    _Generic_ISR_Handler,%r0
     102#
     103#
     104#
    203105        .EXPORT _Generic_ISR_Handler,ENTRY,PRIV_LEV=0
    204106_Generic_ISR_Handler:
    … …  
    236138#  reg    current value        saved value
    237139# ------------------------------------------------
    238 #  arg0   scratch               isr_arg0  (ctl)
    239 #  r9     vector number         isr_r9    (ctl)
     140#  arg0   scratch               isr_arg0  (cr24)
     141#  r9     vector number         isr_r9    (cr25)
    240142#
    241143# Point to beginning of integer context and
    … …  
    278180#  reg    current value        saved value
    279181# ------------------------------------------------
    280 #  arg0   scratch               isr_arg0  (ctl)
    281 #  r9     vector number         isr_r9    (ctl)
     182#  arg0   scratch               isr_arg0  (cr24)
     183#  r9     vector number         isr_r9    (cr25)
    282184#
    283185# Fix them
    … …  
    378280
    379281# load address of user handler
     282# Note:  No error checking is done, it is assumed that the
     283#        vector table contains a valid address or a stub
     284#        spurious handler.
    380285        .import   _ISR_Vector_table,data
    381286        ldil      L%_ISR_Vector_table,%r8
    … …  
    389294#    and we are using a hard coded address from a table
    390295#  So... we fudge r2 ourselves (ala dynacall)
    391 #
     296#  arg0 = vector number, arg1 = ptr to rtems_interrupt_frame
    392297        copy      %r9, %r26
    393298        .call  ARGW0=GR, ARGW1=GR
    … …  
    405310        ldw        -4(sp), sp
    406311
    407 #    r3  -- &_ISR_Nest_level
     312#    r3  -- (most of) &_ISR_Nest_level
    408313#    r5  -- value _ISR_Nest_level
    409 #    r4  -- &_Thread_Dispatch_disable_level
     314#    r4  -- (most of) &_Thread_Dispatch_disable_level
    410315#    r6  -- value _Thread_Dispatch_disable_level
     316#    r7  -- (most of) &_ISR_Signals_to_thread_executing
     317#    r8  -- value _ISR_Signals_to_thread_executing
    411318
    412319        .import   _ISR_Nest_level,data
    413320        ldil      L%_ISR_Nest_level,%r3
    414         ldo       R%_ISR_Nest_level(%r3),%r3
    415         ldw       0(%r3),%r5
     321        ldw       R%_ISR_Nest_level(%r3),%r5
    416322
    417323        .import   _Thread_Dispatch_disable_level,data
    418324        ldil      L%_Thread_Dispatch_disable_level,%r4
    419         ldo       R%_Thread_Dispatch_disable_level(%r4),%r4
    420         ldw       0(%r4), %r6
     325        ldw       R%_Thread_Dispatch_disable_level(%r4),%r6
     326
     327        .import    _ISR_Signals_to_thread_executing,data
     328        ldil       L%_ISR_Signals_to_thread_executing,%r7
    421329
    422330# decrement isr nest level
    423331        addi      -1, %r5, %r5
    424         stw       %r5, 0(%r3)
     332        stw       %r5, R%_ISR_Nest_level(%r3)
    425333
    426334# decrement dispatch disable level counter and, if not 0, go on
    427335        addi       -1,%r6,%r6
    428336        comibf,=   0,%r6,isr_restore
    429         stw        %r6, 0(%r4)
     337        stw        %r6, R%_Thread_Dispatch_disable_level(%r4)
    430338
    431339# check whether or not a context switch is necessary
    … …  
    437345# check whether or not a context switch is necessary because an ISR
    438346#    sent signals to the interrupted task
    439         .import    _ISR_Signals_to_thread_executing,data
    440         ldil       L%_ISR_Signals_to_thread_executing,%r8
    441         ldw        R%_ISR_Signals_to_thread_executing(%r8),%r8
     347        ldw        R%_ISR_Signals_to_thread_executing(%r7),%r8
    442348        comibt,=,n 0,%r8,isr_restore
    443349
    … …  
    451357
    452358ISR_dispatch:
     359        stw        %r0, R%_ISR_Signals_to_thread_executing(%r7)
     360
    453361        ssm        HPPA_PSW_I, %r0
    454362
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