Changeset d074e12 in rtems for c/src/lib/libbsp/m68k/idp


Ignore:
Timestamp:
Aug 4, 1997, 10:22:59 PM (24 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, 5, master
Children:
5b9ec351
Parents:
19fd334
Message:

Switched to new version of mc68681.h

File:
1 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/m68k/idp/console/duart.c

    r19fd334 rd074e12  
    5050   */
    5151
    52   MC68681_WRITE(MC68681_INTERRUPT_MASK_REG, 0x00);
    53   MC68681_WRITE(MC68681_COMMAND_REG_A ,MC68681_MODE_REG_DISABLE_TX);
    54   MC68681_WRITE(MC68681_COMMAND_REG_A, MC68681_MODE_REG_DISABLE_RX);
    55   MC68681_WRITE(MC68681_COMMAND_REG_B, MC68681_MODE_REG_DISABLE_TX);
    56   MC68681_WRITE(MC68681_COMMAND_REG_B, MC68681_MODE_REG_DISABLE_RX);
     52  MC68681_WRITE(DUART_ADDR, MC68681_INTERRUPT_MASK_REG, 0x00);
     53  MC68681_WRITE(DUART_ADDR, MC68681_COMMAND_REG_A ,MC68681_MODE_REG_DISABLE_TX);
     54  MC68681_WRITE(DUART_ADDR, MC68681_COMMAND_REG_A, MC68681_MODE_REG_DISABLE_RX);
     55  MC68681_WRITE(DUART_ADDR, MC68681_COMMAND_REG_B, MC68681_MODE_REG_DISABLE_TX);
     56  MC68681_WRITE(DUART_ADDR, MC68681_COMMAND_REG_B, MC68681_MODE_REG_DISABLE_RX);
    5757
    5858  /*
     
    9393     *  reset mr pointer, ch
    9494     */
    95      MC68681_WRITE(MC68681_COMMAND_REG_B, MC68681_MODE_REG_RESET_TX);
    96      MC68681_WRITE(MC68681_COMMAND_REG_B, MC68681_MODE_REG_RESET_RX);
    97      MC68681_WRITE(MC68681_COMMAND_REG_B, MC68681_MODE_REG_RESET_MR_PTR);
     95     MC68681_WRITE(DUART_ADDR, MC68681_COMMAND_REG_B, MC68681_MODE_REG_RESET_TX);
     96     MC68681_WRITE(DUART_ADDR, MC68681_COMMAND_REG_B, MC68681_MODE_REG_RESET_RX);
     97     MC68681_WRITE(DUART_ADDR, MC68681_COMMAND_REG_B, MC68681_MODE_REG_RESET_MR_PTR);
    9898
    9999    /*
     
    105105     *  reset mr pointer, ch
    106106     */
    107      MC68681_WRITE(MC68681_COMMAND_REG_A, MC68681_MODE_REG_RESET_TX);
    108      MC68681_WRITE(MC68681_COMMAND_REG_A, MC68681_MODE_REG_RESET_RX);
    109      MC68681_WRITE(MC68681_COMMAND_REG_A, MC68681_MODE_REG_RESET_MR_PTR);
     107     MC68681_WRITE(DUART_ADDR, MC68681_COMMAND_REG_A, MC68681_MODE_REG_RESET_TX);
     108     MC68681_WRITE(DUART_ADDR, MC68681_COMMAND_REG_A, MC68681_MODE_REG_RESET_RX);
     109     MC68681_WRITE(DUART_ADDR, MC68681_COMMAND_REG_A, MC68681_MODE_REG_RESET_MR_PTR);
    110110
    111111     Pit_initialized = 1;
     
    123123   * init cts
    124124   */
    125   MC68681_WRITE(MC68681_INTERRUPT_VECTOR_REG, 
     125  MC68681_WRITE(DUART_ADDR, MC68681_INTERRUPT_VECTOR_REG, 
    126126                MC68681_INTERRUPT_VECTOR_INIT);
    127   MC68681_WRITE(MC68681_INTERRUPT_MASK_REG,
     127  MC68681_WRITE(DUART_ADDR, MC68681_INTERRUPT_MASK_REG,
    128128                MC68681_IR_RX_READY_A | MC68681_IR_RX_READY_B); 
    129   MC68681_WRITE(MC68681_AUX_CTRL_REG, MC68681_CLEAR);
    130   MC68681_WRITE(MC68681_COUNTER_TIMER_UPPER_REG, 0x00);
    131   MC68681_WRITE(MC68681_COUNTER_TIMER_LOWER_REG, 0x02);
    132   MC68681_WRITE(MC68681_OUTPUT_PORT_CONFIG_REG, MC68681_CLEAR);
    133   MC68681_WRITE(MC68681_OUTPUT_PORT_SET_REG, 0x01);
     129  MC68681_WRITE(DUART_ADDR, MC68681_AUX_CTRL_REG, MC68681_CLEAR);
     130  MC68681_WRITE(DUART_ADDR, MC68681_COUNTER_TIMER_UPPER_REG, 0x00);
     131  MC68681_WRITE(DUART_ADDR, MC68681_COUNTER_TIMER_LOWER_REG, 0x02);
     132  MC68681_WRITE(DUART_ADDR, MC68681_OUTPUT_PORT_CONFIG_REG, MC68681_CLEAR);
     133  MC68681_WRITE(DUART_ADDR, MC68681_OUTPUT_PORT_SET_REG, 0x01);
    134134
    135135  /*
     
    140140   * enable Transmit and receive
    141141   */
    142   MC68681_WRITE(MC68681_CLOCK_SELECT_REG_A, MC68681_BAUD_RATE_MASK_9600);
    143   MC68681_WRITE(MC68681_MODE_REG_1A,
     142  MC68681_WRITE(DUART_ADDR, MC68681_CLOCK_SELECT_REG_A, MC68681_BAUD_RATE_MASK_9600);
     143  MC68681_WRITE(DUART_ADDR, MC68681_MODE_REG_1A,
    144144                (MC68681_8BIT_CHARS | MC68681_NO_PARITY));
    145   MC68681_WRITE(MC68681_MODE_REG_2A,MC68681_STOP_BIT_LENGTH_1);
    146   MC68681_WRITE(MC68681_COMMAND_REG_A,
     145  MC68681_WRITE(DUART_ADDR, MC68681_MODE_REG_2A,MC68681_STOP_BIT_LENGTH_1);
     146  MC68681_WRITE(DUART_ADDR, MC68681_COMMAND_REG_A,
    147147                (MC68681_MODE_REG_ENABLE_TX | MC68681_MODE_REG_ENABLE_RX));
    148148
     
    151151   * init csrb -- 9600 baud
    152152   */
    153   MC68681_WRITE(MC68681_CLOCK_SELECT_REG_B, MC68681_BAUD_RATE_MASK_9600);
     153  MC68681_WRITE(DUART_ADDR, MC68681_CLOCK_SELECT_REG_B, MC68681_BAUD_RATE_MASK_9600);
    154154
    155155
     
    159159   * Set 8 Bit characters with no parity
    160160   */
    161   MC68681_WRITE(MC68681_MODE_REG_1B,
     161  MC68681_WRITE(DUART_ADDR, MC68681_MODE_REG_1B,
    162162                (MC68681_NO_PARITY | MC68681_8BIT_CHARS) );
    163163#else
     
    165165   * Set 7 Bit Characters with parity
    166166   */
    167   MC68681_WRITE(MC68681_MODE_REG_1B,
     167  MC68681_WRITE(DUART_ADDR, MC68681_MODE_REG_1B,
    168168                (MC68681_WITH_PARITY |  MC68681_7BIT_CHARS) );
    169169#endif
     
    174174   * Disable Recieve and transmit on B
    175175   */
    176   MC68681_WRITE(MC68681_MODE_REG_2B,MC68681_STOP_BIT_LENGTH_1);
    177   MC68681_WRITE(MC68681_COMMAND_REG_B,
     176  MC68681_WRITE(DUART_ADDR, MC68681_MODE_REG_2B,MC68681_STOP_BIT_LENGTH_1);
     177  MC68681_WRITE(DUART_ADDR, MC68681_COMMAND_REG_B,
    178178                (MC68681_MODE_REG_ENABLE_TX | MC68681_MODE_REG_ENABLE_RX) );
    179179}
     
    244244   * transmit character over port A
    245245   */
    246   MC68681_WRITE(MC68681_TRANSMIT_BUFFER_A, ch);
     246  MC68681_WRITE(DUART_ADDR, MC68681_TRANSMIT_BUFFER_A, ch);
    247247}
    248248
     
    267267   * transmit character over port B
    268268   */
    269   MC68681_WRITE(MC68681_TRANSMIT_BUFFER_B, ch);
    270 }
     269  MC68681_WRITE(DUART_ADDR, MC68681_TRANSMIT_BUFFER_B, ch);
     270}
Note: See TracChangeset for help on using the changeset viewer.