Changeset d03776e in rtems
- Timestamp:
- 10/01/21 04:57:01 (2 years ago)
- Branches:
- master
- Children:
- 087e4ec
- Parents:
- 0f62af0e
- git-author:
- Alex White <alex.white@…> (10/01/21 04:57:01)
- git-committer:
- Joel Sherrill <joel@…> (10/13/21 19:45:37)
- Files:
-
- 37 added
- 2 deleted
- 4 edited
- 10 moved
Legend:
- Unmodified
- Added
- Removed
-
bsps/include/bsp/fatal.h
r0f62af0e rd03776e 175 175 IMXRT_FATAL_LPI2C_REGISTER_FAILED, 176 176 IMXRT_FATAL_LPI2C_UNSUPPORTED_HARDWARE, 177 178 /* MicroBlaze fatal codes */ 179 MICROBLAZE_FATAL_CLOCK_IRQ_INSTALL = BSP_FATAL_CODE_BLOCK(16), 177 180 } bsp_fatal_code; 178 181 -
bsps/microblaze/include/bsp/linker-symbols.h
r0f62af0e rd03776e 1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 1 3 /* 2 * 4 * Copyright (C) 2015 Hesham Almatary 3 5 * 4 6 * Redistribution and use in source and binary forms, with or without … … 8 10 * notice, this list of conditions and the following disclaimer. 9 11 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the11 * documentation and/or other materials provided with the distribution.12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 12 14 * 13 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -
bsps/microblaze/microblaze_fpga/console/debug-io.c
r0f62af0e rd03776e 1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 1 3 /** 2 4 * @file 3 5 * 4 * @ingroup microblaze_uart6 * @ingroup RTEMSBSPsMicroblaze 5 7 * 6 * @brief Console Configuration.8 * @brief MicroBlaze debug IO support 7 9 */ 8 10 9 11 /* 10 * Copyright (C) 2015 Hesham Almatary 12 * Copyright (C) 2015 Hesham Almatary 13 * Copyright (C) 2021 On-Line Applications Research Corporation (OAR) 11 14 * 12 15 * Redistribution and use in source and binary forms, with or without … … 16 19 * notice, this list of conditions and the following disclaimer. 17 20 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the19 * documentation and/or other materials provided with the distribution.21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 20 23 * 21 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" … … 32 35 */ 33 36 37 #include <dev/serial/uartlite_l.h> 34 38 #include <rtems/bspIo.h> 35 39 36 #include < libchip/serial.h>40 #include <bspopts.h> 37 41 38 #include <bspopts.h> 39 #include <bsp/uart.h> 42 static void output_char( char c ) 43 { 44 if ( c == '\n' ) { 45 XUartLite_SendByte( BSP_MICROBLAZE_FPGA_UART_BASE, '\r' ); 46 } 47 XUartLite_SendByte( BSP_MICROBLAZE_FPGA_UART_BASE, c ); 48 } 40 49 41 console_tbl Console_Configuration_Ports [] = { 42 { 43 .sDeviceName = "/dev/ttyS0", 44 .deviceType = SERIAL_CUSTOM, 45 .pDeviceFns = µblaze_uart_fns, 46 .deviceProbe = NULL, 47 .pDeviceFlow = NULL, 48 .ulCtrlPort1 = UART_BASEADDRESS, 49 .ulCtrlPort2 = 0, 50 .ulClock = 9600, 51 .ulIntVector = 0 52 } 53 }; 50 static int xUartLite_RecvByte( int minor ) 51 { 52 if ( XUartLite_IsReceiveEmpty( BSP_MICROBLAZE_FPGA_UART_BASE ) ) { 53 return -1; 54 } 54 55 55 #define PORT_COUNT \ 56 (sizeof(Console_Configuration_Ports) \ 57 / sizeof(Console_Configuration_Ports [0])) 56 return XUartLite_ReadReg( BSP_MICROBLAZE_FPGA_UART_BASE, XUL_RX_FIFO_OFFSET ); 57 } 58 58 59 unsigned long Console_Configuration_Count = PORT_COUNT; 60 61 static void output_char(char c) 59 static int get_char( void ) 62 60 { 63 const console_fns *con = 64 Console_Configuration_Ports [Console_Port_Minor].pDeviceFns; 65 66 if (c == '\n') { 67 con->deviceWritePolled((int) Console_Port_Minor, '\r'); 68 } 69 con->deviceWritePolled((int) Console_Port_Minor, c); 61 return xUartLite_RecvByte( 0 ); 70 62 } 71 63 72 64 BSP_output_char_function_type BSP_output_char = output_char; 73 65 74 BSP_polling_getchar_function_type BSP_poll_char = NULL;66 BSP_polling_getchar_function_type BSP_poll_char = get_char; -
bsps/microblaze/microblaze_fpga/include/bsp.h
r0f62af0e rd03776e 1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 3 /** 4 * @file 5 * 6 * @ingroup RTEMSBSPsMicroblaze 7 * 8 * @brief Core BSP definitions 9 */ 10 1 11 /* 2 * Copyright (C) 2015 Hesham Almatary 12 * Copyright (C) 2015 Hesham Almatary 13 * Copyright (C) 2021 On-Line Applications Research Corporation (OAR) 3 14 * 4 15 * Redistribution and use in source and binary forms, with or without … … 8 19 * notice, this list of conditions and the following disclaimer. 9 20 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the11 * documentation and/or other materials provided with the distribution.21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 12 23 * 13 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" … … 24 35 */ 25 36 26 #ifndef _BSP_H27 #define _BSP_H37 #ifndef LIBBSP_MICROBLAZE_FPGA_BSP_H 38 #define LIBBSP_MICROBLAZE_FPGA_BSP_H 28 39 29 40 #ifdef __cplusplus … … 32 43 33 44 #include <bspopts.h> 45 #include <bsp/default-initial-extension.h> 34 46 35 47 #include <rtems.h> 36 #include <rtems/iosupp.h>37 #include <rtems/console.h>38 #include <rtems/clockdrv.h>39 40 /* support for simulated clock tick */41 Thread clock_driver_sim_idle_body(uintptr_t);42 #define BSP_IDLE_TASK_BODY clock_driver_sim_idle_body43 48 44 49 #ifdef __cplusplus … … 46 51 #endif 47 52 48 #endif 53 #endif /* LIBBSP_MICROBLAZE_FPGA_BSP_H */ -
bsps/microblaze/microblaze_fpga/include/tm27.h
r0f62af0e rd03776e 1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 3 /** 4 * @file 5 * 6 * @ingroup RTEMSBSPsMicroblaze 7 * 8 * @brief BSP tm27 header 9 */ 10 1 11 /* 2 * COPYRIGHT (c) 1989-2011. 3 * On-Line Applications Research Corporation (OAR). 12 * Copyright (C) 2021 On-Line Applications Research Corporation (OAR) 4 13 * 5 14 * Redistribution and use in source and binary forms, with or without … … 9 18 * notice, this list of conditions and the following disclaimer. 10 19 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the12 * documentation and/or other materials provided with the distribution.20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 13 22 * 14 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" … … 33 42 34 43 /* 35 * Define the interrupt mechanism for Time Test 27 44 * Time Test 27 cannot be implemented reliably because the AXI interrupt 45 * controller is not guaranteed to support software interrupts. 36 46 */ 37 47 … … 40 50 #define Install_tm27_vector( handler ) /* set_vector( (handler), 6, 1 ) */ 41 51 42 #define Cause_tm27_intr() /* XXX*/52 #define Cause_tm27_intr() /* empty */ 43 53 44 #define Clear_tm27_intr() /* XXX*/54 #define Clear_tm27_intr() /* empty */ 45 55 46 56 #define Lower_tm27_intr() /* empty */ 47 57 48 #endif 58 #endif /* __tm27_h */ -
bsps/microblaze/microblaze_fpga/start/_exception_handler.S
r0f62af0e rd03776e 1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 1 3 /* Copyright (c) 2001, 2009 Xilinx, Inc. All rights reserved. 2 4 … … 35 37 36 38 _exception_handler: 39 #ifndef __rtems__ 37 40 rtsd r17, 0 38 41 nop 42 #else /* __rtems__ */ 43 /* Subtract stack frame */ 44 addik r1, r1, -52 45 46 swi r5, r1, 8 47 48 addi r5, r0, 0xFFFF 49 50 braid _ISR_Handler 51 nop 52 #endif /* __rtems__ */ -
bsps/microblaze/microblaze_fpga/start/_hw_exception_handler.S
r0f62af0e rd03776e 1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 1 3 /* Copyright (c) 2001, 2009 Xilinx, Inc. All rights reserved. 2 4 … … 35 37 36 38 _hw_exception_handler: 37 rted r17, 0 39 #ifndef __rtems__ 40 rtsd r17, 0 38 41 nop 42 #else /* __rtems__ */ 43 /* Subtract stack frame */ 44 addik r1, r1, -52 45 46 swi r5, r1, 8 47 48 addi r5, r0, 0xFFFF 49 50 braid _ISR_Handler 51 nop 52 #endif /* __rtems__ */ -
bsps/microblaze/microblaze_fpga/start/_interrupt_handler.S
r0f62af0e rd03776e 1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 1 3 /* Copyright (c) 2001, 2009 Xilinx, Inc. All rights reserved. 2 4 … … 35 37 36 38 _interrupt_handler: 39 #ifndef __rtems__ 37 40 rtid r14, 0 38 41 nop 42 #else /* __rtems__ */ 43 /* Subtract stack frame */ 44 addik r1, r1, -52 45 46 swi r5, r1, 8 47 48 /* Indicate unknown interrupt source */ 49 addi r5, r0, 0xFF 50 51 braid _ISR_Handler 52 nop 53 #endif /* __rtems__ */ -
bsps/microblaze/shared/start/start.S
r0f62af0e rd03776e 1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 1 3 /* Copyright (c) 2001, 2009 Xilinx, Inc. All rights reserved. 2 4 … … 35 37 ------- ----------- ------ 36 38 37 # 0x00 #(-- IMM --)38 # 0x04 #Reset _start139 # 0x00 # (-- IMM --) 40 # 0x04 # Reset _start1 39 41 40 # 0x08 #(-- IMM --)41 # 0x0c #Software Exception _exception_handler42 # 0x08 # (-- IMM --) 43 # 0x0c # Software Exception _exception_handler 42 44 43 # 0x10 #(-- IMM --)44 # 0x14 #Hardware Interrupt _interrupt_handler45 # 0x10 # (-- IMM --) 46 # 0x14 # Hardware Interrupt _interrupt_handler 45 47 46 # 0x18 #(-- IMM --)47 # 0x1C #Breakpoint Exception (-- Don't Care --)48 # 0x18 # (-- IMM --) 49 # 0x1C # Breakpoint Exception (-- Don't Care --) 48 50 49 # 0x20 #(-- IMM --)50 # 0x24 #Hardware Exception _hw_exception_handler51 # 0x20 # (-- IMM --) 52 # 0x24 # Hardware Exception _hw_exception_handler 51 53 52 54 */ … … 54 56 55 57 .globl _start 56 58 .section .vectors.reset, "ax" 57 59 .align 2 58 59 60 .ent _start 61 .type _start, @function 60 62 _start: 61 brai_start162 63 brai _start1 64 .end _start 63 65 64 65 66 .section .vectors.sw_exception, "ax" 67 .align 2 66 68 _vector_sw_exception: 67 brai_exception_handler69 brai _exception_handler 68 70 69 70 71 .section .vectors.interrupt, "ax" 72 .align 2 71 73 _vector_interrupt: 72 brai_interrupt_handler74 brai _interrupt_handler 73 75 74 75 76 .section .vectors.hw_exception, "ax" 77 .align 2 76 78 _vector_hw_exception: 77 brai_hw_exception_handler79 brai _hw_exception_handler 78 80 79 80 81 82 83 81 .section .text 82 .globl _start1 83 .align 2 84 .ent _start1 85 .type _start1, @function 84 86 _start1: 85 //la 86 //la 87 la r1, r0, bsp_section_stack_begin-16 /* 16 bytes (4 words are needed by crtinit for args and link reg */87 //la r13, r0, _SDA_BASE_ /* Set the Small Data Anchors and the stack pointer */ 88 //la r2, r0, _SDA2_BASE_ 89 la r1, r0, _ISR_Stack_area_end-16 /* 16 bytes (4 words are needed by crtinit for args and link reg */ 88 90 89 brlid 91 brlid r15, _crtinit /* Initialize BSS and run program */ 90 92 nop 91 93 92 brlid r15, exit /* Call exit with the return value of main */ 93 addik r5, r3, 0 94 #ifndef __rtems__ 95 brlid r15, exit /* Call exit with the return value of main */ 96 addik r5, r3, 0 97 #endif /* __rtems__ */ 94 98 95 96 99 /* Control does not reach here */ 100 .end _start1 97 101 98 102 #ifndef __rtems__ 99 103 /* 100 101 104 _exit 105 Our simple _exit 102 106 */ 103 104 105 106 107 .globl _exit 108 .align 2 109 .ent _exit 110 .type _exit, @function 107 111 _exit: 108 112 bri 0 109 113 .end _exit 114 #endif /* __rtems__ */ -
cpukit/score/cpu/microblaze/cpu.c
r0f62af0e rd03776e 1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 3 /** 4 * @file 5 * 6 * @ingroup RTEMSScoreCPUMicroBlaze 7 * 8 * @brief MicroBlaze architecture support implementation 9 */ 10 1 11 /* 2 * Copyright (c) 2015, Hesham Almatary 3 * COPYRIGHT (c) 1989-2011. 4 * On-Line Applications Research Corporation (OAR). 12 * Copyright (c) 2015, Hesham Almatary 13 * Copyright (C) 2021 On-Line Applications Research Corporation (OAR) 5 14 * 6 15 * Redistribution and use in source and binary forms, with or without … … 10 19 * notice, this list of conditions and the following disclaimer. 11 20 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the13 * documentation and/or other materials provided with the distribution.21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 14 23 * 15 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" … … 30 39 #endif 31 40 32 #include <rtems/system.h>33 41 #include <rtems/score/isr.h> 42 #include <rtems/score/tls.h> 34 43 #include <rtems/score/wkspace.h> 35 44 36 /* _CPU_Initialize 37 * 38 * This routine performs processor dependent initialization. 39 * 40 * INPUT PARAMETERS: NONE 41 * 42 * NO_CPU Specific Information: 43 * 44 * XXX document implementation including references if appropriate 45 */ 46 47 void _CPU_Initialize(void) 45 void _CPU_Initialize( void ) 48 46 { 49 /*50 * If there is not an easy way to initialize the FP context51 * during Context_Initialize, then it is usually easier to52 * save an "uninitialized" FP context here and copy it to53 * the task's during Context_Initialize.54 */55 56 /* FP context initialization support goes here */57 47 } 58 48 … … 67 57 ) 68 58 { 69 uint32_t stack = ( (uint32_t) stack_area_begin);59 uint32_t stack = (uint32_t) stack_area_begin; 70 60 uint32_t stack_high = stack + stack_area_size; 71 61 72 memset( context, 0, sizeof(*context));62 memset( context, 0, sizeof(*context) ) ; 73 63 74 context->r[0] = stack_high; 75 context->r[3] = (uint32_t) entry_point; 64 context->r1 = stack_high - 64; 65 context->r15 = (uint32_t) entry_point; 66 67 uint32_t msr; 68 _CPU_MSR_GET( msr ); 69 context->rmsr = msr; 70 71 if ( tls_area != NULL ) { 72 _TLS_TCB_at_area_begin_initialize( tls_area ); 73 } 76 74 } 77 75 78 /*PAGE 79 * 80 * _CPU_ISR_Get_level 81 * 82 * NO_CPU Specific Information: 83 * 84 * XXX document implementation including references if appropriate 85 */ 86 87 uint32_t _CPU_ISR_Get_level( void ) 88 { 89 /* 90 * This routine returns the current interrupt level. 91 */ 92 93 return 0; 94 } 95 96 /*PAGE 97 * 98 * _CPU_ISR_install_raw_handler 99 * 100 * NO_CPU Specific Information: 101 * 102 * XXX document implementation including references if appropriate 103 */ 104 105 void _CPU_ISR_install_raw_handler( 106 uint32_t vector, 107 proc_ptr new_handler, 108 proc_ptr *old_handler 109 ) 110 { 111 /* 112 * This is where we install the interrupt handler into the "raw" interrupt 113 * table used by the CPU to dispatch interrupt handlers. 114 */ 115 } 116 117 /*PAGE 118 * 119 * _CPU_ISR_install_vector 120 * 121 * This kernel routine installs the RTEMS handler for the 122 * specified vector. 123 * 124 * Input parameters: 125 * vector - interrupt vector number 126 * old_handler - former ISR for this vector number 127 * new_handler - replacement ISR for this vector number 128 * 129 * Output parameters: NONE 130 * 131 * 132 * NO_CPU Specific Information: 133 * 134 * XXX document implementation including references if appropriate 135 */ 136 137 void _CPU_ISR_install_vector( 138 uint32_t vector, 139 proc_ptr new_handler, 140 proc_ptr *old_handler 141 ) 142 { 143 *old_handler = _ISR_Vector_table[ vector ]; 144 145 /* 146 * If the interrupt vector table is a table of pointer to isr entry 147 * points, then we need to install the appropriate RTEMS interrupt 148 * handler for this vector number. 149 */ 150 151 _CPU_ISR_install_raw_handler( vector, new_handler, old_handler ); 152 153 /* 154 * We put the actual user ISR address in '_ISR_vector_table'. This will 155 * be used by the _ISR_Handler so the user gets control. 156 */ 157 158 _ISR_Vector_table[ vector ] = new_handler; 159 } 160 161 /*PAGE 162 * 163 * _CPU_Install_interrupt_stack 164 * 165 * NO_CPU Specific Information: 166 * 167 * XXX document implementation including references if appropriate 168 */ 169 170 void _CPU_Install_interrupt_stack( void ) 76 void _CPU_Exception_frame_print( const CPU_Exception_frame *ctx ) 171 77 { 172 78 } 173 79 174 /*PAGE 175 * 176 * _CPU_Thread_Idle_body 177 * 178 * NOTES: 179 * 180 * 1. This is the same as the regular CPU independent algorithm. 181 * 182 * 2. If you implement this using a "halt", "idle", or "shutdown" 183 * instruction, then don't forget to put it in an infinite loop. 184 * 185 * 3. Be warned. Some processors with onboard DMA have been known 186 * to stop the DMA if the CPU were put in IDLE mode. This might 187 * also be a problem with other on-chip peripherals. So use this 188 * hook with caution. 189 * 190 * NO_CPU Specific Information: 191 * 192 * XXX document implementation including references if appropriate 193 */ 80 void _CPU_ISR_Set_level( uint32_t level ) 81 { 82 uint32_t microblaze_switch_reg; 83 84 _CPU_MSR_GET( microblaze_switch_reg ); 85 86 if ( level == 0 ) { 87 microblaze_switch_reg |= (MICROBLAZE_MSR_IE | MICROBLAZE_MSR_EE); 88 } else { 89 microblaze_switch_reg &= ~(MICROBLAZE_MSR_IE | MICROBLAZE_MSR_EE); 90 } 91 92 _CPU_MSR_SET( microblaze_switch_reg ); 93 } 94 95 uint32_t _CPU_ISR_Get_level( void ) 96 { 97 uint32_t level; 98 99 _CPU_MSR_GET( level ); 100 101 /* This is unique. The MSR register contains an interrupt enable flag where 102 * most other architectures have an interrupt disable flag. */ 103 return ( level & (MICROBLAZE_MSR_IE | MICROBLAZE_MSR_EE) ) == 0; 104 } 105 106 void _CPU_ISR_install_vector( 107 uint32_t vector, 108 CPU_ISR_handler new_handler, 109 CPU_ISR_handler *old_handler 110 ) 111 { 112 *old_handler = _ISR_Vector_table[ vector ]; 113 _ISR_Vector_table[ vector ] = new_handler; 114 } 194 115 195 116 void *_CPU_Thread_Idle_body( uintptr_t ignored ) 196 117 { 197 198 for( ; ; ) 199 /* insert your "halt" instruction here */ ; 200 return NULL; 118 while ( true ) { 119 __asm__ volatile ( "sleep" ); 120 } 201 121 } -
cpukit/score/cpu/microblaze/include/rtems/asm.h
r0f62af0e rd03776e 1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 1 3 /** 2 * @file rtems/asm.h4 * @file 3 5 * 4 * This include file attempts to address the problems 5 * caused by incompatible flavors of assemblers and 6 * toolsets. It primarily addresses variations in the 7 * use of leading underscores on symbols and the requirement 8 * that register names be preceded by a %. 6 * @brief MicroBlaze assembler support 7 * 8 * This include file attempts to address the problems 9 * caused by incompatible flavors of assemblers and 10 * toolsets. It primarily addresses variations in the 11 * use of leading underscores on symbols and the requirement 12 * that register names be preceded by a %. 9 13 */ 10 14 11 15 /* 12 * NOTE: The spacing in the use of these macros13 * is critical to them working as advertised.16 * Copyright (c) 2015, Hesham Almatary 17 * Copyright (C) 2021 On-Line Applications Research Corporation (OAR) 14 18 * 15 * COPYRIGHT: 19 * Redistribution and use in source and binary forms, with or without 20 * modification, are permitted provided that the following conditions 21 * are met: 22 * 1. Redistributions of source code must retain the above copyright 23 * notice, this list of conditions and the following disclaimer. 24 * 2. Redistributions in binary form must reproduce the above copyright 25 * notice, this list of conditions and the following disclaimer in the 26 * documentation and/or other materials provided with the distribution. 16 27 * 17 * This file is based on similar code found in newlib available 18 * from ftp.cygnus.com. The file which was used had no copyright 19 * notice. This file is freely distributable as long as the source 20 * of the file is noted. This file is: 21 * 22 * Copyright (c) 2015, Hesham Almatary 23 * COPYRIGHT (c) 1994-2006. 24 * On-Line Applications Research Corporation (OAR). 25 * 26 * $Id: asm.h,v 1.16 2006/01/16 15:12:12 joel Exp $ 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 29 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 31 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 32 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 33 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 34 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 35 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 36 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 37 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGE. 27 39 */ 28 40 … … 37 49 #define ASM 38 50 #endif 51 39 52 #include <rtems/score/cpuopts.h> 40 53 -
cpukit/score/cpu/microblaze/include/rtems/score/microblaze.h
r0f62af0e rd03776e 1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 3 /** 4 * @file 5 * 6 * @ingroup RTEMSScoreCPU 7 * 8 * @brief MicroBlaze architecture support 9 */ 10 1 11 /* 2 * Copyright (c) 2015, Hesham Almatary 3 * COPYRIGHT (c) 1989-2008. 4 * On-Line Applications Research Corporation (OAR). 12 * Copyright (c) 2015, Hesham Almatary 13 * Copyright (C) 2021 On-Line Applications Research Corporation (OAR) 5 14 * 6 15 * Redistribution and use in source and binary forms, with or without … … 10 19 * notice, this list of conditions and the following disclaimer. 11 20 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the13 * documentation and/or other materials provided with the distribution.21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 14 23 * 15 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" … … 26 35 */ 27 36 28 /* 29 * This file sets up basic CPU dependency settings based on 30 * compiler settings. For example, it can determine if 31 * floating point is available. This particular implementation 32 * is specified to the NO CPU port. 33 * 34 * $Id: no_cpu.h,v 1.9 2009/12/02 09:48:25 ralf Exp $ 35 * 36 */ 37 38 39 #ifndef _RTEMS_SCORE_NO_CPU_H 40 #define _RTEMS_SCORE_NO_CPU_H 37 #ifndef _RTEMS_SCORE_MICROBLAZE_H 38 #define _RTEMS_SCORE_MICROBLAZE_H 41 39 42 40 #ifdef __cplusplus … … 44 42 #endif 45 43 46 /*47 * This file contains the information required to build48 * RTEMS for a particular member of the NO CPU family.49 * It does this by setting variables to indicate which50 * implementation dependent features are present in a particular51 * member of the family.52 *53 * This is a good place to list all the known CPU models54 * that this port supports and which RTEMS CPU model they correspond55 * to.56 */57 58 #if defined(rtems_multilib)59 /*60 * Figure out all CPU Model Feature Flags based upon compiler61 * predefines.62 */63 64 #define CPU_MODEL_NAME "rtems_multilib"65 #define NOCPU_HAS_FPU 166 67 #else68 /* if defined(__MICROBLAZE__) */69 70 44 #define CPU_MODEL_NAME "MicroBlaze" 71 #define NOCPU_HAS_FPU 1 72 73 /* 74 #else 75 76 #error "Unsupported CPU Model" 77 */ 78 79 #endif 45 #define NOCPU_HAS_FPU 1 80 46 81 47 /* … … 89 55 #endif 90 56 91 #endif /* _RTEMS_SCORE_ NO_CPU_H */57 #endif /* _RTEMS_SCORE_MICROBLAZE_H */ -
cpukit/score/cpu/microblaze/microblaze-context-switch.S
r0f62af0e rd03776e 1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 3 /** 4 * @file 5 * 6 * @ingroup RTEMSScoreCPUMicroBlaze 7 * 8 * @brief MicroBlaze context switch implementation 9 */ 10 1 11 /* 2 * Copyright (c) 2015, Hesham Almatary 12 * Copyright (c) 2015, Hesham Almatary 13 * Copyright (C) 2021 On-Line Applications Research Corporation (OAR) 3 14 * 4 15 * Redistribution and use in source and binary forms, with or without … … 8 19 * notice, this list of conditions and the following disclaimer. 9 20 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the11 * documentation and/or other materials provided with the distribution.21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 12 23 * 13 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" … … 60 71 swi r31, r5, 76 61 72 73 mfs r21, rmsr 74 swi r21, r5, 80 75 76 62 77 SYM(restore): 63 78 lwi r1, r6, 0 … … 80 95 lwi r29, r6, 68 81 96 lwi r30, r6, 72 97 98 lwi r31, r6, 80 99 mts rmsr, r31 100 82 101 lwi r31, r6, 76 83 102 -
spec/build/cpukit/librtemscpu.yml
r0f62af0e rd03776e 472 472 - role: build-dependency 473 473 uid: cpumips 474 - role: build-dependency 475 uid: cpumicroblaze 474 476 - role: build-dependency 475 477 uid: cpumoxie
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