Changeset cfd8d7a in rtems
- Timestamp:
- 05/08/13 07:30:31 (11 years ago)
- Branches:
- 4.11, 5, master
- Children:
- 9deed9ed
- Parents:
- 9dcc683
- git-author:
- Sebastian Huber <sebastian.huber@…> (05/08/13 07:30:31)
- git-committer:
- Sebastian Huber <sebastian.huber@…> (05/10/13 10:10:14)
- Files:
-
- 12 edited
Legend:
- Unmodified
- Added
- Removed
-
c/src/lib/libbsp/arm/realview-pbx-a9/make/custom/realview_pbx_a9_qemu.cfg
r9dcc683 rcfd8d7a 3 3 RTEMS_CPU = arm 4 4 5 CPU_CFLAGS = -m cpu=cortex-a9 -mthumb5 CPU_CFLAGS = -march=armv7-a -mthumb -mfpu=neon -mfloat-abi=hard -mtune=cortex-a9 6 6 7 7 CFLAGS_OPTIMIZE_V ?= -O0 -g -
c/src/lib/libbsp/arm/shared/start/start.S
r9dcc683 rcfd8d7a 155 155 /* Stay in SVC mode */ 156 156 157 #ifdef ARM_MULTILIB_VFP_D32 158 /* Read CPACR */ 159 mrc p15, 0, r0, c1, c0, 2 160 161 /* Enable CP10 and CP11 */ 162 orr r0, r0, #(1 << 20) 163 orr r0, r0, #(1 << 22) 164 165 /* Clear ASEDIS and D32DIS */ 166 bic r0, r0, #(3 << 30) 167 168 /* Write CPACR */ 169 mcr p15, 0, r0, c1, c0, 2 170 isb 171 172 /* Enable FPU */ 173 mov r0, #(1 << 30) 174 vmsr FPEXC, r0 175 #endif 176 157 177 /* 158 178 * Branch to start hook 0. -
c/src/lib/libbsp/arm/xilinx-zynq/make/custom/xilinx_zynq_a9_qemu.cfg
r9dcc683 rcfd8d7a 3 3 RTEMS_CPU = arm 4 4 5 CPU_CFLAGS = -m cpu=cortex-a9 -mthumb5 CPU_CFLAGS = -march=armv7-a -mthumb -mfpu=neon -mfloat-abi=hard -mtune=cortex-a9 6 6 7 7 CFLAGS_OPTIMIZE_V ?= -O0 -g -
cpukit/score/cpu/arm/arm-context-validate.S
r9dcc683 rcfd8d7a 18 18 19 19 #include <rtems/asm.h> 20 #include <rtems/score/cpu.h> 20 21 21 22 #define FRAME_OFFSET_R4 0 … … 29 30 #define FRAME_OFFSET_LR 32 30 31 31 #define FRAME_SIZE (FRAME_OFFSET_LR + 4) 32 #ifdef ARM_MULTILIB_VFP_D32 33 #define FRAME_OFFSET_D8 40 34 #define FRAME_OFFSET_D9 48 35 #define FRAME_OFFSET_D10 56 36 #define FRAME_OFFSET_D11 64 37 #define FRAME_OFFSET_D12 72 38 #define FRAME_OFFSET_D13 80 39 #define FRAME_OFFSET_D14 88 40 #define FRAME_OFFSET_D15 96 41 42 #define FRAME_SIZE (FRAME_OFFSET_D15 + 8) 43 #else 44 #define FRAME_SIZE (FRAME_OFFSET_LR + 4) 45 #endif 32 46 33 47 .section .text … … 58 72 str r1, [sp, #FRAME_OFFSET_LR] 59 73 74 #ifdef ARM_MULTILIB_VFP_D32 75 vstr d8, [sp, #FRAME_OFFSET_D8] 76 vstr d9, [sp, #FRAME_OFFSET_D9] 77 vstr d10, [sp, #FRAME_OFFSET_D10] 78 vstr d11, [sp, #FRAME_OFFSET_D11] 79 vstr d12, [sp, #FRAME_OFFSET_D12] 80 vstr d13, [sp, #FRAME_OFFSET_D13] 81 vstr d14, [sp, #FRAME_OFFSET_D14] 82 vstr d15, [sp, #FRAME_OFFSET_D15] 83 #endif 84 60 85 /* Fill */ 61 86 … … 71 96 .endm 72 97 98 99 #ifdef ARM_MULTILIB_VFP_D32 100 /* R3 contains the FPSCR */ 101 vmrs r3, FPSCR 102 movs r4, #0x001f 103 movt r4, #0xf800 104 bic r3, r3, r4 105 and r4, r4, r0 106 orr r3, r3, r4 107 vmsr FPSCR, r3 108 #else 73 109 fill_register r3 110 #endif 111 74 112 fill_register r4 75 113 fill_register r5 … … 83 121 fill_register lr 84 122 123 #ifdef ARM_MULTILIB_VFP_D32 124 .macro fill_vfp_register reg 125 add r1, r1, #1 126 vmov \reg, r1, r1 127 .endm 128 129 fill_vfp_register d0 130 fill_vfp_register d1 131 fill_vfp_register d2 132 fill_vfp_register d3 133 fill_vfp_register d4 134 fill_vfp_register d5 135 fill_vfp_register d6 136 fill_vfp_register d7 137 fill_vfp_register d8 138 fill_vfp_register d9 139 fill_vfp_register d10 140 fill_vfp_register d11 141 fill_vfp_register d12 142 fill_vfp_register d13 143 fill_vfp_register d14 144 fill_vfp_register d15 145 fill_vfp_register d16 146 fill_vfp_register d17 147 fill_vfp_register d18 148 fill_vfp_register d19 149 fill_vfp_register d20 150 fill_vfp_register d21 151 fill_vfp_register d22 152 fill_vfp_register d23 153 fill_vfp_register d24 154 fill_vfp_register d25 155 fill_vfp_register d26 156 fill_vfp_register d27 157 fill_vfp_register d28 158 fill_vfp_register d29 159 fill_vfp_register d30 160 fill_vfp_register d31 161 #endif 162 85 163 /* Check */ 86 164 check: … … 97 175 mov r1, r0 98 176 177 #ifndef ARM_MULTILIB_VFP_D32 99 178 check_register r3 179 #endif 180 100 181 check_register r4 101 182 check_register r5 … … 108 189 check_register r12 109 190 check_register lr 191 192 #ifdef ARM_MULTILIB_VFP_D32 193 b check_vfp 194 #endif 110 195 111 196 b check … … 133 218 mov lr, r1 134 219 220 #ifdef ARM_MULTILIB_VFP_D32 221 vldr d8, [sp, #FRAME_OFFSET_D8] 222 vldr d9, [sp, #FRAME_OFFSET_D9] 223 vldr d10, [sp, #FRAME_OFFSET_D10] 224 vldr d11, [sp, #FRAME_OFFSET_D11] 225 vldr d12, [sp, #FRAME_OFFSET_D12] 226 vldr d13, [sp, #FRAME_OFFSET_D13] 227 vldr d14, [sp, #FRAME_OFFSET_D14] 228 vldr d15, [sp, #FRAME_OFFSET_D15] 229 #endif 230 135 231 add sp, sp, #FRAME_SIZE 136 232 … … 138 234 139 235 FUNCTION_END(_CPU_Context_validate) 236 237 #ifdef ARM_MULTILIB_VFP_D32 238 check_vfp: 239 240 .macro check_vfp_register reg 241 add r1, r1, #1 242 vmov r4, r5, \reg 243 cmp r4, r5 244 bne 1f 245 cmp r1, r4 246 bne 1f 247 b 2f 248 1: 249 b restore 250 2: 251 .endm 252 253 vmrs r4, FPSCR 254 cmp r4, r3 255 bne restore 256 257 check_vfp_register d0 258 check_vfp_register d1 259 check_vfp_register d2 260 check_vfp_register d3 261 check_vfp_register d4 262 check_vfp_register d5 263 check_vfp_register d6 264 check_vfp_register d7 265 check_vfp_register d8 266 check_vfp_register d9 267 check_vfp_register d10 268 check_vfp_register d11 269 check_vfp_register d12 270 check_vfp_register d13 271 check_vfp_register d14 272 check_vfp_register d15 273 check_vfp_register d16 274 check_vfp_register d17 275 check_vfp_register d18 276 check_vfp_register d19 277 check_vfp_register d20 278 check_vfp_register d21 279 check_vfp_register d22 280 check_vfp_register d23 281 check_vfp_register d24 282 check_vfp_register d25 283 check_vfp_register d26 284 check_vfp_register d27 285 check_vfp_register d28 286 check_vfp_register d29 287 check_vfp_register d30 288 check_vfp_register d31 289 290 /* Restore r4 and r5 */ 291 mov r1, r0 292 fill_register r4 293 fill_register r5 294 295 b check 296 297 #endif -
cpukit/score/cpu/arm/arm-context-volatile-clobber.S
r9dcc683 rcfd8d7a 28 28 .endm 29 29 30 #ifdef ARM_MULTILIB_VFP_D32 31 vmrs r1, FPSCR 32 movs r2, #0x001f 33 movt r2, #0xf800 34 bic r1, r1, r2 35 and r2, r2, r0 36 orr r1, r1, r2 37 vmsr FPSCR, r1 38 39 .macro clobber_vfp_register reg 40 sub r0, r0, #1 41 vmov \reg, r0, r0 42 .endm 43 44 clobber_vfp_register d0 45 clobber_vfp_register d1 46 clobber_vfp_register d2 47 clobber_vfp_register d3 48 clobber_vfp_register d4 49 clobber_vfp_register d5 50 clobber_vfp_register d6 51 clobber_vfp_register d7 52 clobber_vfp_register d16 53 clobber_vfp_register d17 54 clobber_vfp_register d18 55 clobber_vfp_register d19 56 clobber_vfp_register d20 57 clobber_vfp_register d21 58 clobber_vfp_register d22 59 clobber_vfp_register d23 60 clobber_vfp_register d24 61 clobber_vfp_register d25 62 clobber_vfp_register d26 63 clobber_vfp_register d27 64 clobber_vfp_register d28 65 clobber_vfp_register d29 66 clobber_vfp_register d30 67 clobber_vfp_register d31 68 #endif 69 30 70 clobber_register r1 31 71 clobber_register r2 -
cpukit/score/cpu/arm/arm-exception-frame-print.c
r9dcc683 rcfd8d7a 19 19 #include <rtems/score/cpu.h> 20 20 #include <rtems/bspIo.h> 21 22 static void _ARM_VFP_context_print( const ARM_VFP_context *vfp_context ) 23 { 24 #ifdef ARM_MULTILIB_VFP_D32 25 if ( vfp_context != NULL ) { 26 const uint64_t *dx = &vfp_context->register_d0; 27 int i; 28 29 printk( 30 "FPEXC = 0x%08x\nFPSCR = 0x%08x\n", 31 vfp_context->register_fpexc, 32 vfp_context->register_fpscr 33 ); 34 35 for ( i = 0; i < 32; ++i ) { 36 uint32_t low = (uint32_t) dx[i]; 37 uint32_t high = (uint32_t) (dx[i] >> 32); 38 39 printk( "D%02i = 0x%08x%08x\n", i, high, low ); 40 } 41 } 42 #endif 43 } 21 44 22 45 void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ) … … 60 83 frame->vector 61 84 ); 85 86 _ARM_VFP_context_print( frame->vfp_context ); 62 87 } -
cpukit/score/cpu/arm/arm_exc_interrupt.S
r9dcc683 rcfd8d7a 8 8 9 9 /* 10 * Copyright (c) 2009 11 * embedded brains GmbH 12 * Obere Lagerstr. 30 13 * D-82178 Puchheim 14 * Germany 15 * <rtems@embedded-brains.de> 10 * Copyright (c) 2009-2013 embedded brains GmbH. All rights reserved. 11 * 12 * embedded brains GmbH 13 * Dornierstr. 4 14 * 82178 Puchheim 15 * Germany 16 * <rtems@embedded-brains.de> 16 17 * 17 18 * The license and distribution terms for this file may be … … 45 46 #define CONTEXT_LIST {r0, r1, r2, r3, EXCHANGE_LR, EXCHANGE_SPSR, r12} 46 47 #define CONTEXT_SIZE 28 48 49 #ifdef ARM_MULTILIB_VFP_D32 50 #define VFP_CONTEXT_WITH_ALIGNMENT_SPACE (24 * 8 + 4 + 4) 51 #endif 47 52 48 53 .extern _Thread_Dispatch_disable_level … … 74 79 stmdb sp!, CONTEXT_LIST 75 80 stmdb sp!, {lr} 81 82 #ifdef ARM_MULTILIB_VFP_D32 83 /* Save VFP context */ 84 sub sp, #VFP_CONTEXT_WITH_ALIGNMENT_SPACE 85 add r1, sp, #4 86 vmrs r0, FPSCR 87 bic r1, r1, #7 88 vstmia r1!, {d0-d7} 89 vstmia r1!, {d16-d31} 90 str r0, [r1] 91 #endif 76 92 77 93 /* Remember INT stack pointer */ … … 145 161 SWITCH_FROM_THUMB_TO_ARM 146 162 163 #ifdef ARM_MULTILIB_VFP_D32 164 /* Restore VFP context */ 165 add r1, sp, #4 166 bic r1, r1, #7 167 vldmia r1!, {d0-d7} 168 vldmia r1!, {d16-d31} 169 ldr r0, [r1] 170 add sp, #VFP_CONTEXT_WITH_ALIGNMENT_SPACE 171 vmsr FPSCR, r0 172 #endif 173 147 174 /* Restore link register */ 148 175 ldmia sp!, {lr} -
cpukit/score/cpu/arm/armv4-exception-default.S
r9dcc683 rcfd8d7a 22 22 #ifdef ARM_MULTILIB_ARCH_V4 23 23 24 #define MORE_CONTEXT_SIZE \ 25 (ARM_EXCEPTION_FRAME_SIZE - ARM_EXCEPTION_FRAME_REGISTER_SP_OFFSET) 26 24 27 .extern _ARM_Exception_default 25 28 … … 39 42 40 43 /* Save context and load vector */ 41 sub sp, # 2044 sub sp, #MORE_CONTEXT_SIZE 42 45 stmdb sp!, {r0-r12} 43 46 mov r4, #1 … … 48 51 49 52 /* Save context and load vector */ 50 sub sp, # 2053 sub sp, #MORE_CONTEXT_SIZE 51 54 stmdb sp!, {r0-r12} 52 55 mov r4, #2 … … 57 60 58 61 /* Save context and load vector */ 59 sub sp, # 2062 sub sp, #MORE_CONTEXT_SIZE 60 63 stmdb sp!, {r0-r12} 61 64 mov r4, #3 … … 66 69 67 70 /* Save context and load vector */ 68 sub sp, # 2071 sub sp, #MORE_CONTEXT_SIZE 69 72 stmdb sp!, {r0-r12} 70 73 mov r4, #4 … … 73 76 74 77 /* Save context and load vector */ 75 sub sp, # 2078 sub sp, #MORE_CONTEXT_SIZE 76 79 stmdb sp!, {r0-r12} 77 80 mov r4, #5 … … 80 83 81 84 /* Save context and load vector */ 82 sub sp, # 2085 sub sp, #MORE_CONTEXT_SIZE 83 86 stmdb sp!, {r0-r12} 84 87 mov r4, #6 … … 87 90 88 91 /* Save context and load vector */ 89 sub sp, # 2092 sub sp, #MORE_CONTEXT_SIZE 90 93 stmdb sp!, {r0-r12} 91 94 mov r4, #7 … … 100 103 bic r5, #ARM_PSR_T 101 104 msr cpsr, r5 102 mov r0, sp105 sub r0, sp, #ARM_EXCEPTION_FRAME_SIZE 103 106 mov r1, lr 104 107 msr cpsr, r7 105 add r5, sp, #72 106 stmdb r5!, {r0-r4} 108 mov r5, #0 109 add r6, sp, #ARM_EXCEPTION_FRAME_REGISTER_SP_OFFSET 110 stm r6, {r0-r5} 111 112 /* Argument for high level handler */ 113 mov r0, sp 114 115 #ifdef ARM_MULTILIB_VFP_D32 116 /* Ensure that the FPU is enabled */ 117 vmrs r1, FPEXC 118 tst r1, #(1 << 30) 119 beq fpu_save_done 120 121 add r3, sp, #ARM_EXCEPTION_FRAME_VFP_CONTEXT_OFFSET 122 sub sp, #(ARM_VFP_CONTEXT_SIZE + 4) 123 add r4, sp, #4 124 bic r4, r4, #7 125 str r4, [r3] 126 vmrs r2, FPSCR 127 stmia r4!, {r1-r2} 128 vstmia r4!, {d0-d15} 129 vstmia r4!, {d16-d31} 130 131 fpu_save_done: 132 #endif 107 133 108 134 /* Call high level handler */ 109 mov r0, sp110 135 SWITCH_FROM_ARM_TO_THUMB r1 111 136 bl _ARM_Exception_default -
cpukit/score/cpu/arm/cpu.c
r9dcc683 rcfd8d7a 34 34 #include <rtems/score/thread.h> 35 35 #include <rtems/score/cpu.h> 36 37 #ifdef ARM_MULTILIB_VFP_D32 38 RTEMS_STATIC_ASSERT( 39 offsetof( Context_Control, register_d8 ) == ARM_CONTEXT_CONTROL_D8_OFFSET, 40 ARM_CONTEXT_CONTROL_D8_OFFSET 41 ); 42 #endif 43 44 RTEMS_STATIC_ASSERT( 45 sizeof( CPU_Exception_frame ) == ARM_EXCEPTION_FRAME_SIZE, 46 ARM_EXCEPTION_FRAME_SIZE 47 ); 48 49 RTEMS_STATIC_ASSERT( 50 offsetof( CPU_Exception_frame, register_sp ) 51 == ARM_EXCEPTION_FRAME_REGISTER_SP_OFFSET, 52 ARM_EXCEPTION_FRAME_REGISTER_SP_OFFSET 53 ); 54 55 RTEMS_STATIC_ASSERT( 56 sizeof( ARM_VFP_context ) == ARM_VFP_CONTEXT_SIZE, 57 ARM_VFP_CONTEXT_SIZE 58 ); 36 59 37 60 #ifdef ARM_MULTILIB_ARCH_V4 -
cpukit/score/cpu/arm/cpu_asm.S
r9dcc683 rcfd8d7a 31 31 32 32 #include <rtems/asm.h> 33 #include <rtems/score/cpu _asm.h>33 #include <rtems/score/cpu.h> 34 34 35 35 #ifdef ARM_MULTILIB_ARCH_V4 … … 58 58 stmia r0, {r2, r4, r5, r6, r7, r8, r9, r10, r11, r13, r14} 59 59 60 #ifdef ARM_MULTILIB_VFP_D32 61 add r3, r0, #ARM_CONTEXT_CONTROL_D8_OFFSET 62 vstm r3, {d8-d15} 63 #endif 60 64 61 65 /* Start restoring context */ 62 66 _restore: 67 68 #ifdef ARM_MULTILIB_VFP_D32 69 add r3, r1, #ARM_CONTEXT_CONTROL_D8_OFFSET 70 vldm r3, {d8-d15} 71 #endif 72 63 73 ldmia r1, {r2, r4, r5, r6, r7, r8, r9, r10, r11, r13, r14} 64 74 msr cpsr, r2 -
cpukit/score/cpu/arm/rtems/score/arm.h
r9dcc683 rcfd8d7a 38 38 #endif 39 39 40 /* All ARM CPUs are assumed to not have floating point units */ 41 #if defined(__SOFTFP__) 42 #define ARM_HAS_FPU 0 43 #else 44 #define ARM_HAS_FPU 1 45 #warning "FPU-support not yet implemented for the arm" 40 #if defined(__ARM_NEON__) 41 #define ARM_MULTILIB_VFP_D32 42 #elif !defined(__SOFTFP__) 43 #error "FPU support not implemented" 46 44 #endif 47 48 45 49 46 /* -
cpukit/score/cpu/arm/rtems/score/cpu.h
r9dcc683 rcfd8d7a 9 9 * processor. 10 10 * 11 * Copyright (c) 2009-201 1embedded brains GmbH.11 * Copyright (c) 2009-2013 embedded brains GmbH. 12 12 * 13 13 * Copyright (c) 2007 Ray Xu <Rayx.cn@gmail.com> … … 129 129 #define CPU_ISR_PASSES_FRAME_POINTER 0 130 130 131 #if ( ARM_HAS_FPU == 1 ) 132 #define CPU_HARDWARE_FP TRUE 133 #else 134 #define CPU_HARDWARE_FP FALSE 135 #endif 131 #define CPU_HARDWARE_FP FALSE 136 132 137 133 #define CPU_SOFTWARE_FP FALSE … … 214 210 215 211 /** @} */ 212 213 #ifdef ARM_MULTILIB_VFP_D32 214 #define ARM_CONTEXT_CONTROL_D8_OFFSET 48 215 #endif 216 217 #define ARM_EXCEPTION_FRAME_SIZE 76 218 219 #define ARM_EXCEPTION_FRAME_REGISTER_SP_OFFSET 52 220 221 #define ARM_EXCEPTION_FRAME_VFP_CONTEXT_OFFSET 72 222 223 #define ARM_VFP_CONTEXT_SIZE 264 216 224 217 225 #ifndef ASM … … 254 262 void *register_sp; 255 263 #endif 264 #ifdef ARM_MULTILIB_VFP_D32 265 uint64_t register_d8; 266 uint64_t register_d9; 267 uint64_t register_d10; 268 uint64_t register_d11; 269 uint64_t register_d12; 270 uint64_t register_d13; 271 uint64_t register_d14; 272 uint64_t register_d15; 273 #endif 256 274 } Context_Control; 257 275 … … 259 277 /* Not supported */ 260 278 } Context_Control_fp; 261 262 SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context;263 279 264 280 extern uint32_t arm_cpu_mode; … … 419 435 #define _CPU_Stop_multitasking _ARMV7M_Stop_multitasking 420 436 #endif 421 422 void _CPU_Context_save_fp( Context_Control_fp **fp_context_ptr );423 424 void _CPU_Context_restore_fp( Context_Control_fp **fp_context_ptr );425 437 426 438 void _CPU_Context_volatile_clobber( uintptr_t pattern ); … … 500 512 501 513 #endif /* defined(ARM_MULTILIB_ARCH_V4) */ 514 515 typedef struct { 516 uint32_t register_fpexc; 517 uint32_t register_fpscr; 518 uint64_t register_d0; 519 uint64_t register_d1; 520 uint64_t register_d2; 521 uint64_t register_d3; 522 uint64_t register_d4; 523 uint64_t register_d5; 524 uint64_t register_d6; 525 uint64_t register_d7; 526 uint64_t register_d8; 527 uint64_t register_d9; 528 uint64_t register_d10; 529 uint64_t register_d11; 530 uint64_t register_d12; 531 uint64_t register_d13; 532 uint64_t register_d14; 533 uint64_t register_d15; 534 uint64_t register_d16; 535 uint64_t register_d17; 536 uint64_t register_d18; 537 uint64_t register_d19; 538 uint64_t register_d20; 539 uint64_t register_d21; 540 uint64_t register_d22; 541 uint64_t register_d23; 542 uint64_t register_d24; 543 uint64_t register_d25; 544 uint64_t register_d26; 545 uint64_t register_d27; 546 uint64_t register_d28; 547 uint64_t register_d29; 548 uint64_t register_d30; 549 uint64_t register_d31; 550 } ARM_VFP_context; 502 551 503 552 typedef struct { … … 525 574 uint32_t vector; 526 575 #endif 576 const ARM_VFP_context *vfp_context; 527 577 } CPU_Exception_frame; 528 578
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