Ignore:
Timestamp:
Jul 27, 2018, 12:47:17 PM (15 months ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
master
Children:
44c2d393
Parents:
65f52d0
git-author:
Sebastian Huber <sebastian.huber@…> (07/27/18 12:47:17)
git-committer:
Sebastian Huber <sebastian.huber@…> (07/27/18 13:06:55)
Message:

riscv: Rework CPU counter support

Update #3433.

File:
1 edited

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  • cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h

    r65f52d0 rcfc9573  
    346346}
    347347
     348/*
     349 * The RISC-V ISA provides a rdtime instruction, however, it is implemented in
     350 * most chips via a trap-and-emulate.  Using this in machine mode makes no
     351 * sense.  Use the memory-mapped mtime register directly instead.  The address
     352 * of this register is platform-specific and provided via the device tree.
     353 *
     354 * To allow better code generation provide a const (_RISCV_Counter) and a
     355 * mutable (_RISCV_Counter_mutable) declaration for this pointer variable
     356 * (defined in assembler code).
     357 *
     358 * See code generated for this test case:
     359 *
     360 * extern volatile int * const c;
     361 *
     362 * extern volatile int *v;
     363 *
     364 * int fc(void)
     365 * {
     366 *   int a = *c;
     367 *   __asm__ volatile("" ::: "memory");
     368 *   return *c - a;
     369 * }
     370 *
     371 * int fv(void)
     372 * {
     373 *   int a = *v;
     374 *   __asm__ volatile("" ::: "memory");
     375 *   return *v - a;
     376 * }
     377 */
     378extern volatile uint32_t *_RISCV_Counter_mutable;
     379
     380/*
     381 * Initial value of _RISCV_Counter and _RISCV_Counter_mutable.  Must be
     382 * provided by the BSP.
     383 */
     384extern volatile uint32_t _RISCV_Counter_register;
     385
    348386#ifdef RTEMS_SMP
    349387
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