Changeset cfc9573 in rtems


Ignore:
Timestamp:
Jul 27, 2018, 12:47:17 PM (12 months ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
master
Children:
44c2d393
Parents:
65f52d0
git-author:
Sebastian Huber <sebastian.huber@…> (07/27/18 12:47:17)
git-committer:
Sebastian Huber <sebastian.huber@…> (07/27/18 13:06:55)
Message:

riscv: Rework CPU counter support

Update #3433.

Files:
1 added
4 edited

Legend:

Unmodified
Added
Removed
  • bsps/riscv/riscv/clock/clockdrv.c

    r65f52d0 rcfc9573  
    3333 */
    3434
    35 #include <rtems/timecounter.h>
    36 #include <rtems/score/cpuimpl.h>
    37 #include <rtems/score/riscv-utility.h>
    38 
    3935#include <bsp/fatal.h>
    4036#include <bsp/fdt.h>
    4137#include <bsp/irq.h>
    4238#include <bsp/riscv.h>
     39
     40#include <rtems/sysinit.h>
     41#include <rtems/timecounter.h>
     42#include <rtems/score/cpuimpl.h>
     43#include <rtems/score/riscv-utility.h>
    4344
    4445#include <libfdt.h>
     
    145146}
    146147
     148volatile uint32_t _RISCV_Counter_register;
     149
     150static void riscv_counter_initialize(void)
     151{
     152  _RISCV_Counter_mutable = &riscv_clint->mtime.val_32[0];
     153}
     154
    147155uint32_t _CPU_Counter_frequency( void )
    148156{
    149157  return riscv_clock_get_timebase_frequency(bsp_fdt_get());
    150158}
     159
     160RTEMS_SYSINIT_ITEM(
     161  riscv_counter_initialize,
     162  RTEMS_SYSINIT_CPU_COUNTER,
     163  RTEMS_SYSINIT_ORDER_FIRST
     164);
    151165
    152166#define Clock_driver_support_at_tick() riscv_clock_at_tick(&riscv_clock_tc)
  • cpukit/score/cpu/riscv/Makefile.am

    r65f52d0 rcfc9573  
    99libscorecpu_a_SOURCES += riscv-context-validate.S
    1010libscorecpu_a_SOURCES += riscv-context-volatile-clobber.S
     11libscorecpu_a_SOURCES += riscv-counter.S
    1112
    1213include $(top_srcdir)/automake/local.am
  • cpukit/score/cpu/riscv/include/rtems/score/cpu.h

    r65f52d0 rcfc9573  
    436436uint32_t _CPU_Counter_frequency( void );
    437437
     438extern volatile uint32_t * const _RISCV_Counter;
     439
    438440static inline CPU_Counter_ticks _CPU_Counter_read( void )
    439441{
    440   unsigned long ticks;
    441 
    442   __asm__ volatile ( "rdtime %0" : "=&r" ( ticks ) );
    443 
    444   return (uint32_t) ticks;
     442  return *_RISCV_Counter;
    445443}
    446444
  • cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h

    r65f52d0 rcfc9573  
    346346}
    347347
     348/*
     349 * The RISC-V ISA provides a rdtime instruction, however, it is implemented in
     350 * most chips via a trap-and-emulate.  Using this in machine mode makes no
     351 * sense.  Use the memory-mapped mtime register directly instead.  The address
     352 * of this register is platform-specific and provided via the device tree.
     353 *
     354 * To allow better code generation provide a const (_RISCV_Counter) and a
     355 * mutable (_RISCV_Counter_mutable) declaration for this pointer variable
     356 * (defined in assembler code).
     357 *
     358 * See code generated for this test case:
     359 *
     360 * extern volatile int * const c;
     361 *
     362 * extern volatile int *v;
     363 *
     364 * int fc(void)
     365 * {
     366 *   int a = *c;
     367 *   __asm__ volatile("" ::: "memory");
     368 *   return *c - a;
     369 * }
     370 *
     371 * int fv(void)
     372 * {
     373 *   int a = *v;
     374 *   __asm__ volatile("" ::: "memory");
     375 *   return *v - a;
     376 * }
     377 */
     378extern volatile uint32_t *_RISCV_Counter_mutable;
     379
     380/*
     381 * Initial value of _RISCV_Counter and _RISCV_Counter_mutable.  Must be
     382 * provided by the BSP.
     383 */
     384extern volatile uint32_t _RISCV_Counter_register;
     385
    348386#ifdef RTEMS_SMP
    349387
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