Ignore:
Timestamp:
May 8, 2009, 6:22:51 PM (10 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.9
Children:
82948ea1
Parents:
ef3a82f
Message:

2009-05-08 Kate Feng <feng1@…>

PR1395/bsps

  • Updated the changes from RTEMS-4.8.0, which were made since Oct. 2007.
  • network/if_1GHz/if_wm.c: fixed some bugs in the 1GHz driver.
  • pci/pci_interface.c: + Enabled PCI "Read", "Read Line", and "Read Multiple" + Agressive Prefetch to improve the performance of the PCI based

applications (e.g. 1GHz NIC).

  • irq/BSP_irq.c : Replaced the irq/irq.c, and used GT_GPP_Value register to monitor the cause of the level sensitive interrupts. This unique solution solves various bugs in the 1GHz network drivers Fixed bugs in compute_pic_masks_from_prio()
  • pci/pci.c : Updated it to be consistent with the original pci.c
  • written by Eric Valette. There is no change in its function.
  • irq/irq_init.c : set defaultIrq->next_handler to be 0
  • for BSP_SHARED_HANDLER_SUPPORT.
File:
1 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/powerpc/mvme5500/pci/pci.c

    ref3a82f rcf599996  
    1414 *  http://www.rtems.com/rtems/license.html.
    1515 *
    16  *  Copyright 2004, Brookhaven National Laboratory and
    17  *                  Shuchen K. Feng, <feng1@bnl.gov>, 2004
    18  *   - modified and added support for MVME5500 board
    19  *   - added 2nd PCI support for the mvme5500/GT64260 PCI bridge
    20  *   - added bus support for the expansion of PMCSpan, thanks to
    21  *     Peter Dufault (dufault@hda.com) for inputs.
    22  *
    23  * $Id$
     16 *  pci.c,v 1.2 2002/05/14 17:10:16 joel Exp
     17 *
     18 *  Copyright 2004, 2008 Brookhaven National Laboratory and
     19 *                  Shuchen K. Feng, <feng1@bnl.gov>
     20 *   
     21 *   - to be consistent with the original pci.c written by Eric Valette
     22 *   - added 2nd PCI support for discovery based PCI bridge (e.g. mvme5500/mvme6100)
     23 *   - added bus support for the expansion of PMCSpan as per request by Peter
    2424 */
    2525#define PCI_MAIN
     
    2828#include <rtems/bspIo.h>            /* printk */
    2929
     30#include <bsp/irq.h>
    3031#include <bsp/pci.h>
    3132#include <bsp/gtreg.h>
    3233#include <bsp/gtpcireg.h>
     34#include <bsp.h>
    3335
    3436#include <stdio.h>
     
    3638
    3739#define PCI_DEBUG 0
    38 #define PCI_PRINT 0
     40#define PCI_PRINT 1
    3941
    4042/* allow for overriding these definitions */
     
    5759#define HOSTBRIDGET_ERROR               0xf0000000
    5860
    59 /* define a shortcut */
    60 #define pci     BSP_pci_configuration
    61 
    62 static int                numPCIDevs=0;
     61#define GT64x60_PCI_CONFIG_ADDR         GT64x60_REG_BASE + PCI_CONFIG_ADDR
     62#define GT64x60_PCI_CONFIG_DATA         GT64x60_REG_BASE + PCI_CONFIG_DATA
     63
     64#define GT64x60_PCI1_CONFIG_ADDR        GT64x60_REG_BASE + PCI1_CONFIG_ADDR
     65#define GT64x60_PCI1_CONFIG_DATA        GT64x60_REG_BASE + PCI1_CONFIG_DATA
     66
     67static int      numPCIDevs=0;
     68static DiscoveryChipVersion BSP_sysControllerVersion = 0;
     69static BSP_VMEchipTypes BSP_VMEinterface = 0;
     70static pci_config BSP_pci[2]={
     71  {(volatile unsigned char*) (GT64x60_PCI_CONFIG_ADDR),
     72   (volatile unsigned char*) (GT64x60_PCI_CONFIG_DATA),
     73   0 /* defined at BSP_pci_configuration */},
     74  {(volatile unsigned char*) (GT64x60_PCI1_CONFIG_ADDR),
     75   (volatile unsigned char*) (GT64x60_PCI1_CONFIG_DATA),
     76   0 /* defined at BSP_pci_configuration */}
     77};
     78
    6379extern void pci_interface(void);
    6480
     
    6783 */
    6884#define pciConfigPack(bus,dev,func,offset)\
    69 (((func&7)<<8)|((dev&0x1f )<<11)|(( bus&0xff)<<16)|(offset&0xfc))|0x80000000
     85((offset&~3)<<24)|(PCI_DEVFN(dev,func)<<16)|(bus<<8)|0x80
    7086
    7187/*
     
    7692/* Please note that PCI0 and PCI1 does not correlate with the busNum 0 and 1.
    7793 */
    78 static int direct_pci_read_config_byte(unsigned char bus,unsigned char dev,unsigned char func,
     94static int indirect_pci_read_config_byte(unsigned char bus,unsigned char dev,unsigned char func,
    7995unsigned char offset,unsigned char *val)
    8096{
    81   volatile unsigned char *config_addr, *config_data;
    82 
    83   if (bus>= BSP_MAX_PCI_BUS_ON_PCI0) {
    84      bus-=BSP_MAX_PCI_BUS_ON_PCI0;
    85      config_addr = (volatile unsigned char*) PCI1_CONFIG_ADDR;
    86      config_data = (volatile unsigned char*) PCI1_CONFIG_DATA;
    87   }
    88   else {
    89      config_addr = pci.pci_config_addr;
    90      config_data = pci.pci_config_data;
    91   }
     97  int n=0;
     98
     99  if (bus>= BSP_MAX_PCI_BUS_ON_PCI0) {
     100     bus-=BSP_MAX_PCI_BUS_ON_PCI0;
     101     n=1;
     102  }
     103
    92104  *val = 0xff;
    93105  if (offset & ~0xff) return PCIBIOS_BAD_REGISTER_NUMBER;
    94106#if 0
    95   printk("addr %x, data %x, pack %x \n", config_addr,
    96     config_data,pciConfigPack(bus,dev,func,offset));
    97 #endif
    98   outl(pciConfigPack(bus,dev,func,offset),config_addr);
    99   *val = inb(config_data + (offset&3));
    100   return PCIBIOS_SUCCESSFUL;
    101 }
    102 
    103 static int direct_pci_read_config_word(unsigned char bus, unsigned char dev,
     107  printk("addr %x, data %x, pack %x \n", BSP_pci[n].pci_config_addr),
     108    BSP_pci[n].config_data,pciConfigPack(bus,dev,func,offset));
     109#endif
     110
     111  out_be32(BSP_pci[n].pci_config_addr, pciConfigPack(bus,dev,func,offset));
     112  *val = in_8(BSP_pci[n].pci_config_data + (offset&3));
     113  return PCIBIOS_SUCCESSFUL;
     114}
     115
     116static int indirect_pci_read_config_word(unsigned char bus, unsigned char dev,
    104117unsigned char func, unsigned char offset, unsigned short *val)
    105118{
    106   volatile unsigned char *config_addr, *config_data;
    107 
    108   if (bus>= BSP_MAX_PCI_BUS_ON_PCI0) {
    109      bus-=BSP_MAX_PCI_BUS_ON_PCI0;
    110      config_addr = (volatile unsigned char*) PCI1_CONFIG_ADDR;
    111      config_data = (volatile unsigned char*) PCI1_CONFIG_DATA;
    112   }
    113   else {
    114      config_addr = (volatile unsigned char*) pci.pci_config_addr;
    115      config_data = (volatile unsigned char*) pci.pci_config_data;
     119  int n=0;
     120
     121  if (bus>= BSP_MAX_PCI_BUS_ON_PCI0) {
     122     bus-=BSP_MAX_PCI_BUS_ON_PCI0;
     123     n=1;
    116124  }
    117125
     
    122130    config_data,pciConfigPack(bus,dev,func,offset));
    123131#endif
    124   outl(pciConfigPack(bus,dev,func,offset),config_addr);
    125   *val = inw(config_data + (offset&2));
    126   return PCIBIOS_SUCCESSFUL;
    127 }
    128 
    129 static int direct_pci_read_config_dword(unsigned char bus, unsigned char dev,
     132  out_be32(BSP_pci[n].pci_config_addr, pciConfigPack(bus,dev,func,offset));
     133  *val = in_le16(BSP_pci[n].pci_config_data + (offset&2));
     134  return PCIBIOS_SUCCESSFUL;
     135}
     136
     137static int indirect_pci_read_config_dword(unsigned char bus, unsigned char dev,
    130138unsigned char func, unsigned char offset, unsigned int *val)
    131139{
    132   volatile unsigned char *config_addr, *config_data;
    133 
    134   if (bus>= BSP_MAX_PCI_BUS_ON_PCI0) {
    135      bus-=BSP_MAX_PCI_BUS_ON_PCI0;
    136      config_addr = (volatile unsigned char*) PCI1_CONFIG_ADDR;
    137      config_data = (volatile unsigned char*) PCI1_CONFIG_DATA;
    138   }
    139   else {
    140      config_addr = (volatile unsigned char*) pci.pci_config_addr;
    141      config_data = (volatile unsigned char*) pci.pci_config_data;
     140  int n=0;
     141
     142  if (bus>= BSP_MAX_PCI_BUS_ON_PCI0) {
     143     bus-=BSP_MAX_PCI_BUS_ON_PCI0;
     144     n=1;
    142145  }
    143146
    144147  *val = 0xffffffff;
    145148  if ((offset&3)|| (offset & ~0xff)) return PCIBIOS_BAD_REGISTER_NUMBER;
    146 #if 0
    147   printk("addr %x, data %x, pack %x \n", config_addr,
    148     pci.pci_config_data,pciConfigPack(bus,dev,func,offset));
    149 #endif
    150   outl(pciConfigPack(bus,dev,func,offset),config_addr);
    151   *val = inl(config_data);
    152   return PCIBIOS_SUCCESSFUL;
    153 }
    154 
    155 static int direct_pci_write_config_byte(unsigned char bus, unsigned char dev,unsigned char func, unsigned char offset, unsigned char val)
    156 {
    157   volatile unsigned char *config_addr, *config_data;
    158 
    159   if (bus>= BSP_MAX_PCI_BUS_ON_PCI0) {
    160      bus-=BSP_MAX_PCI_BUS_ON_PCI0;
    161      config_addr = (volatile unsigned char*) PCI1_CONFIG_ADDR;
    162      config_data = (volatile unsigned char*) PCI1_CONFIG_DATA;
    163   }
    164   else {
    165      config_addr = pci.pci_config_addr;
    166      config_data = pci.pci_config_data;
     149
     150  out_be32(BSP_pci[n].pci_config_addr, pciConfigPack(bus,dev,func,offset));
     151  *val = in_le32(BSP_pci[n].pci_config_data);
     152  return PCIBIOS_SUCCESSFUL;
     153}
     154
     155static int indirect_pci_write_config_byte(unsigned char bus, unsigned char dev,unsigned char func, unsigned char offset, unsigned char val)
     156{
     157  int n=0;
     158
     159  if (bus>= BSP_MAX_PCI_BUS_ON_PCI0) {
     160     bus-=BSP_MAX_PCI_BUS_ON_PCI0;
     161     n=1;
    167162  }
    168163
    169164  if (offset & ~0xff) return PCIBIOS_BAD_REGISTER_NUMBER;
    170 #if 0
    171   printk("addr %x, data %x, pack %x \n", config_addr,
    172     config_data,pciConfigPack(bus,dev,func,offset));
    173 #endif
    174 
    175   outl(pciConfigPack(bus,dev,func,offset), config_addr);
    176   outb(val, config_data + (offset&3));
    177   return PCIBIOS_SUCCESSFUL;
    178 }
    179 
    180 static int direct_pci_write_config_word(unsigned char bus, unsigned char dev,unsigned char func, unsigned char offset, unsigned short val)
    181 {
    182   volatile unsigned char *config_addr, *config_data;
    183 
    184   if (bus>= BSP_MAX_PCI_BUS_ON_PCI0) {
    185      bus-=BSP_MAX_PCI_BUS_ON_PCI0;
    186      config_addr = (volatile unsigned char*) PCI1_CONFIG_ADDR;
    187      config_data = (volatile unsigned char*) PCI1_CONFIG_DATA;
    188   }
    189   else {
    190      config_addr = (volatile unsigned char*) pci.pci_config_addr;
    191      config_data = (volatile unsigned char*) pci.pci_config_data;
     165
     166  out_be32(BSP_pci[n].pci_config_addr, pciConfigPack(bus,dev,func,offset));
     167  out_8(BSP_pci[n].pci_config_data + (offset&3), val);
     168  return PCIBIOS_SUCCESSFUL;
     169}
     170
     171static int indirect_pci_write_config_word(unsigned char bus, unsigned char dev,unsigned char func, unsigned char offset, unsigned short val)
     172{
     173  int n=0;
     174
     175  if (bus>= BSP_MAX_PCI_BUS_ON_PCI0) {
     176     bus-=BSP_MAX_PCI_BUS_ON_PCI0;
     177     n=1;
    192178  }
    193179
    194180  if ((offset&1)|| (offset & ~0xff)) return PCIBIOS_BAD_REGISTER_NUMBER;
    195 #if 0
    196   printk("addr %x, data %x, pack %x \n", config_addr,
    197     config_data,pciConfigPack(bus,dev,func,offset));
    198 #endif
    199   outl(pciConfigPack(bus,dev,func,offset),config_addr);
    200   outw(val, config_data + (offset&3));
    201   return PCIBIOS_SUCCESSFUL;
    202 }
    203 
    204 static int direct_pci_write_config_dword(unsigned char bus,unsigned char dev,unsigned char func, unsigned char offset, unsigned int val)
    205 {
    206   volatile unsigned char *config_addr, *config_data;
    207 
    208   if (bus>= BSP_MAX_PCI_BUS_ON_PCI0) {
    209      bus-=BSP_MAX_PCI_BUS_ON_PCI0;
    210      config_addr = (volatile unsigned char *) PCI1_CONFIG_ADDR;
    211      config_data = (volatile unsigned char *) PCI1_CONFIG_DATA;
    212   }
    213   else {
    214      config_addr = (volatile unsigned char*) pci.pci_config_addr;
    215      config_data = (volatile unsigned char*) pci.pci_config_data;
     181
     182  out_be32(BSP_pci[n].pci_config_addr, pciConfigPack(bus,dev,func,offset));
     183  out_le16(BSP_pci[n].pci_config_data + (offset&3), val);
     184  return PCIBIOS_SUCCESSFUL;
     185}
     186
     187static int indirect_pci_write_config_dword(unsigned char bus,unsigned char dev,unsigned char func, unsigned char offset, unsigned int val)
     188{
     189  int n=0;
     190
     191  if (bus>= BSP_MAX_PCI_BUS_ON_PCI0) {
     192     bus-=BSP_MAX_PCI_BUS_ON_PCI0;
     193     n=1;
    216194  }
    217195
    218196  if ((offset&3)|| (offset & ~0xff)) return PCIBIOS_BAD_REGISTER_NUMBER;
    219 #if 0
    220   printk("addr %x, data %x, pack %x \n", config_addr,
    221     config_data,pciConfigPack(bus,dev,func,offset));
    222 #endif
    223   outl(pciConfigPack(bus,dev,func,offset),config_addr);
    224   outl(val,config_data);
    225   return PCIBIOS_SUCCESSFUL;
    226 }
    227 
    228 const pci_config_access_functions pci_direct_functions = {
    229         direct_pci_read_config_byte,
    230         direct_pci_read_config_word,
    231         direct_pci_read_config_dword,
    232         direct_pci_write_config_byte,
    233         direct_pci_write_config_word,
    234         direct_pci_write_config_dword
     197
     198  out_be32(BSP_pci[n].pci_config_addr, pciConfigPack(bus,dev,func,offset));
     199  out_le32(BSP_pci[n].pci_config_data, val);
     200  return PCIBIOS_SUCCESSFUL;
     201}
     202
     203const pci_config_access_functions pci_indirect_functions = {
     204        indirect_pci_read_config_byte,
     205        indirect_pci_read_config_word,
     206        indirect_pci_read_config_dword,
     207        indirect_pci_write_config_byte,
     208        indirect_pci_write_config_word,
     209        indirect_pci_write_config_dword
    235210};
    236211
    237212
    238 pci_config BSP_pci_configuration = {(volatile unsigned char*) PCI_CONFIG_ADDR,
    239                          (volatile unsigned char*)PCI_CONFIG_DATA,
    240                                     &pci_direct_functions};
     213pci_config BSP_pci_configuration = {
     214           (volatile unsigned char*) (GT64x60_PCI_CONFIG_ADDR),
     215           (volatile unsigned char*) (GT64x60_PCI_CONFIG_DATA),
     216           &pci_indirect_functions};
     217
     218DiscoveryChipVersion BSP_getDiscoveryChipVersion(void)
     219{
     220  return(BSP_sysControllerVersion);
     221}
     222
     223BSP_VMEchipTypes BSP_getVMEchipType(void)
     224{
     225  return(BSP_VMEinterface);
     226}
    241227
    242228/*
     
    249235{
    250236  int deviceFound;
    251   unsigned char ucBusNumber, ucSlotNumber, ucFnNumber, ucNumFuncs;
    252   unsigned int ulHeader;
    253   unsigned int pcidata, ulClass, ulDeviceID;
    254 
    255   pci_interface();
    256  
     237  unsigned char ucBusNumber, ucSlotNumber, ucFnNumber, ucNumFuncs, data8;
     238  uint32_t ulHeader, ulClass, ulDeviceID;
     239#if PCI_DEBUG
     240  uint32_t pcidata;
     241#endif
     242
    257243  /*
    258244   * Scan PCI0 and PCI1 buses
     
    280266      switch(ulDeviceID) {
    281267        case (PCI_VENDOR_ID_MARVELL+(PCI_DEVICE_ID_MARVELL_GT6426xAB<<16)):
     268          pci_read_config_byte(0,0,0,PCI_REVISION_ID, &data8);
     269          switch(data8) {
     270          case 0x10:
     271            BSP_sysControllerVersion = GT64260A;
    282272#if PCI_PRINT
    283           printk("Marvell GT6426xA/B hostbridge detected at bus%d slot%d\n",
     273            printk("Marvell GT64260A (Discovery I) hostbridge detected at bus%d slot%d\n",
    284274                 ucBusNumber,ucSlotNumber);
    285275#endif
     276            break;
     277          case 0x20:
     278            BSP_sysControllerVersion = GT64260B;
     279#if PCI_PRINT
     280            printk("Marvell GT64260B (Discovery I) hostbridge detected at bus%d slot%d\n",
     281                 ucBusNumber,ucSlotNumber);
     282#endif
     283            break;
     284          default:
     285            printk("Undefined revsion of GT64260 chip\n");
     286            break;
     287          }
    286288          break;
    287         case (PCI_VENDOR_ID_PLX2+(PCI_DEVICE_ID_PLX2_PCI6154_HB2<<16)):
    288 #if PCI_PRINT
    289           printk("PLX PCI6154 PCI-PCI bridge detected at bus%d slot%d\n",
    290                  ucBusNumber,ucSlotNumber);
    291 #endif
    292           break;
    293289        case PCI_VENDOR_ID_TUNDRA:
    294290#if PCI_PRINT
     
    297293#endif
    298294          break;
    299       case (PCI_VENDOR_ID_INTEL+(PCI_DEVICE_INTEL_82544EI_COPPER<<16)):
     295      case (PCI_VENDOR_ID_DEC+(PCI_DEVICE_ID_DEC_21150<<16)):
    300296#if PCI_PRINT
    301           printk("INTEL 82544EI COPPER network controller detected at bus%d slot%d\n",
    302                  ucBusNumber,ucSlotNumber);
    303 #endif
    304           break;
    305       case (PCI_VENDOR_ID_DEC+(PCI_DEVICE_ID_DEC_21150<<16)):
    306  #if PCI_PRINT
    307297          printk("DEC21150 PCI-PCI bridge detected at bus%d slot%d\n",
    308298                 ucBusNumber,ucSlotNumber);
     
    310300          break;
    311301       default :
     302#if PCI_PRINT
    312303          printk("BSP unlisted vendor, Bus%d Slot%d DeviceID 0x%x \n",
    313304             ucBusNumber,ucSlotNumber, ulDeviceID);
     305#endif
     306          /* Kate Feng : device not supported by BSP needs to remap the IRQ line on mvme5500/mvme6100 */
     307          pci_read_config_byte(ucBusNumber,ucSlotNumber,0,PCI_INTERRUPT_LINE,&data8);
     308          if (data8 < BSP_GPP_IRQ_LOWEST_OFFSET)  pci_write_config_byte(ucBusNumber,
     309             ucSlotNumber,0,PCI_INTERRUPT_LINE,BSP_GPP_IRQ_LOWEST_OFFSET+data8);
     310
    314311          break;
    315312      }
     
    404401
    405402      }
    406 
    407       pci_read_config_dword(ucBusNumber,
    408                                ucSlotNumber,
    409                                0,
    410                           PCI_COMMAND,
    411                           &pcidata);
    412 #if PCI_DEBUG
    413       printk("MOTLoad command staus 0x%x, ", pcidata);
    414 #endif
    415       /* Clear the error on the host bridge */
    416       if ( (ucBusNumber==0) && (ucSlotNumber==0))
    417         pcidata |= PCI_STATUS_CLRERR_MASK;
    418       /* Enable bus,I/O and memory master access. */
    419       pcidata |= (PCI_COMMAND_MASTER|PCI_COMMAND_IO|PCI_COMMAND_MEMORY);
    420       pci_write_config_dword(ucBusNumber,
    421                                ucSlotNumber,
    422                                0,
    423                           PCI_COMMAND,
    424                           pcidata);
    425 
    426       pci_read_config_dword(ucBusNumber,
    427                                ucSlotNumber,
    428                                0,
    429                           PCI_COMMAND,
    430                           &pcidata);
    431 #if PCI_DEBUG     
    432       printk("Now command/staus 0x%x\n", pcidata);
    433 #endif
    434403    }
    435404    if (deviceFound) ucMaxPCIBus++;
     
    439408         pci_bus_count(), numPCIDevs);
    440409#endif
     410  pci_interface();
    441411  return(0);
    442412}
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