Changeset cf599996 in rtems


Ignore:
Timestamp:
May 8, 2009, 6:22:51 PM (10 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.9
Children:
82948ea1
Parents:
ef3a82f
Message:

2009-05-08 Kate Feng <feng1@…>

PR1395/bsps

  • Updated the changes from RTEMS-4.8.0, which were made since Oct. 2007.
  • network/if_1GHz/if_wm.c: fixed some bugs in the 1GHz driver.
  • pci/pci_interface.c: + Enabled PCI "Read", "Read Line", and "Read Multiple" + Agressive Prefetch to improve the performance of the PCI based

applications (e.g. 1GHz NIC).

  • irq/BSP_irq.c : Replaced the irq/irq.c, and used GT_GPP_Value register to monitor the cause of the level sensitive interrupts. This unique solution solves various bugs in the 1GHz network drivers Fixed bugs in compute_pic_masks_from_prio()
  • pci/pci.c : Updated it to be consistent with the original pci.c
  • written by Eric Valette. There is no change in its function.
  • irq/irq_init.c : set defaultIrq->next_handler to be 0
  • for BSP_SHARED_HANDLER_SUPPORT.
Location:
c/src/lib/libbsp/powerpc/mvme5500
Files:
18 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/powerpc/mvme5500/ChangeLog

    ref3a82f rcf599996  
     12009-05-08      Kate Feng <feng1@bnl.gov>
     2
     3        PR1395/bsps
     4        * Updated the changes from RTEMS-4.8.0, which were made since Oct. 2007.
     5        * network/if_1GHz/if_wm.c: fixed some bugs in the 1GHz driver.
     6        * pci/pci_interface.c:
     7          + Enabled PCI "Read", "Read Line", and "Read Multiple"
     8          +  Agressive Prefetch to improve the performance of the PCI based
     9             applications (e.g. 1GHz NIC).
     10        * irq/BSP_irq.c : Replaced the irq/irq.c, and used GT_GPP_Value
     11        register to monitor the cause of the level sensitive interrupts.
     12        This unique solution solves various bugs in the 1GHz network drivers
     13        Fixed bugs in compute_pic_masks_from_prio()
     14        * pci/pci.c : Updated it to be consistent with the original pci.c
     15        * written by Eric Valette.  There is no change in its function.
     16        * irq/irq_init.c : set defaultIrq->next_handler to be 0
     17        * for BSP_SHARED_HANDLER_SUPPORT.
     18
    1192008-12-08      Ralf Corsépius <ralf.corsepius@rtems.org>
    220
  • c/src/lib/libbsp/powerpc/mvme5500/GT64260/VPD.h

    ref3a82f rcf599996  
    66 */
    77
    8 extern unsigned char ConfVPD_buff[200];
    9 
    108#define VPD_ENET0_OFFSET  0x3c
    119#define VPD_ENET1_OFFSET  0x45
  • c/src/lib/libbsp/powerpc/mvme5500/GT64260/gtreg.h

    ref3a82f rcf599996  
    191191#define GT_MPP_Control3                 0xf00c
    192192
    193 /* <skf> added */
     193/* <skf> added for GT64260 */
    194194#define GT_MPP_SerialPortMultiplex      0xf010
    195195
     
    790790#define TWSI_SFT_RST            0xc01c
    791791
    792 /* Interrupt Controller - Interrupt Controller Registers */
    793792/* Section 25.2 : Table 734 <skf> */
    794793
    795 #define GT_MAIN_INT_CAUSE_LO    0xc18 /* read Only */
    796 #define GT_MAIN_INT_CAUSE_HI   0xc68 /* read Only */
    797 #define GT_CPU_INT_MASK_LO      0xc1c
    798 #define GT_CPU_INT_MASK_HI      0xc6c
    799 #define GT_CPU_SEL_CAUSE        0xc70 /* read Only */
     794#define GT64260_MAIN_INT_CAUSE_LO       0xc18 /* read Only */
     795#define GT64260_MAIN_INT_CAUSE_HI       0xc68 /* read Only */
     796#define GT64260_CPU_INT_MASK_LO         0xc1c
     797#define GT64260_CPU_INT_MASK_HI         0xc6c
     798#define GT64260_CPU_SEL_CAUSE   0xc70 /* read Only */
    800799#define GT_PCI0_INT_MASK_LO     0xc24
    801800#define GT_PCI0_INT_MASK_HI     0xc64
  • c/src/lib/libbsp/powerpc/mvme5500/Makefile.am

    ref3a82f rcf599996  
    3333    ../../shared/bsppredriverhook.c startup/bspclean.c \
    3434    ../../shared/bsplibc.c ../../shared/bsppost.c \
    35     ../../shared/gnatinstallhandler.c startup/reboot.c
     35    ../../shared/gnatinstallhandler.c startup/reboot.c \
     36    ../../powerpc/shared/startup/probeMemEnd.c
     37
    3638pclock_SOURCES = ../../powerpc/shared/clock/p_clock.c
    3739
     
    4648
    4749include_bsp_HEADERS += irq/irq.h
    48 irq_SOURCES = irq/irq_init.c irq/irq.c
     50irq_SOURCES = irq/irq_init.c irq/BSP_irq.c
    4951
    5052nodist_include_HEADERS += ../../shared/tod.h
  • c/src/lib/libbsp/powerpc/mvme5500/README

    ref3a82f rcf599996  
    11#
    2 #  $Id: README,v 1.3.1  Shuchen Kate Feng, NSLS, BNL (08/27/07)
     2#  $Id: README,v 1.4.1  Shuchen Kate Feng, NSLS, BNL (03/16/2009)
    33#
    44
     
    88reference README.irq
    99
    10 The BSP is built and tested on the 4.7.1 and 4.7.99.2 CVS RTEMS release.
     10The BSP is built and tested on the RTEMS 4.9.1 release. The
     11PR1385 patch for c/src/lib/libbsp/powerpc/shared/irq/irq_asm.S
     12is not needed for the mvme5500 BSP because the PowerPC BSPs
     13use the shared exception framework in the RTEMS 4.9 release.
    1114
    1215I believe in valuable real-time programming, where technical neatness,
  • c/src/lib/libbsp/powerpc/mvme5500/README.booting

    ref3a82f rcf599996  
    1 README.booting: written by S. Kate Feng <feng1@bnl.gov>, Aug. 28, 2007
     1README.booting: written by S. Kate Feng <feng1@bnl.gov>, March 16, 2009
    22
    3 The bootloader is adapted from Till Straumann's Generic Mini-loader,
    4 which he wrote originally for the SVGM powerpc board.
    5 The BSP is built and tested on the 4.7 CVS RTEMS release.
     3The BSP is built and tested on the RTEMS 4.9.1 release. The
     4PR1385 patch for c/src/lib/libbsp/powerpc/shared/irq/irq_asm.S
     5is not needed for the mvme5500 BSP because the PowerPC BSPs
     6use the shared exception framework in the RTEMS 4.9 release.
    67
    78Booting requirement :
     
    1213   (Note : EPICS needs a NTP server).
    1314 
    14 2) Please copy the prebuilt RTEMS binary (e.g. misc/rtems5500-cexp.bin)
    15    and perhaps others (e.g. misc/st.sys) to the /tftpboot/epics/hostname/bin/
    16    directory or the TFTPBOOT one you specified in the 'tftpGet'
    17    command of the boot script (as shown in the following example).
    18 
    19 3) Example of the boot script setup carried out on the MOTLoad
     152) Example of the boot script setup carried out on the MOTLoad
    2016   command line :
    2117
     
    3329        sxx.xx.xx.xx is the server IP address)
    3430
    35 4) Other reference web sites for mvme5500 BSP:
    36 http://lansce.lanl.gov/EPICS/presentations/KateFeng%20RTEMS-mvme55001.ppt
     313) Other reference web sites for mvme5500 BSP:
    3732http://www.nsls.bnl.gov/facility/expsys/software/EPICS/
    38 http://www.nsls.bnl.gov/facility/expsys/software/EPICS/FAQ.txt
    3933
    40 5) When generating code (especially C++) for this system, one should
    41    use at least gcc-3.2 (preferrably a copy downloaded from the RTEMS
    42    site [snapshot area] )
    4334
    44 6) To reboot the RTEMS-MVME5500 (board reset), one can invoke the
     354) To reboot the RTEMS-MVME5500 (board reset), one can invoke the
    4536   rtemsReboot() command at Cexp> prompt.
    4637 
    47 7) Please reference http://www.slac.stanford.edu/~strauman/rtems
    48 for the source code and installation guidance of cexp, GeSys and
    49 other useful utilities such as telnet, nfs, and so on.
    50 
    51 8) To get started with RTEMS/EPICS and to build development
     385) To get started with RTEMS/EPICS and to build development
    5239tools and BSP, I would recommend one to reference
    5340http://www.aps.anl.gov/epics/base/RTEMS/tutorial/
  • c/src/lib/libbsp/powerpc/mvme5500/include/bsp.h

    ref3a82f rcf599996  
    88 *  http://www.rtems.com/license/LICENSE.
    99 *
    10  *  S. Kate Feng 2003-2007 : Modified it to support the mvme5500 BSP.
     10 *  (C) S. Kate Feng 2003-2007 : Modified it to support the mvme5500 BSP.
     11 *
    1112 *
    1213 */
     
    2324#include <bsp/vectors.h>
    2425
    25 #include <bsp/bspMvme5500.h>
     26/* Board type */
     27typedef enum {
     28        undefined = 0,
     29        MVME5500,
     30        MVME6100
     31} BSP_BoardTypes;
     32
     33BSP_BoardTypes BSP_getBoardType();
     34
     35/* Board type */
     36typedef enum {
     37        Undefined,
     38        UNIVERSE2,
     39        TSI148,
     40} BSP_VMEchipTypes;
     41
     42BSP_VMEchipTypes BSP_getVMEchipType();
     43
     44/* The version of Discovery system controller */
     45
     46typedef enum {
     47        notdefined,
     48        GT64260A,
     49        GT64260B,           
     50        MV64360,
     51} DiscoveryChipVersion;
     52
     53DiscoveryChipVersion BSP_getDiscoveryChipVersion();
     54
     55#define _256M           0x10000000
     56#define _512M           0x20000000
     57
     58#define GT64x60_REG_BASE        0xf1000000  /* Base of GT64260 Reg Space */
     59#define GT64x60_REG_SPACE_SIZE  0x10000     /* 64Kb Internal Reg Space */
     60
     61#define GT64x60_DEV1_BASE       0xf1100000  /* Device bank1(chip select 1) base
     62                                             */
     63#define GT64260_DEV1_SIZE       0x00100000 /* Device bank size */
    2664
    2765/* fundamental addresses for this BSP (PREPxxx are from libcpu/io.h) */
    28 #define _IO_BASE GT64260_REG_BASE
     66#define _IO_BASE GT64x60_REG_BASE
     67
     68#define BSP_NVRAM_BASE_ADDR     0xf1110000
     69
     70#define BSP_RTC_INTA_REG        0x7ff0
     71#define BSP_RTC_SECOND          0x7ff2 
     72#define BSP_RTC_MINUTE          0x7ff3
     73#define BSP_RTC_HOUR            0x7ff4 
     74#define BSP_RTC_DATE            0x7ff5
     75#define BSP_RTC_INTERRUPTS      0x7ff6
     76#define BSP_RTC_WATCHDOG        0x7ff7
    2977
    3078/* PCI0 Domain I/O space */
     
    70118
    71119#define CONFIGURE_NUMBER_OF_TERMIOS_PORTS 2
     120#define BSP_INTERRUPT_STACK_SIZE  (16 * 1024) /* <skf> 2/09 wants it to be adjustable by BSP */
    72121
    73122/* uart.c uses out_8 instead of outb  */
    74 #define BSP_UART_IOBASE_COM1    GT64260_DEV1_BASE + 0x20000
    75 #define BSP_UART_IOBASE_COM2    GT64260_DEV1_BASE + 0x21000
     123#define BSP_UART_IOBASE_COM1    GT64x60_DEV1_BASE + 0x20000
     124#define BSP_UART_IOBASE_COM2    GT64x60_DEV1_BASE + 0x21000
    76125
    77126#define BSP_CONSOLE_PORT                BSP_UART_COM1  /* console */
    78127#define BSP_UART_BAUD_BASE              115200
    79128
    80 /*
    81  * Vital Board data Start using DATA RESIDUAL
    82  */
    83129/*
    84130 * Total memory using RESIDUAL DATA
     
    101147  ((unsigned long long) ((((unsigned long long)BSP_time_base_divisor) * 1000000ULL) /((unsigned long long) BSP_bus_frequency)) * ((unsigned long long) (_value)))
    102148
     149extern rtems_configuration_table  BSP_Configuration;
    103150extern void BSP_panic(char *s);
    104151extern void bsp_reset(void);
     
    119166#endif
    120167
    121 extern int
    122 RTEMS_BSP_NETWORK_DRIVER_ATTACH(/* struct rtems_bsdnet_ifconfig * */);
     168extern int RTEMS_BSP_NETWORK_DRIVER_ATTACH();
    123169
    124170/*
     
    127173#define BSP_ZERO_WORKSPACE_AUTOMATICALLY TRUE
    128174
    129 /* As per Linux, This should be in the ppc/system.h */
     175#define gccMemBar() RTEMS_COMPILER_MEMORY_BARRIER()
    130176
     177static inline void lwmemBar()
     178{
     179    asm volatile("lwsync":::"memory");
     180}
     181
     182static inline void io_flush()
     183{
     184    asm volatile("isync":::"memory");
     185}
    131186static inline void memBar()
    132187{
    133188    asm volatile("sync":::"memory");
    134189}
    135 
    136190static inline void ioBar()
    137191{
    138     asm volatile("eieio");
     192    asm volatile("eieio":::"memory");
    139193}
    140194
  • c/src/lib/libbsp/powerpc/mvme5500/irq/irq_init.c

    ref3a82f rcf599996  
    3737static rtems_irq_connect_data           rtemsIrq[BSP_IRQ_NUMBER];
    3838static rtems_irq_global_settings        initial_config;
     39
     40#ifdef BSP_SHARED_HANDLER_SUPPORT
     41static rtems_irq_connect_data           defaultIrq = {
     42  /* vectorIdex,  hdl       ,handle  , on       , off      , isOn      ,next_handler, */
     43  0,              nop_func  , NULL   , nop_func , nop_func , not_connected, 0
     44};
     45#else
    3946static rtems_irq_connect_data           defaultIrq = {
    4047  /* vectorIdex,         hdl      , handle      , on            , off           , isOn */
    4148  0,                     nop_func  , NULL       , nop_func      , nop_func      , not_connected
    4249};
     50#endif
    4351
    4452rtems_irq_prio BSPirqPrioTable[BSP_PIC_IRQ_NUMBER]={
     
    136144  printk("Done setup irq mngt configuration\n");
    137145#endif
    138  
    139   /* I don't really understand why all sources are enable here... (T.S) */
    140   for (i= BSP_MAIN_GPP7_0_IRQ; i <= BSP_MAIN_GPP31_24_IRQ; i++)
    141       BSP_enable_pic_irq(i);
    142 
    143   rtems_interrupt_enable(l);
    144146
    145147#ifdef TRACE_IRQ_INIT 
  • c/src/lib/libbsp/powerpc/mvme5500/network/if_100MHz/GT64260eth.c

    ref3a82f rcf599996  
    88 * netBSD : Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc.
    99 * Marvell : NDA document for the discovery system controller
    10  * The author referenced two RTEMS network drivers of other NICs.
    11  * rtems : 1) dec21140.c, a network driver for for TULIP based Ethernet Controller
    12  *            (C) 1999 Emmanuel Raguet. raguet@crf.canon.fr
    13  *
    14  *         2) yellowfin.c, a network driver for the SVGM5 BSP.
    15  *           Stanford Linear Accelerator Center, Till Straumann
    1610 *
    1711 * Some notes from the author, S. Kate Feng :
     
    367361 
    368362  printk("\nEthernet driver name %s unit %d \n",name, unit);
    369   printk("(c) 2004, Brookhaven National Lab. <feng1@bnl.gov> (RTEMS/mvme5500 port)\n");
    370 
     363  printk("RTEMS-mvme5500 BSP Copyright (c) 2004, Brookhaven National Lab., Shuchen Kate Feng \n");
    371364  /* Make certain elements e.g. descriptor lists are aligned. */
    372365  softc_mem = rtems_bsdnet_malloc(sizeof(*sc) + SOFTC_ALIGN, M_FREE, M_NOWAIT);
     
    394387    printk("Read EEPROM ");
    395388     for (i = 0; i < 6; i++)
    396        hwaddr[i] = ConfVPD_buff[VPD_ENET0_OFFSET+i];
     389       hwaddr[i] = ReadConfVPD_buff(VPD_ENET0_OFFSET+i);
    397390  }
    398391
     
    11381131}
    11391132
    1140 /* TOCHECK : Should it be about rx or tx ? */
    11411133static void GTeth_ifchange(struct GTeth_softc *sc)
    11421134{
     
    14461438}
    14471439
     1440#ifdef GT64260eth_DEBUG
    14481441static void GT64260eth_error(struct GTeth_softc *sc)
    14491442{
     
    14751468  sc->intr_err_ptr1 %= INTR_ERR_SIZE;   /* Till Straumann */
    14761469}
    1477 
     1470#endif
    14781471
    14791472/* The daemon does all of the work; RX, TX and cleaning up buffers/descriptors */
     
    15491542
    15501543       /* Log errors and other uncommon events. */
     1544#ifdef GT64260eth_DEBUG
    15511545       if (events & ERR_EVENT) GT64260eth_error(sc);
     1546#endif
    15521547  } /* end for(;;) { rtems_bsdnet_event_receive() .....*/
    15531548
  • c/src/lib/libbsp/powerpc/mvme5500/network/if_1GHz/if_wm.c

    ref3a82f rcf599996  
    11/*
    22 * Copyright (c) 2004,2005 RTEMS/Mvme5500 port by S. Kate Feng <feng1@bnl.gov>
     3 *      under the Deaprtment of Energy contract DE-AC02-98CH10886
    34 *      Brookhaven National Laboratory, All rights reserved
    45 *
     
    2627 *    to WB region", MII mode (PHY) instead of TBI mode.
    2728 * 6) We currently only use 32-bit (instead of 64-bit) DMA addressing.
    28  * 7) Support for checksum offloading and TCP segmentation offload will
    29  *    be available for releasing in 2008, upon request, if I still believe.
     29 * 7) Implementation for Jumbo Frame and TCP checksum is not completed yet.
    3030 *   
    3131 */
     
    3434
    3535#define INET
     36
     37/*#define RTEMS_ETHERMTU_JUMBO*/
    3638
    3739#include <rtems.h>
    3840#include <rtems/bspIo.h>      /* printk */
     41
    3942#include <stdio.h>            /* printf for statistics */
    4043#include <string.h>
     
    6568#include <netinet/in.h>
    6669#include <netinet/if_ether.h>
     70#include <net/ethernet.h>
    6771
    6872#ifdef INET
     
    7680#define WMREG_RADV      0x282c  /* Receive Interrupt Absolute Delay Timer */
    7781
    78 /*#define CKSUM_OFFLOAD*/
    79 
    8082#define ETHERTYPE_FLOWCONTROL   0x8808  /* 802.3x flow control packet */
    8183
    82 #define i82544EI_TASK_NAME "IGHZ"
     84#define i82544EI_TASK_NAME "IGHz"
    8385#define SOFTC_ALIGN        4095
    8486
    85 #define INTR_ERR_SIZE        16
     87#define IF_ERR_BUFSZE        16
    8688
    8789/*#define WM_DEBUG*/
     
    9193#define WM_DEBUG_RX             0x04
    9294#define WM_DEBUG_GMII           0x08
    93 int     wm_debug = WM_DEBUG_TX|WM_DEBUG_RX|WM_DEBUG_LINK;
     95static int      wm_debug = WM_DEBUG_TX|WM_DEBUG_RX|WM_DEBUG_LINK; /* May 7, 2009 */
    9496
    9597#define DPRINTF(x, y)   if (wm_debug & (x)) printk y
     
    110112#define ALL_EVENTS (KILL_EVENT|START_TRANSMIT_EVENT|RX_EVENT|TX_EVENT|ERR_EVENT|INIT_EVENT)
    111113
    112 
    113 #define NTXDESC                 128
     114/* <skf> used 64 in 4.8.0, TOD; try 4096 */
     115#define NTXDESC                 256
    114116#define NTXDESC_MASK            (NTXDESC - 1)
    115117#define WM_NEXTTX(x)            (((x) + 1) & NTXDESC_MASK)
    116118
    117 #define NRXDESC                 64
     119#define NRXDESC                 256
    118120#define NRXDESC_MASK            (NRXDESC - 1)
    119121#define WM_NEXTRX(x)            (((x) + 1) & NRXDESC_MASK)
     
    124126#define WM_CDRXOFF(x)   WM_CDOFF(sc_rxdescs[(x)])
    125127
    126 #define TXQ_HiLmt_OFF 64
     128#define TXQ_HiLmt_OFF 32
    127129
    128130static uint32_t TxDescCmd;
     131static unsigned BSP_1GHz_membase;
    129132
    130133/*
     
    137140        struct mbuf *rxs_mbuf[NRXDESC];        /* receive buffer memory */
    138141        struct wm_softc *next_module;
    139         volatile unsigned int intr_errsts[INTR_ERR_SIZE]; /* intr_status */
    140         unsigned int intr_err_ptr1;     /* ptr used in i82544EI_error() */
    141         unsigned int intr_err_ptr2;     /* ptr used in ISR */
     142        volatile unsigned int if_errsts[IF_ERR_BUFSZE]; /* intr_status */
     143        unsigned int if_err_ptr1;     /* ptr used in i82544EI_error() */
     144        unsigned int if_err_ptr2;     /* ptr used in ISR */
    142145        int txs_firstdesc;              /* first descriptor in packet */
    143146        int txs_lastdesc;               /* last descriptor in packet */
     
    169172        int     sc_rxdiscard;
    170173        int     sc_rxlen;
     174
    171175        uint32_t sc_ctrl;               /* prototype CTRL register */
    172 #if 0
    173176        uint32_t sc_ctrl_ext;           /* prototype CTRL_EXT register */
    174 #endif
     177
    175178        uint32_t sc_icr;                /* prototype interrupt bits */
    176179        uint32_t sc_tctl;               /* prototype TCTL register */
     
    178181        uint32_t sc_tipg;               /* prototype TIPG register */
    179182        uint32_t sc_fcrtl;              /* prototype FCRTL register */
     183        uint32_t sc_pba;                /* prototype PBA register */
    180184
    181185        int sc_mchash_type;             /* multicast filter offset */
     
    185189          volatile unsigned long     rxInterrupts;
    186190          volatile unsigned long     txInterrupts;
    187           unsigned long     txMultiBuffPacket;
    188           unsigned long     txMultiMaxLen;
    189           unsigned long     txSinglMaxLen;
    190           unsigned long     txMultiMaxLoop;
    191           unsigned long     txBuffMaxLen;
    192191          unsigned long     linkInterrupts;
    193192          unsigned long     length_errors;
     
    225224
    226225static void i82544EI_ifstart(struct ifnet *ifp);
    227 static int  wm_ioctl(struct ifnet *ifp, u_long cmd,uint32_t data);
     226static int  wm_ioctl(struct ifnet *ifp, ioctl_command_t cmd,caddr_t data);
    228227static void i82544EI_ifinit(void *arg);
    229228static void wm_stop(struct ifnet *ifp, int disable);
     229static void wm_gmii_mediainit(struct wm_softc *sc);
    230230
    231231static void wm_rxdrain(struct wm_softc *sc);
     
    234234static void i82544EI_daemon(void *arg);
    235235static void wm_set_filter(struct wm_softc *sc);
    236 
    237 static void i82544EI_isr(void);
     236static void i82544EI_rx(struct wm_softc *sc);
     237static void i82544EI_isr(rtems_irq_hdl_param handle);
    238238static void i82544EI_sendpacket(struct wm_softc *sc, struct mbuf *m);
    239 extern int pci_mem_find(int b, int d, int f, int reg, unsigned *basep,unsigned *sizep);
    240 extern int pci_io_find(int b, int d, int f, int reg,unsigned *basep,unsigned *sizep);
    241 extern int pci_get_capability(int b, int d, int f, int capid,int *offset,uint32_t *value);
    242 extern char * ether_sprintf1(void);
     239extern int  pci_mem_find(), pci_io_find(), pci_get_capability();
    243240
    244241static void i82544EI_irq_on(const rtems_irq_connect_data *irq)
     
    272269        BSP_GPP_82544_IRQ,
    273270        (rtems_irq_hdl) i82544EI_isr,
     271        (rtems_irq_hdl_param) NULL,
    274272        (rtems_irq_enable) i82544EI_irq_on,
    275273        (rtems_irq_disable) i82544EI_irq_off,
     
    291289  unit = rtems_bsdnet_parse_driver_name(config, &name);
    292290  if (unit < 0) return 0;
    293  
    294   printk("\nEthernet driver name %s unit %d \n",name, unit);
    295   printk("Copyright (c) 2004,2005 S. Kate Feng <feng1@bnl.gov> (RTEMS/mvme5500 port)\n");
     291
     292  if ( !strncmp((const char *)name,"autoz",5))
     293     memcpy(name,"gtGHz",5);
     294         
     295  printk("\nAttaching MVME5500 1GHz NIC%d\n", unit);
     296  printk("RTEMS-mvme5500 BSP Copyright (c) 2004,2005,2008, Brookhaven National Lab., Shuchen Kate Feng \n");
    296297
    297298  /* Make sure certain elements e.g. descriptor lists are aligned.*/
     
    311312    rtems_panic("i82544EI device ID not found\n");
    312313
    313 #if WM_DEBUG
     314#ifdef WM_DEBUG
    314315  printk("82544EI:b%d, d%d, f%d\n", b, d,f);
    315316#endif
     
    319320     rtems_panic("i82544EI: unable to map memory space\n");
    320321
     322#ifdef WM_DEBUG
     323  printk("Memory base addr 0x%x\n", sc->sc_membase);
     324#endif
     325  BSP_1GHz_membase= sc->sc_membase;
     326
    321327#ifdef WM_DEBUG
    322328  printk("Memory base addr 0x%x\n", sc->sc_membase);
     
    325331
    326332
    327   sc->sc_ctrl |=CSR_READ(sc,WMREG_CTRL); 
     333  sc->sc_ctrl=CSR_READ(sc,WMREG_CTRL); 
    328334  /*
    329335   * Determine a few things about the bus we're connected to.
     
    363369  enaddr[5] = myea[2] >> 8;
    364370
    365 
    366371  memcpy(sc->arpcom.ac_enaddr, enaddr, ETHER_ADDR_LEN);
    367372#ifdef WM_DEBUG
    368373  printk("%s: Ethernet address %s\n", sc->dv_xname,
    369             ether_sprintf1(enaddr));
     374            ether_sprintf(enaddr));
    370375#endif
    371376
     
    397402  CSR_WRITE(sc,WMREG_CTRL_EXT, sc->sc_ctrl_ext);
    398403#endif
     404
     405  /*
     406   * Determine if we're TBI or GMII mode, and initialize the
     407   * media structures accordingly.
     408   */
     409  if ((CSR_READ(sc, WMREG_STATUS) & STATUS_TBIMODE) != 0) {
     410    /* 1000BASE-X : fiber  (TBI mode)
     411       wm_tbi_mediainit(sc); */
     412  } else {   /* 1000BASE-T : copper (internal PHY mode), for the mvme5500 */
     413           wm_gmii_mediainit(sc);
     414  } 
    399415
    400416  ifp = &sc->arpcom.ac_if;
     
    404420  ifp->if_softc = sc;
    405421  ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
     422#ifdef RTEMS_ETHERMTU_JUMBO
     423  sc->arpcom.ec_capabilities |= ETHERCAP_JUMBO_MTU;
     424  ifp->if_mtu = config->mtu ? config->mtu : ETHERMTU_JUMBO;
     425#else
    406426  ifp->if_mtu = config->mtu ? config->mtu : ETHERMTU;
     427#endif
     428#ifdef RTEMS_CKSUM_OFFLOAD
     429  /* < skf> The following is really not related to jumbo frame
     430  sc->arpcom.ec_capabilities |= ETHERCAP_VLAN_MTU;*/
     431  ifp->if_capabilities |= IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx |
     432                    IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx |
     433                    IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx |
     434                    IFCAP_CSUM_TCPv6_Tx | IFCAP_CSUM_UDPv6_Tx |
     435                    IFCAP_TSOv4;  /* TCP segmentation offload. */
     436#endif
     437
    407438  ifp->if_ioctl = wm_ioctl;
    408439  ifp->if_start = i82544EI_ifstart;
     
    419450     rtems_panic("i82544EI: semaphore creation failed");
    420451
    421   sc->next_module = root_i82544EI_dev;
     452  i82544IrqData.handle= (rtems_irq_hdl_param) sc;
     453  /* sc->next_module = root_i82544EI_dev;*/
    422454  root_i82544EI_dev = sc;
    423455
     
    433465
    434466/*
     467 * wm_reset:
     468 *
     469 *      Reset the i82544 chip.
     470 */
     471static void wm_reset(struct wm_softc *sc)
     472{
     473  int i;
     474
     475 /* Packet Buffer Allocation (PBA)
     476  * Writing PBA sets the receive portion of the buffer.
     477  * the remainder is used for the transmit buffer.
     478  *
     479  * 82544 has a Packet Buffer of 64K.
     480  * Default allocation : PBA=40K for Rx, leaving 24K for Tx.
     481  * Default for jumbo: PBA=48K for Rx, leaving 16K for Tx.
     482  */ 
     483  sc->sc_pba = sc->arpcom.ac_if.if_mtu > 8192 ? PBA_40K : PBA_48K;
     484  CSR_WRITE(sc, WMREG_PBA, sc->sc_pba);
     485
     486  /* device reset */
     487  CSR_WRITE(sc, WMREG_CTRL, CTRL_RST);
     488  rtems_bsp_delay(10000);
     489
     490  for (i = 0; i < 1000; i++) {
     491      if ((CSR_READ(sc, WMREG_CTRL) & CTRL_RST) == 0)
     492        break;
     493      rtems_bsp_delay(20);
     494  }
     495  if (CSR_READ(sc, WMREG_CTRL) & CTRL_RST)
     496      printk("Intel 82544 1GHz reset failed to complete\n");
     497
     498  sc->sc_ctrl_ext = CSR_READ(sc,WMREG_CTRL_EXT);
     499  sc->sc_ctrl_ext |= CTRL_EXT_EE_RST;
     500  CSR_WRITE(sc, WMREG_CTRL_EXT, sc->sc_ctrl_ext); 
     501  CSR_READ(sc, WMREG_STATUS);
     502  /* Wait for EEPROM reload */
     503  rtems_bsp_delay(2000);
     504  sc->sc_ctrl= CSR_READ(sc, WMREG_CTRL);
     505}
     506
     507/*
    435508 * i82544EI_ifstart:            [ifnet interface function]
    436509 *
     
    464537  struct ifnet *ifp = &sc->arpcom.ac_if;
    465538
    466   printf("       Rx Interrupts:%-8u\n", sc->stats.rxInterrupts);
     539  printf("    Ghost Interrupts:%-8lu\n", sc->stats.ghostInterrupts);
     540  printf("       Rx Interrupts:%-8lu\n", sc->stats.rxInterrupts);
    467541  printf("     Receive Packets:%-8u\n", CSR_READ(sc,WMREG_GPRC));
    468   printf("     Receive Overrun:%-8u\n", sc->stats.rxOvrRunInterrupts);
     542  printf("     Receive Overrun:%-8lu\n", sc->stats.rxOvrRunInterrupts);
    469543  printf("     Receive  errors:%-8u\n", CSR_READ(sc,WMREG_RXERRC));
    470   printf("   Rx sequence error:%-8u\n", sc->stats.rxSeqErr);
    471   printf("      Rx /C/ ordered:%-8u\n", sc->stats.rxC_ordered);
     544  printf("   Rx sequence error:%-8lu\n", sc->stats.rxSeqErr);
     545  printf("      Rx /C/ ordered:%-8lu\n", sc->stats.rxC_ordered);
    472546  printf("    Rx Length Errors:%-8u\n", CSR_READ(sc,WMREG_RLEC));
    473   printf("       Tx Interrupts:%-8u\n", sc->stats.txInterrupts);
    474 #if 0
    475   printf("Multi-BuffTx Packets:%-8u\n", sc->stats.txMultiBuffPacket);
    476   printf("Multi-BuffTx max len:%-8u\n", sc->stats.txMultiMaxLen);
    477   printf("SingleBuffTx max len:%-8u\n", sc->stats.txSinglMaxLen);
    478   printf("Multi-BuffTx maxloop:%-8u\n", sc->stats.txMultiMaxLoop);
    479   printf("Tx buffer max len   :%-8u\n", sc->stats.txBuffMaxLen);
    480 #endif
     547  printf("       Tx Interrupts:%-8lu\n", sc->stats.txInterrupts);
    481548  printf("   Transmitt Packets:%-8u\n", CSR_READ(sc,WMREG_GPTC));
    482   printf("   Transmitt  errors:%-8u\n", ifp->if_oerrors);
    483   printf("         Active Txqs:%-8u\n", sc->txq_nactive);
     549  printf("   Transmitt  errors:%-8lu\n", ifp->if_oerrors);
     550  printf("         Active Txqs:%-8lu\n", sc->txq_nactive);
    484551  printf("          collisions:%-8u\n", CSR_READ(sc,WMREG_COLC));
    485552  printf("          Crc Errors:%-8u\n", CSR_READ(sc,WMREG_CRCERRS));
    486   printf("  Link Status Change:%-8u\n", sc->stats.linkStatusChng);
     553  printf("  Link Status Change:%-8lu\n", sc->stats.linkStatusChng);
    487554}
    488555
     
    492559 *      Handle control requests from the operator.
    493560 */
    494 static int wm_ioctl(struct ifnet *ifp, u_long cmd,uint32_t data)
     561static int wm_ioctl(struct ifnet *ifp, ioctl_command_t cmd,caddr_t data)
    495562{
    496563  struct wm_softc *sc = ifp->if_softc;
     
    524591 *      Interrupt service routine.
    525592 */
    526 static void i82544EI_isr()
    527 {
    528   volatile struct wm_softc *sc = root_i82544EI_dev;
     593static void i82544EI_isr(rtems_irq_hdl_param handle)
     594{
     595  volatile struct wm_softc *sc = (struct wm_softc *) handle;
    529596  uint32_t icr;
    530597  rtems_event_set  events=0;
     
    550617  }
    551618  if (icr & ICR_RXSEQ) /* framing error */ {
    552      sc->intr_errsts[sc->intr_err_ptr2++]=icr;
    553      sc->intr_err_ptr2 %=INTR_ERR_SIZE; /* Till Straumann */
     619     sc->if_errsts[sc->if_err_ptr2++]=icr;
     620     if ( sc->if_err_ptr2 ==IF_ERR_BUFSZE) sc->if_err_ptr2=0;
    554621     events |= ERR_EVENT;
    555622     sc->stats.rxSeqErr++;
     
    609676         */
    610677        if ( ((y=(len+mtp->m_len)) > sizeof(union mcluster))) {
    611           printk(">2048, use next descriptor\n");
     678          printk(" >%d, use next descriptor\n", sizeof(union mcluster));
    612679          break;
    613680        }
     
    615682        pt += mtp->m_len;
    616683        len += mtp->m_len;
    617 #if 0
    618         sc->stats.txSinglMaxLen= MAX(mtp->m_len, sc->stats.txSinglMaxLen);
    619 #endif
    620684      } /* end for loop */
    621685      mdest->m_len=len;
     
    631695      else
    632696         rtems_panic("i8254EI : no more free descriptors");
    633 #if 0
    634       sc->stats.txMultiMaxLen= MAX(mdest->m_len, sc->stats.txMultiMaxLen);
    635       sc->stats.txMultiBuffPacket++;
    636 #endif
    637697    } /* end for while */
    638698    /* free old mbuf chain */
    639 #if 0
    640     sc->stats.txMultiMaxLoop=MAX(loop, sc->stats.txMultiMaxLoop);
    641 #endif
    642699    m_freem(m);
    643700    m=0;
     
    745802
    746803    status = sc->sc_rxdescs[i].wrx_status;
     804    if ((status & WRX_ST_DD) == 0)  break; /* descriptor not done */
     805
    747806    errors = sc->sc_rxdescs[i].wrx_errors;
    748807    len = le16toh(sc->sc_rxdescs[i].wrx_len);
    749808    m = sc->rxs_mbuf[i];
    750 
    751     if ((status & WRX_ST_DD) == 0)  break; /* descriptor not done */
    752 
    753809    if (sc->sc_rxdiscard) {
    754810       printk("RX: discarding contents of descriptor %d\n", i);
     
    822878  uint8_t cksumfields;
    823879
     880#if 0
     881  /* KATETODO : sc_align_tweak */
     882        /*
     883         * *_HDR_ALIGNED_P is constant 1 if __NO_STRICT_ALIGMENT is set.
     884         * There is a small but measurable benefit to avoiding the adjusment
     885         * of the descriptor so that the headers are aligned, for normal mtu,
     886         * on such platforms.  One possibility is that the DMA itself is
     887         * slightly more efficient if the front of the entire packet (instead
     888         * of the front of the headers) is aligned.
     889         *
     890         * Note we must always set align_tweak to 0 if we are using
     891         * jumbo frames.
     892         */
     893#ifdef __NO_STRICT_ALIGNMENT
     894        sc->sc_align_tweak = 0;
     895#else
     896        if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN) > (MCLBYTES - 2))
     897                sc->sc_align_tweak = 0;
     898        else
     899                sc->sc_align_tweak = 2;
     900#endif /* __NO_STRICT_ALIGNMENT */
     901#endif
     902
    824903  /* Cancel any pending I/O. */
    825904  wm_stop(ifp, 0);
    826905
     906  /* update statistics before reset */
     907  ifp->if_collisions += CSR_READ(sc, WMREG_COLC);
     908  ifp->if_ierrors += CSR_READ(sc, WMREG_RXERRC);
     909
     910  /* Reset the chip to a known state. */
     911  wm_reset(sc);
     912
    827913  /* Initialize the error buffer ring */
    828   sc->intr_err_ptr1=0;
    829   sc->intr_err_ptr2=0;
    830   for (i=0; i< INTR_ERR_SIZE; i++) sc->intr_errsts[i]=0;
     914  sc->if_err_ptr1=0;
     915  sc->if_err_ptr2=0;
     916  for (i=0; i< IF_ERR_BUFSZE; i++) sc->if_errsts[i]=0;
    831917
    832918  /* Initialize the transmit descriptor ring. */
    833   memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs));
     919  memset( (void *) sc->sc_txdescs, 0, sizeof(sc->sc_txdescs));
    834920  sc->txq_free = NTXDESC;
    835921  sc->txq_next = 0;
     
    850936  CSR_WRITE(sc,WMREG_TDH, 0);
    851937  CSR_WRITE(sc,WMREG_TDT, 0);
    852   CSR_WRITE(sc,WMREG_TIDV, 64 );
    853   CSR_WRITE(sc,WMREG_TADV, 128);
     938  CSR_WRITE(sc,WMREG_TIDV, 0 );
     939  /* CSR_WRITE(sc,WMREG_TADV, 128);  not for 82544 */
    854940
    855941  CSR_WRITE(sc,WMREG_TXDCTL, TXDCTL_PTHRESH(0) |
     
    865951   * this packet.
    866952   */
    867 #ifdef CKSUM_OFFLOAD
    868   if (m0->m_pkthdr.csum_flags &
    869      (M_CSUM_IPv4|M_CSUM_TCPv4|M_CSUM_UDPv4)) {
    870      if (wm_tx_cksum(sc, txs, &TxDescCmd,&cksumfields) != 0) {
     953#ifdef RTEMS_CKSUM_OFFLOAD
     954  if (m0->m_pkthdr.csum_flags & (M_CSUM_TSOv4|M_CSUM_TSOv6|
     955                    M_CSUM_IPv4|M_CSUM_TCPv4|M_CSUM_UDPv4|
     956                                 M_CSUM_TCPv6|M_CSUM_UDPv6)) {
     957     if (wm_tx_offload(sc, txs, &TxDescCmd,&cksumfields) != 0) {
    871958         /* Error message already displayed. */
    872959         continue;
     
    876963     TxDescCmd = 0;
    877964     cksumfields = 0;
    878 #ifdef CKSUM_OFFLOAD
     965#ifdef RTEMS_CKSUM_OFFLOAD
    879966  }
    880967#endif
     
    895982   * descriptor rings.
    896983   */
    897   memset(sc->sc_rxdescs, 0, sizeof(sc->sc_rxdescs));
     984  memset( (void *) sc->sc_rxdescs, 0, sizeof(sc->sc_rxdescs));
    898985  CSR_WRITE(sc,WMREG_RDBAH, 0);
    899986  CSR_WRITE(sc,WMREG_RDBAL, WM_CDRXADDR(sc));
     
    902989  CSR_WRITE(sc,WMREG_RDT, 0);
    903990  CSR_WRITE(sc,WMREG_RDTR, 0 |RDTR_FPD);
    904   CSR_WRITE(sc, WMREG_RADV, 256);
     991  /* CSR_WRITE(sc, WMREG_RADV, 256);  not for 82544.  */
    905992
    906993  for (i = 0; i < NRXDESC; i++) {
     
    9311018       CSR_WRITE(sc,WMREG_VFTA + (i << 2), 0);
    9321019
     1020#if 0
     1021  /* Use MOTLoad default
    9331022  /*
    9341023   * Set up flow-control parameters.
    935    *
    936    * XXX Values could probably stand some tuning.
    937    */
    938   CSR_WRITE(sc,WMREG_FCAL, FCAL_CONST);/*safe,even though MOTLOAD 0x00c28001 */
    939   CSR_WRITE(sc,WMREG_FCAH, FCAH_CONST);/*safe,even though MOTLOAD 0x00000100 */
    940   CSR_WRITE(sc,WMREG_FCT, ETHERTYPE_FLOWCONTROL);/*safe,even though MOTLoad 0x8808 */
     1024   */
     1025  CSR_WRITE(sc,WMREG_FCAL, FCAL_CONST);/* same as MOTLOAD 0x00c28001 */
     1026  CSR_WRITE(sc,WMREG_FCAH, FCAH_CONST);/* same as MOTLOAD 0x00000100 */
     1027  CSR_WRITE(sc,WMREG_FCT, ETHERTYPE_FLOWCONTROL);/* same as MOTLoad 0x8808 */
    9411028
    9421029
     
    9461033  CSR_WRITE(sc,WMREG_FCRTH, FCRTH_DFLT);
    9471034  CSR_WRITE(sc,WMREG_FCRTL, sc->sc_fcrtl);
    948   CSR_WRITE(sc,WMREG_FCTTV, FCTTV_DFLT);
     1035  /*KATETO   CSR_WRITE(sc,WMREG_FCTTV, FCTTV_DFLT);*/
     1036  CSR_WRITE(sc,WMREG_FCTTV, 0x100);
     1037#endif
    9491038
    9501039  sc->sc_ctrl &= ~CTRL_VME;
    951   /*sc->sc_ctrl |= CTRL_TFCE | CTRL_RFCE;*/
    952   /* enable Big Endian Mode for the powerPC
    953   sc->sc_ctrl |= CTRL_BEM;*/
     1040  /* TODO : not here.
     1041     Configures flow control settings after link is established
     1042     sc->sc_ctrl |= CTRL_TFCE | CTRL_RFCE; */
    9541043
    9551044  /* Write the control registers. */
     
    9591048#endif
    9601049
    961   /* MOTLoad : WMREG_RXCSUM (0x5000)= 0, no Rx checksum offloading */ 
     1050  /* MOTLoad : WMREG_RXCSUM (0x5000)= 0, no Rx checksum offloading */
     1051#ifdef RTEMS_CKSUM_OFFLOAD
     1052  /*
     1053   * Set up checksum offload parameters.
     1054   */
     1055   reg = CSR_READ(sc, WMREG_RXCSUM);
     1056   reg &= ~(RXCSUM_IPOFL | RXCSUM_IPV6OFL | RXCSUM_TUOFL);
     1057   if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx)
     1058            reg |= RXCSUM_IPOFL;
     1059   if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx))
     1060            reg |= RXCSUM_IPOFL | RXCSUM_TUOFL;
     1061   if (ifp->if_capenable & (IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx))
     1062            reg |= RXCSUM_IPV6OFL | RXCSUM_TUOFL;
     1063   CSR_WRITE(sc, WMREG_RXCSUM, reg);
     1064#endif
    9621065
    9631066  /*
     
    9651068   */
    9661069  CSR_WRITE(sc,WMREG_IMC, 0xffffffffU);
     1070
    9671071  /* Reading the WMREG_ICR clears the interrupt bits */
    9681072  CSR_READ(sc,WMREG_ICR);
     
    9881092   */
    9891093  sc->sc_tctl = TCTL_EN | TCTL_PSP | TCTL_CT(TX_COLLISION_THRESHOLD) |
    990             TCTL_COLD(TX_COLLISION_DISTANCE_FDX) | TCTL_RTLC; /*transmitter enable*/
     1094            TCTL_COLD(TX_COLLISION_DISTANCE_FDX) |
     1095            TCTL_RTLC /* retransmit on late collision */;
    9911096
    9921097  /*
     
    9961101   *
    9971102   * Only the i82544 has the ability to strip the incoming
    998    * CRC, so we don't enable that feature. (TODO)
     1103   * CRC (RCTL_SECRC).
    9991104   */
    10001105  sc->sc_mchash_type = 0;
    10011106  sc->sc_rctl = RCTL_EN | RCTL_LBM_NONE | RCTL_RDMTS_1_2 | RCTL_LPE |
    1002             RCTL_DPF | RCTL_MO(sc->sc_mchash_type);
    1003 
    1004   /* (MCLBYTES == 2048) */
    1005   sc->sc_rctl |= RCTL_2k;
     1107    RCTL_DPF | RCTL_MO(sc->sc_mchash_type)|RCTL_SECRC;
     1108
     1109  if (MCLBYTES == 2048) {
     1110     sc->sc_rctl |= RCTL_2k;
     1111  } else {
     1112        switch(MCLBYTES) {
     1113        case 4096:
     1114             sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_4k;
     1115             break;
     1116        case 8192:
     1117             sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_8k;
     1118             break;
     1119        case 16384:
     1120             sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_16k;
     1121             break;
     1122        default:
     1123             rtems_panic("wm_init: MCLBYTES %d unsupported",
     1124                    MCLBYTES);
     1125             break;
     1126        }
     1127  }
    10061128
    10071129#ifdef WM_DEBUG
     
    10211143}
    10221144
     1145void BSP_rdTIDV()
     1146{
     1147  printf("Reg TIDV: 0x%x\n", in_le32((volatile unsigned *) (BSP_1GHz_membase+WMREG_TIDV)));
     1148}
     1149void BSP_rdRDTR()
     1150{
     1151  printf("Reg RDTR: 0x%x\n", in_le32((volatile unsigned *) (BSP_1GHz_membase+WMREG_RDTR)));
     1152}
     1153
     1154void BSP_setTIDV(int val)
     1155{
     1156  out_le32((volatile unsigned *) (BSP_1GHz_membase+WMREG_TIDV), val);
     1157}
     1158
     1159void BSP_setRDTR(int val)
     1160{
     1161  out_le32((volatile unsigned *) (BSP_1GHz_membase+WMREG_RDTR), val);
     1162}
    10231163/*
    10241164 * i82544EI_ifinit:             [ifnet interface function]
     
    12361376}
    12371377
     1378#if 0
    12381379/*
    12391380 * wm_acquire_eeprom:
     
    12671408  return (0);
    12681409}
     1410#endif
    12691411
    12701412/*
     
    13711513  sc->sc_rctl &= ~(RCTL_BAM | RCTL_UPE | RCTL_MPE);
    13721514
    1373   /*  if (ifp->if_flags & IFF_BROADCAST)*/
     1515  if (ifp->if_flags & IFF_BROADCAST)
    13741516     sc->sc_rctl |= RCTL_BAM;
    13751517  if (ifp->if_flags & IFF_PROMISC) {
     
    14411583{
    14421584  struct ifnet          *ifp = &sc->arpcom.ac_if;
    1443   unsigned long         intr_status= sc->intr_errsts[sc->intr_err_ptr1++];
     1585  unsigned long         intr_status= sc->if_errsts[sc->if_err_ptr1];
    14441586
    14451587  /* read and reset the status; because this is written
    14461588   * by the ISR, we must disable interrupts here
    14471589   */
    1448   sc->intr_err_ptr1 %=INTR_ERR_SIZE; /* Till Straumann */
    14491590  if (intr_status) {
    14501591    printk("Error %s%d:", ifp->if_name, ifp->if_unit);
     
    14561597  else
    14571598    printk("%s%d: Ghost interrupt ?\n",ifp->if_name,ifp->if_unit);
     1599  sc->if_errsts[sc->if_err_ptr1]=0; 
     1600  if ((++sc->if_err_ptr1)==IF_ERR_BUFSZE) sc->if_err_ptr1=0; /* Till Straumann */
    14581601}
    14591602
     
    14961639     if (KILL_EVENT & events)  break;
    14971640
    1498      if (events & RX_EVENT)  i82544EI_rx(sc);
     1641     if (events & RX_EVENT)  i82544EI_rx(sc); /* in ISR instead */
    14991642
    15001643     /* clean up and try sending packets */
     
    15041647        while (sc->txq_free>0) {
    15051648           if (sc->txq_free>TXQ_HiLmt_OFF) {
     1649              m=0;
    15061650              IF_DEQUEUE(&ifp->if_snd,m);
    15071651              if (m==0) break;
     
    15121656              break;
    15131657           }
    1514            if (events & RX_EVENT)  i82544EI_rx(sc);
    15151658        }
    15161659         /* we leave this loop
     
    15201663          *    returned 0
    15211664          */
    1522      } while (m && sc->txq_free);
     1665     } while (m);
    15231666
    15241667     ifp->if_flags &= ~IFF_OACTIVE;
     
    15571700  rtems_task_delete(RTEMS_SELF);
    15581701}
     1702
     1703/*
     1704 * wm_gmii_reset:
     1705 *
     1706 *      Reset the PHY.
     1707 */
     1708static void wm_gmii_reset(struct wm_softc *sc)
     1709{
     1710
     1711  CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl | CTRL_PHY_RESET);
     1712  rtems_bsp_delay(20000);
     1713
     1714  CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
     1715  rtems_bsp_delay(20000);
     1716
     1717}
     1718
     1719/*
     1720 * wm_gmii_mediainit:
     1721 *
     1722 *      Initialize media for use on 1000BASE-T devices.
     1723 */
     1724static void wm_gmii_mediainit(struct wm_softc *sc)
     1725{
     1726  /*  struct ifnet *ifp = &sc->arpcom.ac_if;*/
     1727
     1728  /* We have MII. */
     1729  sc->sc_flags |= WM_F_HAS_MII;
     1730
     1731#if 1
     1732  /* <skf> May 2009 : The value that should be programmed into IPGT is 10 */
     1733  sc->sc_tipg = TIPG_IPGT(10)+TIPG_IPGR1(8)+TIPG_IPGR2(6);
     1734#else
     1735  sc->sc_tipg = TIPG_1000T_DFLT; /* 0x602008 */
     1736#endif
     1737
     1738  /*
     1739   * Let the chip set speed/duplex on its own based on
     1740   * signals from the PHY.
     1741   * XXXbouyer - I'm not sure this is right for the 80003,
     1742   * the em driver only sets CTRL_SLU here - but it seems to work.
     1743   */
     1744  sc->sc_ctrl |= CTRL_SLU;
     1745  CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
     1746
     1747  wm_gmii_reset(sc);
     1748
     1749#if 0
     1750  /* Initialize our media structures and probe the GMII. */
     1751  sc->sc_mii.mii_ifp = ifp;
     1752
     1753  sc->sc_mii.mii_readreg = wm_gmii_i82544_readreg;
     1754  sc->sc_mii.mii_writereg = wm_gmii_i82544_writereg;
     1755  sc->sc_mii.mii_statchg = wm_gmii_statchg;
     1756
     1757  ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, wm_gmii_mediachange,
     1758            wm_gmii_mediastatus);
     1759
     1760  mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY,
     1761            MII_OFFSET_ANY, MIIF_DOPAUSE);
     1762  if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) {
     1763     ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL);
     1764     ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE);
     1765  } else
     1766      ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO);
     1767#endif
     1768}
  • c/src/lib/libbsp/powerpc/mvme5500/network/if_1GHz/if_wmreg.h

    ref3a82f rcf599996  
    66 *
    77 * Written by Jason R. Thorpe for Wasabi Systems, Inc.
     8 * Some are added by Shuchen Kate Feng <feng1@bnl.gov>,
     9 *            NSLS, Brookhaven National Laboratory. All rights reserved.
     10 *            under the Deaprtment of Energy contract DE-AC02-98CH10886
    811 *
    912 * Redistribution and use in source and binary forms, with or without
     
    5760 * and there must be an even multiple of 8 descriptors in the ring.
    5861 */
    59 typedef struct wiseman_rxdesc {
     62typedef volatile struct wiseman_rxdesc {
    6063        wiseman_addr_t  wrx_addr;       /* buffer address */
    6164
     
    104107        uint16_t wtxu_vlan;             /* VLAN info */
    105108} __attribute__((__packed__)) wiseman_txfields_t;
    106 typedef struct wiseman_txdesc {
     109typedef volatile struct wiseman_txdesc {
    107110        wiseman_addr_t  wtx_addr;       /* buffer address */
    108111        uint32_t        wtx_cmdlen;     /* command and length */
  • c/src/lib/libbsp/powerpc/mvme5500/network/if_1GHz/pcireg.h

    ref3a82f rcf599996  
    55 *     Christopher G. Demetriou.  All rights reserved.
    66 * Copyright (c) 1994, 1996 Charles M. Hannum.  All rights reserved.
     7 * Copyright (C) 2007 Brookhaven National Laboratory, Shuchen Kate Feng
    78 *
    89 * Redistribution and use in source and binary forms, with or without
     
    3132 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
    3233 */
     34#include <bsp.h>
    3335
    3436/*
     
    306308
    307309#define PCI_MAPREG_IO_ADDR(mr)                                          \
    308             ((mr) & PCI_MAPREG_IO_ADDR_MASK)
     310            ((mr+PCI0_IO_BASE) & PCI_MAPREG_IO_ADDR_MASK)
    309311#define PCI_MAPREG_IO_SIZE(mr)                                          \
    310312            (PCI_MAPREG_IO_ADDR(mr) & -PCI_MAPREG_IO_ADDR(mr))
  • c/src/lib/libbsp/powerpc/mvme5500/pci/pci.c

    ref3a82f rcf599996  
    1414 *  http://www.rtems.com/rtems/license.html.
    1515 *
    16  *  Copyright 2004, Brookhaven National Laboratory and
    17  *                  Shuchen K. Feng, <feng1@bnl.gov>, 2004
    18  *   - modified and added support for MVME5500 board
    19  *   - added 2nd PCI support for the mvme5500/GT64260 PCI bridge
    20  *   - added bus support for the expansion of PMCSpan, thanks to
    21  *     Peter Dufault (dufault@hda.com) for inputs.
    22  *
    23  * $Id$
     16 *  pci.c,v 1.2 2002/05/14 17:10:16 joel Exp
     17 *
     18 *  Copyright 2004, 2008 Brookhaven National Laboratory and
     19 *                  Shuchen K. Feng, <feng1@bnl.gov>
     20 *   
     21 *   - to be consistent with the original pci.c written by Eric Valette
     22 *   - added 2nd PCI support for discovery based PCI bridge (e.g. mvme5500/mvme6100)
     23 *   - added bus support for the expansion of PMCSpan as per request by Peter
    2424 */
    2525#define PCI_MAIN
     
    2828#include <rtems/bspIo.h>            /* printk */
    2929
     30#include <bsp/irq.h>
    3031#include <bsp/pci.h>
    3132#include <bsp/gtreg.h>
    3233#include <bsp/gtpcireg.h>
     34#include <bsp.h>
    3335
    3436#include <stdio.h>
     
    3638
    3739#define PCI_DEBUG 0
    38 #define PCI_PRINT 0
     40#define PCI_PRINT 1
    3941
    4042/* allow for overriding these definitions */
     
    5759#define HOSTBRIDGET_ERROR               0xf0000000
    5860
    59 /* define a shortcut */
    60 #define pci     BSP_pci_configuration
    61 
    62 static int                numPCIDevs=0;
     61#define GT64x60_PCI_CONFIG_ADDR         GT64x60_REG_BASE + PCI_CONFIG_ADDR
     62#define GT64x60_PCI_CONFIG_DATA         GT64x60_REG_BASE + PCI_CONFIG_DATA
     63
     64#define GT64x60_PCI1_CONFIG_ADDR        GT64x60_REG_BASE + PCI1_CONFIG_ADDR
     65#define GT64x60_PCI1_CONFIG_DATA        GT64x60_REG_BASE + PCI1_CONFIG_DATA
     66
     67static int      numPCIDevs=0;
     68static DiscoveryChipVersion BSP_sysControllerVersion = 0;
     69static BSP_VMEchipTypes BSP_VMEinterface = 0;
     70static pci_config BSP_pci[2]={
     71  {(volatile unsigned char*) (GT64x60_PCI_CONFIG_ADDR),
     72   (volatile unsigned char*) (GT64x60_PCI_CONFIG_DATA),
     73   0 /* defined at BSP_pci_configuration */},
     74  {(volatile unsigned char*) (GT64x60_PCI1_CONFIG_ADDR),
     75   (volatile unsigned char*) (GT64x60_PCI1_CONFIG_DATA),
     76   0 /* defined at BSP_pci_configuration */}
     77};
     78
    6379extern void pci_interface(void);
    6480
     
    6783 */
    6884#define pciConfigPack(bus,dev,func,offset)\
    69 (((func&7)<<8)|((dev&0x1f )<<11)|(( bus&0xff)<<16)|(offset&0xfc))|0x80000000
     85((offset&~3)<<24)|(PCI_DEVFN(dev,func)<<16)|(bus<<8)|0x80
    7086
    7187/*
     
    7692/* Please note that PCI0 and PCI1 does not correlate with the busNum 0 and 1.
    7793 */
    78 static int direct_pci_read_config_byte(unsigned char bus,unsigned char dev,unsigned char func,
     94static int indirect_pci_read_config_byte(unsigned char bus,unsigned char dev,unsigned char func,
    7995unsigned char offset,unsigned char *val)
    8096{
    81   volatile unsigned char *config_addr, *config_data;
    82 
    83   if (bus>= BSP_MAX_PCI_BUS_ON_PCI0) {
    84      bus-=BSP_MAX_PCI_BUS_ON_PCI0;
    85      config_addr = (volatile unsigned char*) PCI1_CONFIG_ADDR;
    86      config_data = (volatile unsigned char*) PCI1_CONFIG_DATA;
    87   }
    88   else {
    89      config_addr = pci.pci_config_addr;
    90      config_data = pci.pci_config_data;
    91   }
     97  int n=0;
     98
     99  if (bus>= BSP_MAX_PCI_BUS_ON_PCI0) {
     100     bus-=BSP_MAX_PCI_BUS_ON_PCI0;
     101     n=1;
     102  }
     103
    92104  *val = 0xff;
    93105  if (offset & ~0xff) return PCIBIOS_BAD_REGISTER_NUMBER;
    94106#if 0
    95   printk("addr %x, data %x, pack %x \n", config_addr,
    96     config_data,pciConfigPack(bus,dev,func,offset));
    97 #endif
    98   outl(pciConfigPack(bus,dev,func,offset),config_addr);
    99   *val = inb(config_data + (offset&3));
    100   return PCIBIOS_SUCCESSFUL;
    101 }
    102 
    103 static int direct_pci_read_config_word(unsigned char bus, unsigned char dev,
     107  printk("addr %x, data %x, pack %x \n", BSP_pci[n].pci_config_addr),
     108    BSP_pci[n].config_data,pciConfigPack(bus,dev,func,offset));
     109#endif
     110
     111  out_be32(BSP_pci[n].pci_config_addr, pciConfigPack(bus,dev,func,offset));
     112  *val = in_8(BSP_pci[n].pci_config_data + (offset&3));
     113  return PCIBIOS_SUCCESSFUL;
     114}
     115
     116static int indirect_pci_read_config_word(unsigned char bus, unsigned char dev,
    104117unsigned char func, unsigned char offset, unsigned short *val)
    105118{
    106   volatile unsigned char *config_addr, *config_data;
    107 
    108   if (bus>= BSP_MAX_PCI_BUS_ON_PCI0) {
    109      bus-=BSP_MAX_PCI_BUS_ON_PCI0;
    110      config_addr = (volatile unsigned char*) PCI1_CONFIG_ADDR;
    111      config_data = (volatile unsigned char*) PCI1_CONFIG_DATA;
    112   }
    113   else {
    114      config_addr = (volatile unsigned char*) pci.pci_config_addr;
    115      config_data = (volatile unsigned char*) pci.pci_config_data;
     119  int n=0;
     120
     121  if (bus>= BSP_MAX_PCI_BUS_ON_PCI0) {
     122     bus-=BSP_MAX_PCI_BUS_ON_PCI0;
     123     n=1;
    116124  }
    117125
     
    122130    config_data,pciConfigPack(bus,dev,func,offset));
    123131#endif
    124   outl(pciConfigPack(bus,dev,func,offset),config_addr);
    125   *val = inw(config_data + (offset&2));
    126   return PCIBIOS_SUCCESSFUL;
    127 }
    128 
    129 static int direct_pci_read_config_dword(unsigned char bus, unsigned char dev,
     132  out_be32(BSP_pci[n].pci_config_addr, pciConfigPack(bus,dev,func,offset));
     133  *val = in_le16(BSP_pci[n].pci_config_data + (offset&2));
     134  return PCIBIOS_SUCCESSFUL;
     135}
     136
     137static int indirect_pci_read_config_dword(unsigned char bus, unsigned char dev,
    130138unsigned char func, unsigned char offset, unsigned int *val)
    131139{
    132   volatile unsigned char *config_addr, *config_data;
    133 
    134   if (bus>= BSP_MAX_PCI_BUS_ON_PCI0) {
    135      bus-=BSP_MAX_PCI_BUS_ON_PCI0;
    136      config_addr = (volatile unsigned char*) PCI1_CONFIG_ADDR;
    137      config_data = (volatile unsigned char*) PCI1_CONFIG_DATA;
    138   }
    139   else {
    140      config_addr = (volatile unsigned char*) pci.pci_config_addr;
    141      config_data = (volatile unsigned char*) pci.pci_config_data;
     140  int n=0;
     141
     142  if (bus>= BSP_MAX_PCI_BUS_ON_PCI0) {
     143     bus-=BSP_MAX_PCI_BUS_ON_PCI0;
     144     n=1;
    142145  }
    143146
    144147  *val = 0xffffffff;
    145148  if ((offset&3)|| (offset & ~0xff)) return PCIBIOS_BAD_REGISTER_NUMBER;
    146 #if 0
    147   printk("addr %x, data %x, pack %x \n", config_addr,
    148     pci.pci_config_data,pciConfigPack(bus,dev,func,offset));
    149 #endif
    150   outl(pciConfigPack(bus,dev,func,offset),config_addr);
    151   *val = inl(config_data);
    152   return PCIBIOS_SUCCESSFUL;
    153 }
    154 
    155 static int direct_pci_write_config_byte(unsigned char bus, unsigned char dev,unsigned char func, unsigned char offset, unsigned char val)
    156 {
    157   volatile unsigned char *config_addr, *config_data;
    158 
    159   if (bus>= BSP_MAX_PCI_BUS_ON_PCI0) {
    160      bus-=BSP_MAX_PCI_BUS_ON_PCI0;
    161      config_addr = (volatile unsigned char*) PCI1_CONFIG_ADDR;
    162      config_data = (volatile unsigned char*) PCI1_CONFIG_DATA;
    163   }
    164   else {
    165      config_addr = pci.pci_config_addr;
    166      config_data = pci.pci_config_data;
     149
     150  out_be32(BSP_pci[n].pci_config_addr, pciConfigPack(bus,dev,func,offset));
     151  *val = in_le32(BSP_pci[n].pci_config_data);
     152  return PCIBIOS_SUCCESSFUL;
     153}
     154
     155static int indirect_pci_write_config_byte(unsigned char bus, unsigned char dev,unsigned char func, unsigned char offset, unsigned char val)
     156{
     157  int n=0;
     158
     159  if (bus>= BSP_MAX_PCI_BUS_ON_PCI0) {
     160     bus-=BSP_MAX_PCI_BUS_ON_PCI0;
     161     n=1;
    167162  }
    168163
    169164  if (offset & ~0xff) return PCIBIOS_BAD_REGISTER_NUMBER;
    170 #if 0
    171   printk("addr %x, data %x, pack %x \n", config_addr,
    172     config_data,pciConfigPack(bus,dev,func,offset));
    173 #endif
    174 
    175   outl(pciConfigPack(bus,dev,func,offset), config_addr);
    176   outb(val, config_data + (offset&3));
    177   return PCIBIOS_SUCCESSFUL;
    178 }
    179 
    180 static int direct_pci_write_config_word(unsigned char bus, unsigned char dev,unsigned char func, unsigned char offset, unsigned short val)
    181 {
    182   volatile unsigned char *config_addr, *config_data;
    183 
    184   if (bus>= BSP_MAX_PCI_BUS_ON_PCI0) {
    185      bus-=BSP_MAX_PCI_BUS_ON_PCI0;
    186      config_addr = (volatile unsigned char*) PCI1_CONFIG_ADDR;
    187      config_data = (volatile unsigned char*) PCI1_CONFIG_DATA;
    188   }
    189   else {
    190      config_addr = (volatile unsigned char*) pci.pci_config_addr;
    191      config_data = (volatile unsigned char*) pci.pci_config_data;
     165
     166  out_be32(BSP_pci[n].pci_config_addr, pciConfigPack(bus,dev,func,offset));
     167  out_8(BSP_pci[n].pci_config_data + (offset&3), val);
     168  return PCIBIOS_SUCCESSFUL;
     169}
     170
     171static int indirect_pci_write_config_word(unsigned char bus, unsigned char dev,unsigned char func, unsigned char offset, unsigned short val)
     172{
     173  int n=0;
     174
     175  if (bus>= BSP_MAX_PCI_BUS_ON_PCI0) {
     176     bus-=BSP_MAX_PCI_BUS_ON_PCI0;
     177     n=1;
    192178  }
    193179
    194180  if ((offset&1)|| (offset & ~0xff)) return PCIBIOS_BAD_REGISTER_NUMBER;
    195 #if 0
    196   printk("addr %x, data %x, pack %x \n", config_addr,
    197     config_data,pciConfigPack(bus,dev,func,offset));
    198 #endif
    199   outl(pciConfigPack(bus,dev,func,offset),config_addr);
    200   outw(val, config_data + (offset&3));
    201   return PCIBIOS_SUCCESSFUL;
    202 }
    203 
    204 static int direct_pci_write_config_dword(unsigned char bus,unsigned char dev,unsigned char func, unsigned char offset, unsigned int val)
    205 {
    206   volatile unsigned char *config_addr, *config_data;
    207 
    208   if (bus>= BSP_MAX_PCI_BUS_ON_PCI0) {
    209      bus-=BSP_MAX_PCI_BUS_ON_PCI0;
    210      config_addr = (volatile unsigned char *) PCI1_CONFIG_ADDR;
    211      config_data = (volatile unsigned char *) PCI1_CONFIG_DATA;
    212   }
    213   else {
    214      config_addr = (volatile unsigned char*) pci.pci_config_addr;
    215      config_data = (volatile unsigned char*) pci.pci_config_data;
     181
     182  out_be32(BSP_pci[n].pci_config_addr, pciConfigPack(bus,dev,func,offset));
     183  out_le16(BSP_pci[n].pci_config_data + (offset&3), val);
     184  return PCIBIOS_SUCCESSFUL;
     185}
     186
     187static int indirect_pci_write_config_dword(unsigned char bus,unsigned char dev,unsigned char func, unsigned char offset, unsigned int val)
     188{
     189  int n=0;
     190
     191  if (bus>= BSP_MAX_PCI_BUS_ON_PCI0) {
     192     bus-=BSP_MAX_PCI_BUS_ON_PCI0;
     193     n=1;
    216194  }
    217195
    218196  if ((offset&3)|| (offset & ~0xff)) return PCIBIOS_BAD_REGISTER_NUMBER;
    219 #if 0
    220   printk("addr %x, data %x, pack %x \n", config_addr,
    221     config_data,pciConfigPack(bus,dev,func,offset));
    222 #endif
    223   outl(pciConfigPack(bus,dev,func,offset),config_addr);
    224   outl(val,config_data);
    225   return PCIBIOS_SUCCESSFUL;
    226 }
    227 
    228 const pci_config_access_functions pci_direct_functions = {
    229         direct_pci_read_config_byte,
    230         direct_pci_read_config_word,
    231         direct_pci_read_config_dword,
    232         direct_pci_write_config_byte,
    233         direct_pci_write_config_word,
    234         direct_pci_write_config_dword
     197
     198  out_be32(BSP_pci[n].pci_config_addr, pciConfigPack(bus,dev,func,offset));
     199  out_le32(BSP_pci[n].pci_config_data, val);
     200  return PCIBIOS_SUCCESSFUL;
     201}
     202
     203const pci_config_access_functions pci_indirect_functions = {
     204        indirect_pci_read_config_byte,
     205        indirect_pci_read_config_word,
     206        indirect_pci_read_config_dword,
     207        indirect_pci_write_config_byte,
     208        indirect_pci_write_config_word,
     209        indirect_pci_write_config_dword
    235210};
    236211
    237212
    238 pci_config BSP_pci_configuration = {(volatile unsigned char*) PCI_CONFIG_ADDR,
    239                          (volatile unsigned char*)PCI_CONFIG_DATA,
    240                                     &pci_direct_functions};
     213pci_config BSP_pci_configuration = {
     214           (volatile unsigned char*) (GT64x60_PCI_CONFIG_ADDR),
     215           (volatile unsigned char*) (GT64x60_PCI_CONFIG_DATA),
     216           &pci_indirect_functions};
     217
     218DiscoveryChipVersion BSP_getDiscoveryChipVersion(void)
     219{
     220  return(BSP_sysControllerVersion);
     221}
     222
     223BSP_VMEchipTypes BSP_getVMEchipType(void)
     224{
     225  return(BSP_VMEinterface);
     226}
    241227
    242228/*
     
    249235{
    250236  int deviceFound;
    251   unsigned char ucBusNumber, ucSlotNumber, ucFnNumber, ucNumFuncs;
    252   unsigned int ulHeader;
    253   unsigned int pcidata, ulClass, ulDeviceID;
    254 
    255   pci_interface();
    256  
     237  unsigned char ucBusNumber, ucSlotNumber, ucFnNumber, ucNumFuncs, data8;
     238  uint32_t ulHeader, ulClass, ulDeviceID;
     239#if PCI_DEBUG
     240  uint32_t pcidata;
     241#endif
     242
    257243  /*
    258244   * Scan PCI0 and PCI1 buses
     
    280266      switch(ulDeviceID) {
    281267        case (PCI_VENDOR_ID_MARVELL+(PCI_DEVICE_ID_MARVELL_GT6426xAB<<16)):
     268          pci_read_config_byte(0,0,0,PCI_REVISION_ID, &data8);
     269          switch(data8) {
     270          case 0x10:
     271            BSP_sysControllerVersion = GT64260A;
    282272#if PCI_PRINT
    283           printk("Marvell GT6426xA/B hostbridge detected at bus%d slot%d\n",
     273            printk("Marvell GT64260A (Discovery I) hostbridge detected at bus%d slot%d\n",
    284274                 ucBusNumber,ucSlotNumber);
    285275#endif
     276            break;
     277          case 0x20:
     278            BSP_sysControllerVersion = GT64260B;
     279#if PCI_PRINT
     280            printk("Marvell GT64260B (Discovery I) hostbridge detected at bus%d slot%d\n",
     281                 ucBusNumber,ucSlotNumber);
     282#endif
     283            break;
     284          default:
     285            printk("Undefined revsion of GT64260 chip\n");
     286            break;
     287          }
    286288          break;
    287         case (PCI_VENDOR_ID_PLX2+(PCI_DEVICE_ID_PLX2_PCI6154_HB2<<16)):
    288 #if PCI_PRINT
    289           printk("PLX PCI6154 PCI-PCI bridge detected at bus%d slot%d\n",
    290                  ucBusNumber,ucSlotNumber);
    291 #endif
    292           break;
    293289        case PCI_VENDOR_ID_TUNDRA:
    294290#if PCI_PRINT
     
    297293#endif
    298294          break;
    299       case (PCI_VENDOR_ID_INTEL+(PCI_DEVICE_INTEL_82544EI_COPPER<<16)):
     295      case (PCI_VENDOR_ID_DEC+(PCI_DEVICE_ID_DEC_21150<<16)):
    300296#if PCI_PRINT
    301           printk("INTEL 82544EI COPPER network controller detected at bus%d slot%d\n",
    302                  ucBusNumber,ucSlotNumber);
    303 #endif
    304           break;
    305       case (PCI_VENDOR_ID_DEC+(PCI_DEVICE_ID_DEC_21150<<16)):
    306  #if PCI_PRINT
    307297          printk("DEC21150 PCI-PCI bridge detected at bus%d slot%d\n",
    308298                 ucBusNumber,ucSlotNumber);
     
    310300          break;
    311301       default :
     302#if PCI_PRINT
    312303          printk("BSP unlisted vendor, Bus%d Slot%d DeviceID 0x%x \n",
    313304             ucBusNumber,ucSlotNumber, ulDeviceID);
     305#endif
     306          /* Kate Feng : device not supported by BSP needs to remap the IRQ line on mvme5500/mvme6100 */
     307          pci_read_config_byte(ucBusNumber,ucSlotNumber,0,PCI_INTERRUPT_LINE,&data8);
     308          if (data8 < BSP_GPP_IRQ_LOWEST_OFFSET)  pci_write_config_byte(ucBusNumber,
     309             ucSlotNumber,0,PCI_INTERRUPT_LINE,BSP_GPP_IRQ_LOWEST_OFFSET+data8);
     310
    314311          break;
    315312      }
     
    404401
    405402      }
    406 
    407       pci_read_config_dword(ucBusNumber,
    408                                ucSlotNumber,
    409                                0,
    410                           PCI_COMMAND,
    411                           &pcidata);
    412 #if PCI_DEBUG
    413       printk("MOTLoad command staus 0x%x, ", pcidata);
    414 #endif
    415       /* Clear the error on the host bridge */
    416       if ( (ucBusNumber==0) && (ucSlotNumber==0))
    417         pcidata |= PCI_STATUS_CLRERR_MASK;
    418       /* Enable bus,I/O and memory master access. */
    419       pcidata |= (PCI_COMMAND_MASTER|PCI_COMMAND_IO|PCI_COMMAND_MEMORY);
    420       pci_write_config_dword(ucBusNumber,
    421                                ucSlotNumber,
    422                                0,
    423                           PCI_COMMAND,
    424                           pcidata);
    425 
    426       pci_read_config_dword(ucBusNumber,
    427                                ucSlotNumber,
    428                                0,
    429                           PCI_COMMAND,
    430                           &pcidata);
    431 #if PCI_DEBUG     
    432       printk("Now command/staus 0x%x\n", pcidata);
    433 #endif
    434403    }
    435404    if (deviceFound) ucMaxPCIBus++;
     
    439408         pci_bus_count(), numPCIDevs);
    440409#endif
     410  pci_interface();
    441411  return(0);
    442412}
  • c/src/lib/libbsp/powerpc/mvme5500/pci/pci_interface.c

    ref3a82f rcf599996  
    88 *
    99 * 8/17/2006 : S. Kate Feng
    10  *             uses in_le32()/out_le32(), instead of inl()/outl() so that
    11  *             it is easier to be ported.
     10 *             uses in_le32()/out_le32(), instead of inl()/outl() for compatibility.
    1211 *
     12 * 11/2008 : Enable "PCI Read Agressive Prefetch",
     13 *           "PCI Read Line Agressive Prefetch", and
     14 *           "PCI Read Multiple Agressive Prefetch" to improve the
     15 *           performance of the PCI based applications (e.g. 1GHz NIC).
    1316 */
     17
    1418#include <libcpu/io.h>
    1519#include <rtems/bspIo.h>            /* printk */
     
    2024#include <bsp/gtpcireg.h>
    2125
    22 #define REG32_READ(reg) in_le32((volatile unsigned int *)(GT64260_REG_BASE+reg))
    23 #define REG32_WRITE(data, reg) out_le32((volatile unsigned int *)(GT64260_REG_BASE+reg), data)
    24 
    2526#define PCI_DEBUG     0
    2627
    27 /* Please reference the GT64260B datasheet, for the PCI interface,
    28  * Synchronization Barriers and PCI ordering.
    29  *
    30  * Some PCI devices require Synchronization Barriers or PCI ordering
    31  * for synchronization (only one mechanism allowed. See section 11.1.2).
    32  * To use the former mechanism(default), one needs to call
    33  * CPU0_PciEnhanceSync() or CPU1_PciEnhanceSync() to perform software
    34  * synchronization between the CPU and PCI activities.
    35  *
    36  * To use the PCI-ordering, one can call pciToCpuSync() to trigger
    37  * the PCI-to-CPU sync barrier after the out_xx(). In this mode,
    38  * PCI configuration reads suffer sync barrier latency. Please reference
    39  * the datasheet to explore other options.
    40  *
    41  * Note : If PCI_ORDERING is needed for the PCI0, while disabling the
    42  * deadlock  for the PCI0, one should keep the CommDLEn bit enabled
    43  * for the deadlock mechanism so that the 10/100 MB ethernet will
    44  * function correctly.
    45  *
     28#if 0
     29#define CPU2PCI_ORDER
     30#define PCI2CPU_ORDER
     31#endif
     32
     33/* PCI Read Agressive Prefetch Enable (1<<16 ),
     34 * PCI Read Line Agressive Prefetch Enable( 1<<17),
     35 * PCI Read Multiple Agressive Prefetch Enable (1<<18).
    4636 */
    47 /*#define PCI_ORDERING*/
     37#ifdef PCI2CPU_ORDER
     38#define PCI_ACCCTLBASEL_VALUE          0x01079000
     39#else
     40#define PCI_ACCCTLBASEL_VALUE          0x01071000
     41#endif
    4842
    49 #define EN_SYN_BAR   /* take MOTLoad default for enhanced SYN Barrier mode */
    50 
    51 /*#define PCI_DEADLOCK*/
    52 
    53 #ifdef PCI_ORDERING
    54 #define PCI_ACCCTLBASEL_VALUE          0x01009000
    55 #else
    56 #define PCI_ACCCTLBASEL_VALUE          0x01001000
    57 #endif
    5843
    5944#define ConfSBDis     0x10000000  /* 1: disable, 0: enable */
     
    6146#define ConfIOSBDis   0x30000000
    6247#define CpuPipeline   0x00002000  /* optional, 1:enable, 0:disable */
    63 
    64 #define CPU0_SYNC_TRIGGER   0xD0  /* CPU0 Sync Barrier trigger */
    65 #define CPU0_SYNC_VIRTUAL   0xC0  /* CPU0 Sync Barrier Virtual */
    66 
    67 #define CPU1_SYNC_TRIGGER   0xD8  /* CPU1 Sync Barrier trigger */
    68 #define CPU1_SYNC_VIRTUAL   0xC8  /* CPU1 Sync Barrier Virtual */
    69 
    7048
    7149/* CPU to PCI ordering register */
     
    9270{
    9371
    94 #ifdef PCI_DEADLOCK
    95   REG32_WRITE(0x07fff600, CNT_SYNC_REG);
     72#ifdef CPU2PCI_ORDER
     73    /* MOTLOad deafult : 0x07ff8600 */
     74    out_le32((volatile unsigned int *)(GT64x60_REG_BASE+CNT_SYNC_REG), 0x07fff600);
    9675#endif
    97 #ifdef PCI_ORDERING
    98   /* Let's leave this to be MOTLOad deafult : 0x80070000
    99      REG32_WRITE(0xc0070000, DLOCK_ORDER_REG);*/
    100   /* Leave the CNT_SYNC_REG b/c MOTload default had the SyncBarMode set to 1 */
    101 #endif
     76    /* asserts SERR upon various detection */
     77    out_le32((volatile unsigned int *)(GT64x60_REG_BASE+0xc28), 0x3fffff);
     78    pciAccessInit();
     79}
    10280
    103   /* asserts SERR upon various detection */
    104   REG32_WRITE(0x3fffff, 0xc28);
    105 
    106   pciAccessInit();
    107 }
    108 /* Use MOTLoad default for Writeback Priority and Buffer Depth
    109  */
    11081void pciAccessInit(void)
    11182{
     
    11384
    11485  for (PciLocal=0; PciLocal < 2; PciLocal++) {
    115     /* MOTLoad combines the two banks of SDRAM into
    116      * one PCI access control because the top = 0x1ff
    117      */
    118     data = REG32_READ(GT_SCS0_Low_Decode) & 0xfff;
     86    data = in_le32((volatile unsigned int *)(GT64x60_REG_BASE+PCI0_ACCESS_CNTL_BASE0_LOW+(PciLocal * 0x80)));
     87#if 0
     88    printk("PCI%d_ACCESS_CNTL_BASE0_LOW was 0x%x\n",PciLocal,data);
     89#endif
    11990    data |= PCI_ACCCTLBASEL_VALUE;
    12091    data &= ~0x300000;
    121     REG32_WRITE(data, PCI0_ACCESS_CNTL_BASE0_LOW+(PciLocal * 0x80));
    122 #if PCI_DEBUG
    123     printk("PCI%d_ACCESS_CNTL_BASE0_LOW 0x%x\n",PciLocal,REG32_READ(PCI_ACCESS_CNTL_BASE0_LOW+(PciLocal * 0x80)));
     92    out_le32((volatile unsigned int *)(GT64x60_REG_BASE+PCI0_ACCESS_CNTL_BASE0_LOW+(PciLocal * 0x80)), data);
     93#if 0
     94      printf("PCI%d_ACCESS_CNTL_BASE0_LOW now 0x%x\n",PciLocal,in_le32((volatile unsigned int *)(GT64x60_REG_BASE+PCI0_ACCESS_CNTL_BASE0_LOW+(PciLocal * 0x80))));
    12495#endif
    125 
    12696  }
    12797}
    12898
    129 /* Sync Barrier Trigger. A write to the CPU_SYNC_TRIGGER register triggers
    130  * the sync barrier process.  The three bits, define which buffers should
    131  * be flushed.
    132  * Bit 0 = PCI0 slave write buffer.
    133  * Bit 1 = PCI1 slave write buffer.
    134  * Bit 2 = SDRAM snoop queue.
    135  */
    136 void CPU0_PciEnhanceSync(unsigned int syncVal)
    137 {
    138   REG32_WRITE(syncVal,CPU0_SYNC_TRIGGER);
    139   while (REG32_READ(CPU0_SYNC_VIRTUAL));
    140 }
    141 
    142 void CPU1_PciEnhanceSync(unsigned int syncVal)
    143 {
    144   REG32_WRITE(syncVal,CPU1_SYNC_TRIGGER);
    145   while (REG32_READ(CPU1_SYNC_VIRTUAL));
    146 }
    147 
    148 /* Currently, if PCI_ordering is used for synchronization, configuration
    149  * reads is programmed to be the PCI slave "synchronization barrier"
    150  * cycles.
    151  */
    152 void pciToCpuSync(int pci_num)
    153 {
    154   unsigned char data;
    155   unsigned char bus=0;
    156 
    157   if (pci_num) bus += BSP_MAX_PCI_BUS_ON_PCI0;
    158   pci_read_config_byte(bus,0,0,4, &data);
    159 }
  • c/src/lib/libbsp/powerpc/mvme5500/startup/bspclean.c

    ref3a82f rcf599996  
     1/* Copyright 2003, Shuchen Kate Feng <feng1@bnl.gov>,
     2 *                    NSLS,Brookhaven National Laboratory
     3 */
    14#include <bsp.h>
    25#include <rtems/bspIo.h>
  • c/src/lib/libbsp/powerpc/mvme5500/startup/bspstart.c

    ref3a82f rcf599996  
    2424 *  $Id$
    2525 */
    26 
    27 #warning The interrupt disable mask is now stored in SPRG0, please verify that this is compatible to this BSP (see also bootcard.c).
    2826
    2927#include <string.h>
     
    5351#endif
    5452
    55 /*
    56 #define SHOW_MORE_INIT_SETTINGS
     53
     54/*#define SHOW_MORE_INIT_SETTINGS
     55#define CONF_VPD
    5756#define SHOW_LCR1_REGISTER
    5857#define SHOW_LCR2_REGISTER
    5958#define SHOW_LCR3_REGISTER
    60 #define CONF_VPD
    6159*/
    6260
     
    7472extern int I2Cread_eeprom(unsigned char I2cBusAddr, uint32_t devA2A1A0, uint32_t AddrBytes, unsigned char *pBuff, uint32_t numBytes);
    7573extern void BSP_vme_config(void);
     74extern uint32_t probeMemoryEnd();
    7675
    7776uint32_t bsp_clicks_per_usec;
     
    268267
    269268  /* Till Straumann: 2004
    270    * map the PCI 0, 1 Domain I/O space, GT64260B registers
    271    * and the reserved area so that the size is the power of 2.
    272    *
    273    */
    274   setdbat(3,PCI0_IO_BASE, PCI0_IO_BASE, 0x2000000, IO_PAGE);
    275 
     269   * map the PCI 0, 1 Domain I/O space, GT64260B registers,
     270   * Flash Bank 0 and Flash Bank 2.
     271   */
     272  setdbat(3,PCI0_IO_BASE, PCI0_IO_BASE, 0x10000000, IO_PAGE);
    276273
    277274  /*
     
    328325  printk("-----------------------------------------\n");
    329326
    330 #ifdef TEST_RETURN_TO_PPCBUG 
    331   printk("Hit <Enter> to return to PPCBUG monitor\n");
    332   printk("When Finished hit GO. It should print <Back from monitor>\n");
    333   debug_getc();
    334   _return_to_ppcbug();
    335   printk("Back from monitor\n");
    336   _return_to_ppcbug();
    337 #endif /* TEST_RETURN_TO_PPCBUG  */
    338 
    339 #ifdef TEST_RAW_EXCEPTION_CODE 
    340   printk("Testing exception handling Part 1\n");
    341   /*
    342    * Cause a software exception
    343    */
    344   __asm__ __volatile ("sc");
    345   /*
    346    * Check we can still catch exceptions and returned coorectly.
    347    */
    348   printk("Testing exception handling Part 2\n");
    349   __asm__ __volatile ("sc");
    350 #endif 
    351 
    352   BSP_mem_size         =  _512M;
     327  BSP_mem_size         =  probeMemoryEnd();
    353328  /* TODO: calculate the BSP_bus_frequency using the REF_CLK bit
    354329   *       of System Status  register
     
    422397    BSP_pgtbl_activate(pt);
    423398  }
    424 
    425   /*
    426    * PCI 1 domain memory space
    427    */
    428   setdbat(1, PCI1_MEM_BASE, PCI1_MEM_BASE, 0x10000000, IO_PAGE);
    429  
    430 
    431 #ifdef SHOW_MORE_INIT_SETTINGS
    432   printk("Going to start PCI buses scanning and initialization\n");
    433 #endif 
    434   pci_initialize();
    435 #ifdef SHOW_MORE_INIT_SETTINGS
    436   printk("Number of PCI buses found is : %d\n", pci_bus_count());
    437 #endif
    438 
    439   /* Install our own exception handler (needs PCI) */
    440   globalExceptHdl = BSP_exceptionHandler;
    441 
    442   /* clear hostbridge errors. MCP signal is not used on the MVME5500
    443    * PCI config space scanning code will trip otherwise :-(
    444    */
    445   _BSP_clear_hostbridge_errors(0, 1 /*quiet*/);
    446 
    447399  /* Read Configuration Vital Product Data (VPD) */
    448400  if ( I2Cread_eeprom(0xa8, 4,2, &ConfVPD_buff[0], 150))
     
    459411  }
    460412
     413  /*
     414   * PCI 1 domain memory space
     415   */
     416  setdbat(1, PCI1_MEM_BASE, PCI1_MEM_BASE, 0x10000000, IO_PAGE);
     417 
     418
     419#ifdef SHOW_MORE_INIT_SETTINGS
     420  printk("Going to start PCI buses scanning and initialization\n");
     421#endif 
     422  pci_initialize();
     423#ifdef SHOW_MORE_INIT_SETTINGS
     424  printk("Number of PCI buses found is : %d\n", pci_bus_count());
     425#endif
     426
     427  /* Install our own exception handler (needs PCI) */
     428  globalExceptHdl = BSP_exceptionHandler;
     429
     430  /* clear hostbridge errors. MCP signal is not used on the MVME5500
     431   * PCI config space scanning code will trip otherwise :-(
     432   */
     433  _BSP_clear_hostbridge_errors(0, 1 /*quiet*/);
     434
    461435#ifdef SHOW_MORE_INIT_SETTINGS
    462436  printk("MSR %x \n", _read_MSR());
     
    465439
    466440}
     441
     442unsigned char ReadConfVPD_buff(int offset)
     443{
     444  return(ConfVPD_buff[offset]);
     445}
  • c/src/lib/libbsp/powerpc/mvme5500/startup/reboot.c

    ref3a82f rcf599996  
     1/* Copyright 2003, Shuchen Kate Feng <feng1@bnl.gov>,
     2 *                    NSLS,Brookhaven National Laboratory
     3 *
     4 * Ported it from powerpc/shared/console/reboot.c for mvme5500
     5 *
     6 */
     7
    18#include <rtems.h>
    29#include <bsp.h>
     
    1320  printk("RTEMS terminated; Rebooting ...\n");
    1421  /* Mvme5500 board reset : 2004 S. Kate Feng <feng1@bnl.gov>  */
    15   out_8((volatile unsigned char*) (GT64260_DEV1_BASE +2), 0x80);
     22  out_8((volatile unsigned char*) (GT64x60_DEV1_BASE +2), 0x80);
    1623}
  • c/src/lib/libbsp/powerpc/mvme5500/vectors/exceptionhandler.c

    ref3a82f rcf599996  
    135135       printk("\t Next PC or Address of fault = %x, ", excPtr->EXC_SRR0);
    136136       printk("Mvme5500 Saved MSR = %x\n", excPtr->EXC_SRR1);
     137       printk("The Interrupt mask (e.g. MSR_EE) stored in SPRG0= 0x%x\n",
     138              ppc_interrupt_get_disable_mask());
    137139       printk("\t R0  = %08x", excPtr->GPR0);
    138140       printk(" R1  = %08x", excPtr->GPR1);
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