Changeset cf3d1948 in rtems


Ignore:
Timestamp:
Aug 24, 2011, 9:43:06 AM (10 years ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
4.11, 5, master
Children:
1d367a49
Parents:
76c0fb00
Message:

2011-08-24 Sebastian Huber <sebastian.huber@…>

  • rtems/powerpc/registers.h: Renamed defines XER in PPC_XER, LR in PPC_LR, CTR in PPC_CTR, PVR in PPC_PVR, RPA in PPC_RPA, DAR in PPC_DAR, DEC in PPC_DEC, and EAR in PPC_EAR.
Location:
cpukit/score/cpu/powerpc
Files:
2 edited

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  • cpukit/score/cpu/powerpc/ChangeLog

    r76c0fb00 rcf3d1948  
     12011-08-24      Sebastian Huber <sebastian.huber@embedded-brains.de>
     2
     3        * rtems/powerpc/registers.h: Renamed defines XER in PPC_XER, LR in
     4        PPC_LR, CTR in PPC_CTR, PVR in PPC_PVR, RPA in PPC_RPA, DAR in
     5        PPC_DAR, DEC in PPC_DEC, and EAR in PPC_EAR.
     6
    172011-07-21      Sebastian Huber <sebastian.huber@embedded-brains.de>
    28
  • cpukit/score/cpu/powerpc/rtems/powerpc/registers.h

    r76c0fb00 rcf3d1948  
    123123#define TBWU    285     /* Time base Upper/Lower (Writing) */
    124124#define TBWL    284
    125 #define XER     1
    126 #define LR      8
    127 #define CTR     9
     125#define PPC_XER 1
     126#define PPC_LR  8
     127#define PPC_CTR 9
    128128#define HID0    1008    /* Hardware Implementation 0 */
    129129#define HID1    1009    /* Hardware Implementation 1 */
    130130#define HID2    1011    /* Hardware Implementation 2 */
    131131#define DABR    1013    /* Data Access Breakpoint  */
    132 #define PVR     287     /* Processor Version */
     132#define PPC_PVR 287     /* Processor Version */
    133133#define IBAT0U  528     /* Instruction BAT #0 Upper/Lower */
    134134#define IBAT0L  529
     
    175175#define IMISS   980
    176176#define ICMP    981
    177 #define RPA     982
     177#define PPC_RPA 982
    178178#define SDR1    25      /* MMU hash base register */
    179 #define DAR     19      /* Data Address Register */
     179#define PPC_DAR 19      /* Data Address Register */
    180180#define DEAR_BOOKE 61
    181181#define DEAR_405 981
     
    197197#define SRR1    27
    198198#define IABR    1010    /* Instruction Address Breakpoint */
    199 #define DEC     22      /* Decrementer */
    200 #define EAR     282     /* External Address Register */
     199#define PPC_DEC 22      /* Decrementer */
     200#define PPC_EAR 282     /* External Address Register */
    201201
    202202#define MSSCR0   1014   /* Memory Subsystem Control Register */
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