Changeset cf1f72e in rtems for c/src/lib/libcpu/shared/src


Ignore:
Timestamp:
Jun 13, 2000, 9:53:38 PM (20 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, 5, master
Children:
7d52750
Parents:
f0b11d63
Message:

Moved i386 and m68k cache management code to libcpu. Everything
now is an implementation of the prototypes in rtems/rtems/cache.h.
The libcpu/i386/wrapup directory is no longer needed.
The PowerPC needs this done to it.

Location:
c/src/lib/libcpu/shared/src
Files:
1 added
1 moved

Legend:

Unmodified
Added
Removed
  • c/src/lib/libcpu/shared/src/cache_manager.c

    rf0b11d63 rcf1f72e  
    1 /*  cache.c
    2  *
     1/*
    32 *  Cache Manager
    43 *
     
    1110 *
    1211 * 
    13  *  The functions in this file define the API to the RTEMS Cache Manager and
     12 *  The functions in this file implement the API to the RTEMS Cache Manager and
    1413 *  are divided into data cache and instruction cache functions. Data cache
    1514 *  functions are only declared if a data cache is supported. Instruction
     
    3130 */
    3231
    33 #include <rtems/system.h>
     32#include <rtems.h>
    3433#include <sys/types.h>
    35 #include <rtems/rtems/cache.h>
    36 
    37 
    38 /*
    39  * THESE FUNCTIONS ONLY EXIST IF WE HAVE A DATA CACHE
    40  */
    41 #if defined(_CPU_DATA_CACHE_ALIGNMENT)
     34#include <libcpu/cache.h>
     35#include "cache_.h"
     36
     37
     38/*
     39 * THESE FUNCTIONS ONLY HAVE BODIES IF WE HAVE A DATA CACHE
     40 */
    4241
    4342/*
     
    4948rtems_flush_multiple_data_cache_lines( const void * d_addr, size_t n_bytes )
    5049{
    51     const void * final_address;
    52    /*
    53     * Set d_addr to the beginning of the cache line; final_address indicates
    54     * the last address_t which needs to be pushed. Increment d_addr and push
    55     * the resulting line until final_address is passed.
    56     */
    57     final_address = (void *)((size_t)d_addr + n_bytes - 1);
    58     d_addr = (void *)((size_t)d_addr & ~(_CPU_DATA_CACHE_ALIGNMENT - 1));
    59     while( d_addr <= final_address )  {
    60         _CPU_flush_1_data_cache_line( d_addr );
    61         d_addr = (void *)((size_t)d_addr + _CPU_DATA_CACHE_ALIGNMENT);
    62     }
     50#if defined(_CPU_DATA_CACHE_ALIGNMENT)
     51  const void * final_address;
     52
     53 /*
     54  * Set d_addr to the beginning of the cache line; final_address indicates
     55  * the last address_t which needs to be pushed. Increment d_addr and push
     56  * the resulting line until final_address is passed.
     57  */
     58
     59  final_address = (void *)((size_t)d_addr + n_bytes - 1);
     60  d_addr = (void *)((size_t)d_addr & ~(_CPU_DATA_CACHE_ALIGNMENT - 1));
     61  while( d_addr <= final_address )  {
     62    _CPU_flush_1_data_cache_line( d_addr );
     63    d_addr = (void *)((size_t)d_addr + _CPU_DATA_CACHE_ALIGNMENT);
     64  }
     65#endif
    6366}
    6467
     
    6972 * perform the invalidations.
    7073 */
     74
    7175void
    7276rtems_invalidate_multiple_data_cache_lines( const void * d_addr, size_t n_bytes )
    7377{
    74     const void * final_address;
    75    /*
    76     * Set d_addr to the beginning of the cache line; final_address indicates
    77     * the last address_t which needs to be invalidated. Increment d_addr and
    78     * invalidate the resulting line until final_address is passed.
    79     */
    80     final_address = (void *)((size_t)d_addr + n_bytes - 1);
    81     d_addr = (void *)((size_t)d_addr & ~(_CPU_DATA_CACHE_ALIGNMENT - 1));
    82     while( final_address > d_addr ) {
    83         _CPU_invalidate_1_data_cache_line( d_addr );
    84         d_addr = (void *)((size_t)d_addr + _CPU_DATA_CACHE_ALIGNMENT);
    85     }
     78#if defined(_CPU_DATA_CACHE_ALIGNMENT)
     79  const void * final_address;
     80
     81 /*
     82  * Set d_addr to the beginning of the cache line; final_address indicates
     83  * the last address_t which needs to be invalidated. Increment d_addr and
     84  * invalidate the resulting line until final_address is passed.
     85  */
     86
     87  final_address = (void *)((size_t)d_addr + n_bytes - 1);
     88  d_addr = (void *)((size_t)d_addr & ~(_CPU_DATA_CACHE_ALIGNMENT - 1));
     89  while( final_address > d_addr ) {
     90    _CPU_invalidate_1_data_cache_line( d_addr );
     91    d_addr = (void *)((size_t)d_addr + _CPU_DATA_CACHE_ALIGNMENT);
     92  }
     93#endif
    8694}
    8795
     
    94102rtems_flush_entire_data_cache( void )
    95103{
     104#if defined(_CPU_DATA_CACHE_ALIGNMENT)
    96105   /*
    97106    * Call the CPU-specific routine
    98107    */
    99108   _CPU_flush_entire_data_cache();
    100      
     109#endif
    101110}
    102111
     
    109118rtems_invalidate_entire_data_cache( void )
    110119{
    111    /*
    112     * Call the CPU-specific routine
    113     */
    114    _CPU_invalidate_entire_data_cache();
     120#if defined(_CPU_DATA_CACHE_ALIGNMENT)
     121 /*
     122  * Call the CPU-specific routine
     123  */
     124
     125 _CPU_invalidate_entire_data_cache();
     126#endif
    115127}
    116128
     
    122134rtems_get_data_cache_line_size( void )
    123135{
    124         return _CPU_DATA_CACHE_ALIGNMENT;
     136#if defined(_CPU_DATA_CACHE_ALIGNMENT)
     137  return _CPU_DATA_CACHE_ALIGNMENT;
     138#else
     139  return 0;
     140#endif
    125141}
    126142
     
    133149rtems_freeze_data_cache( void )
    134150{
    135         _CPU_freeze_data_cache();
     151#if defined(_CPU_DATA_CACHE_ALIGNMENT)
     152  _CPU_freeze_data_cache();
     153#endif
    136154}
    137155
     
    142160void rtems_unfreeze_data_cache( void )
    143161{
    144         _CPU_unfreeze_data_cache();
     162#if defined(_CPU_DATA_CACHE_ALIGNMENT)
     163  _CPU_unfreeze_data_cache();
     164#endif
    145165}
    146166
     
    150170rtems_enable_data_cache( void )
    151171{
    152         _CPU_enable_data_cache();
     172#if defined(_CPU_DATA_CACHE_ALIGNMENT)
     173  _CPU_enable_data_cache();
     174#endif
    153175}
    154176
     
    158180rtems_disable_data_cache( void )
    159181{
    160         _CPU_disable_data_cache();
    161 }
    162 #endif
    163 
    164 
    165 
    166 /*
    167  * THESE FUNCTIONS ONLY EXIST IF WE HAVE AN INSTRUCTION CACHE
    168  */
    169 #if defined(_CPU_INST_CACHE_ALIGNMENT)
     182#if defined(_CPU_DATA_CACHE_ALIGNMENT)
     183  _CPU_disable_data_cache();
     184#endif
     185}
     186
     187
     188
     189/*
     190 * THESE FUNCTIONS ONLY HAVE BODIES IF WE HAVE AN INSTRUCTION CACHE
     191 */
    170192
    171193/*
     
    177199rtems_invalidate_multiple_inst_cache_lines( const void * i_addr, size_t n_bytes )
    178200{
    179     const void * final_address;
    180    /*
    181     * Set i_addr to the beginning of the cache line; final_address indicates
    182     * the last address_t which needs to be invalidated. Increment i_addr and
    183     * invalidate the resulting line until final_address is passed.
    184     */
    185     final_address = (void *)((size_t)i_addr + n_bytes - 1);
    186     i_addr = (void *)((size_t)i_addr & ~(_CPU_INST_CACHE_ALIGNMENT - 1));
    187     while( final_address > i_addr ) {
    188         _CPU_invalidate_1_inst_cache_line( i_addr );
    189         i_addr = (void *)((size_t)i_addr + _CPU_INST_CACHE_ALIGNMENT);
    190     }
     201#if defined(_CPU_INST_CACHE_ALIGNMENT)
     202  const void * final_address;
     203
     204 /*
     205  * Set i_addr to the beginning of the cache line; final_address indicates
     206  * the last address_t which needs to be invalidated. Increment i_addr and
     207  * invalidate the resulting line until final_address is passed.
     208  */
     209
     210  final_address = (void *)((size_t)i_addr + n_bytes - 1);
     211  i_addr = (void *)((size_t)i_addr & ~(_CPU_INST_CACHE_ALIGNMENT - 1));
     212  while( final_address > i_addr ) {
     213    _CPU_invalidate_1_inst_cache_line( i_addr );
     214    i_addr = (void *)((size_t)i_addr + _CPU_INST_CACHE_ALIGNMENT);
     215  }
     216#endif
    191217}
    192218
     
    199225rtems_invalidate_entire_inst_cache( void )
    200226{
    201    /*
    202     * Call the CPU-specific routine
    203     */
    204    _CPU_invalidate_entire_inst_cache();
     227#if defined(_CPU_INST_CACHE_ALIGNMENT)
     228 /*
     229  * Call the CPU-specific routine
     230  */
     231
     232 _CPU_invalidate_entire_inst_cache();
     233#endif
    205234}
    206235
     
    212241rtems_get_inst_cache_line_size( void )
    213242{
    214         return _CPU_INST_CACHE_ALIGNMENT;
     243#if defined(_CPU_INST_CACHE_ALIGNMENT)
     244  return _CPU_INST_CACHE_ALIGNMENT;
     245#else
     246  return 0;
     247#endif
    215248}
    216249
     
    223256rtems_freeze_inst_cache( void )
    224257{
    225         _CPU_freeze_inst_cache();
     258#if defined(_CPU_INST_CACHE_ALIGNMENT)
     259  _CPU_freeze_inst_cache();
     260#endif
    226261}
    227262
     
    232267void rtems_unfreeze_inst_cache( void )
    233268{
    234         _CPU_unfreeze_inst_cache();
     269#if defined(_CPU_INST_CACHE_ALIGNMENT)
     270  _CPU_unfreeze_inst_cache();
     271#endif
    235272}
    236273
     
    240277rtems_enable_inst_cache( void )
    241278{
    242         _CPU_enable_inst_cache();
     279#if defined(_CPU_INST_CACHE_ALIGNMENT)
     280  _CPU_enable_inst_cache();
     281#endif
    243282}
    244283
     
    248287rtems_disable_inst_cache( void )
    249288{
    250         _CPU_disable_inst_cache();
    251 }
    252 #endif
     289#if defined(_CPU_INST_CACHE_ALIGNMENT)
     290  _CPU_disable_inst_cache();
     291#endif
     292}
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