Ignore:
Timestamp:
Jun 13, 2000, 9:53:38 PM (21 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, 5, master
Children:
7d52750
Parents:
f0b11d63
Message:

Moved i386 and m68k cache management code to libcpu. Everything
now is an implementation of the prototypes in rtems/rtems/cache.h.
The libcpu/i386/wrapup directory is no longer needed.
The PowerPC needs this done to it.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • c/src/exec/score/cpu/i386/rtems/score/i386.h

    rf0b11d63 rcf1f72e  
    186186}
    187187
    188 /*
    189  * Disable the entire cache
    190  */
    191 void _CPU_disable_cache() {
    192   cr0 regCr0;
    193 
    194   regCr0.i = i386_get_cr0();
    195   regCr0.cr0.page_level_cache_disable = 1;
    196   regCr0.cr0.no_write_through = 1;
    197   i386_set_cr0( regCr0.i );
    198   rtems_flush_entire_data_cache();
    199 }
    200 
    201 /*
    202  * Enable the entire cache
    203  */
    204 static inline void _CPU_enable_cache() {
    205   cr0 regCr0;
    206 
    207   regCr0.i = i386_get_cr0();
    208   regCr0.cr0.page_level_cache_disable = 0;
    209   regCr0.cr0.no_write_through = 0;
    210   i386_set_cr0( regCr0.i );
    211   /*rtems_flush_entire_data_cache();*/
    212 }
    213 
    214 /*
    215  * CACHE MANAGER: The following functions are CPU-specific.
    216  * They provide the basic implementation for the rtems_* cache
    217  * management routines. If a given function has no meaning for the CPU,
    218  * it does nothing by default.
    219  *
    220  * FIXME: Definitions for I386_CACHE_ALIGNMENT are missing above for
    221  *        each CPU. The routines below should be implemented per CPU,
    222  *        to accomodate the capabilities of each.
    223  */
    224 
    225 /* FIXME: I don't belong here. */
    226 #define I386_CACHE_ALIGNMENT 16
    227 
    228 #if defined(I386_CACHE_ALIGNMENT)
    229 #define _CPU_DATA_CACHE_ALIGNMENT I386_CACHE_ALIGNMENT
    230 #define _CPU_INST_CACHE_ALIGNEMNT I386_CACHE_ALIGNMENT
    231 
    232 static inline void _CPU_flush_1_data_cache_line (const void * d_addr) {}
    233 static inline void _CPU_invalidate_1_data_cache_line (const void * d_addr) {}
    234 static inline void _CPU_freeze_data_cache (void) {}
    235 static inline void _CPU_unfreeze_data_cache (void) {}
    236 static inline void _CPU_invalidate_1_inst_cache_line const void * d_addr() {}
    237 static inline void _CPU_freeze_inst_cache (void) {}
    238 static inline void _CPU_unfreeze_inst_cache (void) {}
    239 
    240 static inline void _CPU_flush_entire_data_cache (
    241   const void * d_addr )
    242 {
    243   asm ("wbinvd");
    244 }
    245 static inline void _CPU_invalidate_entire_data_cache (
    246   const void * d_addr )
    247 {
    248   asm ("invd");
    249 }
    250 
    251 static inline void _CPU_enable_data_cache (
    252         void )
    253 {
    254         _CPU_enable_cache();
    255 }
    256 
    257 static inline void _CPU_disable_data_cache (
    258         void )
    259 {
    260         _CPU_disable_cache();
    261 }
    262 
    263 static inline void _CPU_invalidate_entire_inst_cache (
    264   const void * i_addr )
    265 {
    266   asm ("invd");
    267 }
    268 
    269 static inline void _CPU_enable_inst_cache (
    270         void )
    271 {
    272         _CPU_enable_cache();
    273 }
    274 
    275 static inline void _CPU_disable_inst_cache (
    276         void )
    277 {
    278         _CPU_disable_cache();
    279 }
    280 #endif
    281 
    282 
    283188/* routines */
    284189
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