Changeset ce90366 in rtems for doc


Ignore:
Timestamp:
Jul 2, 1997, 5:49:23 PM (24 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, 5, master
Children:
2e6d68c4
Parents:
563f7e0
Message:

updated to properly reflect powerpc

Location:
doc/supplements/powerpc
Files:
6 edited

Legend:

Unmodified
Added
Removed
  • doc/supplements/powerpc/callconv.t

    r563f7e0 rce90366  
    4949are both processor and compiler dependent.
    5050
     51RTEMS supports the Embedded Application Binary Interface (EABI)
     52calling convention.  Documentation for EABI is available by sending
     53a message with a subject line of "EABI" to eabi@@goth.sis.mot.com.
     54
    5155@ifinfo
    5256@node Calling Conventions Programming Model, Non-Floating Point Registers, Calling Conventions Introduction, Calling Conventions
     
    6266
    6367This section discusses the programming model for the
    64 SPARC architecture.
     68PowerPC architecture.
    6569
    6670@ifinfo
     
    6973@subsection Non-Floating Point Registers
    7074
    71 The SPARC architecture defines thirty-two
    72 non-floating point registers directly visible to the programmer.
    73 These are divided into four sets:
    74 
    75 @itemize @bullet
    76 @item input registers
    77 
    78 @item local registers
    79 
    80 @item output registers
    81 
    82 @item global registers
    83 @end itemize
    84 
    85 Each register is referred to by either two or three
    86 names in the SPARC reference manuals.  First, the registers are
    87 referred to as r0 through r31 or with the alternate notation
    88 r[0] through r[31].  Second, each register is a member of one of
    89 the four sets listed above.  Finally, some registers have an
    90 architecturally defined role in the programming model which
    91 provides an alternate name.  The following table describes the
    92 mapping between the 32 registers and the register sets:
    93 
    94 @ifset use-ascii
    95 @example
    96 @group
    97      +-----------------+----------------+------------------+
    98      | Register Number | Register Names |   Description    |
    99      +-----------------+----------------+------------------+
    100      |     0 - 7       |    g0 - g7     | Global Registers |
    101      +-----------------+----------------+------------------+
    102      |     8 - 15      |    o0 - o7     | Output Registers |
    103      +-----------------+----------------+------------------+
    104      |    16 - 23      |    l0 - l7     | Local Registers  |
    105      +-----------------+----------------+------------------+
    106      |    24 - 31      |    i0 - i7     | Input Registers  |
    107      +-----------------+----------------+------------------+
    108 @end group
    109 @end example
    110 @end ifset
    111 
    112 @ifset use-tex
    113 @sp 1
    114 @tex
    115 \centerline{\vbox{\offinterlineskip\halign{
    116 \vrule\strut#&
    117 \hbox to 1.75in{\enskip\hfil#\hfil}&
    118 \vrule#&
    119 \hbox to 1.75in{\enskip\hfil#\hfil}&
    120 \vrule#&
    121 \hbox to 1.75in{\enskip\hfil#\hfil}&
    122 \vrule#\cr
    123 \noalign{\hrule}
    124 &\bf Register Number &&\bf Register Names&&\bf Description&\cr\noalign{\hrule}
    125 &0 - 7&&g0 - g7&&Global Registers&\cr\noalign{\hrule}
    126 &8 - 15&&o0 - o7&&Output Registers&\cr\noalign{\hrule}
    127 &16 - 23&&l0 - l7&&Local Registers&\cr\noalign{\hrule}
    128 &24 - 31&&i0 - i7&&Input Registers&\cr\noalign{\hrule}
    129 }}\hfil}
    130 @end tex
    131 @end ifset
    132 
    133 @ifset use-html
    134 @html
    135 <CENTER>
    136   <TABLE COLS=3 WIDTH="80%" BORDER=2>
    137 <TR><TD ALIGN=center><STRONG>Register Number</STRONG></TD>
    138     <TD ALIGN=center><STRONG>Register Names</STRONG></TD>
    139     <TD ALIGN=center><STRONG>Description</STRONG></TD>
    140 <TR><TD ALIGN=center>0 - 7</TD>
    141     <TD ALIGN=center>g0 - g7</TD>
    142     <TD ALIGN=center>Global Registers</TD></TR>
    143 <TR><TD ALIGN=center>8 - 15</TD>
    144     <TD ALIGN=center>o0 - o7</TD>
    145     <TD ALIGN=center>Output Registers</TD></TR>
    146 <TR><TD ALIGN=center>16 - 23</TD>
    147     <TD ALIGN=center>l0 - l7</TD>
    148     <TD ALIGN=center>Local Registers</TD></TR>
    149 <TR><TD ALIGN=center>24 - 31</TD>
    150     <TD ALIGN=center>i0 - i7</TD>
    151     <TD ALIGN=center>Input Registers</TD></TR>
    152   </TABLE>
    153 </CENTER>
    154 @end html
    155 @end ifset
    156 
    157 As mentioned above, some of the registers serve
    158 defined roles in the programming model.  The following table
    159 describes the role of each of these registers:
     75The PowerPC architecture defines thirty-two non-floating point registers
     76directly visible to the programmer.  In thirty-two bit implementations, each
     77register is thirty-two bits wide.  In sixty-four bit implementations, each
     78register is sixty-four bits wide.
     79
     80These registers are referred to as @code{gpr0} to @code{gpr31}.
     81
     82Some of the registers serve defined roles in the EABI programming model. 
     83The following table describes the role of each of these registers:
    16084
    16185@ifset use-ascii
  • doc/supplements/powerpc/callconv.texi

    r563f7e0 rce90366  
    4949are both processor and compiler dependent.
    5050
     51RTEMS supports the Embedded Application Binary Interface (EABI)
     52calling convention.  Documentation for EABI is available by sending
     53a message with a subject line of "EABI" to eabi@@goth.sis.mot.com.
     54
    5155@ifinfo
    5256@node Calling Conventions Programming Model, Non-Floating Point Registers, Calling Conventions Introduction, Calling Conventions
     
    6266
    6367This section discusses the programming model for the
    64 SPARC architecture.
     68PowerPC architecture.
    6569
    6670@ifinfo
     
    6973@subsection Non-Floating Point Registers
    7074
    71 The SPARC architecture defines thirty-two
    72 non-floating point registers directly visible to the programmer.
    73 These are divided into four sets:
    74 
    75 @itemize @bullet
    76 @item input registers
    77 
    78 @item local registers
    79 
    80 @item output registers
    81 
    82 @item global registers
    83 @end itemize
    84 
    85 Each register is referred to by either two or three
    86 names in the SPARC reference manuals.  First, the registers are
    87 referred to as r0 through r31 or with the alternate notation
    88 r[0] through r[31].  Second, each register is a member of one of
    89 the four sets listed above.  Finally, some registers have an
    90 architecturally defined role in the programming model which
    91 provides an alternate name.  The following table describes the
    92 mapping between the 32 registers and the register sets:
    93 
    94 @ifset use-ascii
    95 @example
    96 @group
    97      +-----------------+----------------+------------------+
    98      | Register Number | Register Names |   Description    |
    99      +-----------------+----------------+------------------+
    100      |     0 - 7       |    g0 - g7     | Global Registers |
    101      +-----------------+----------------+------------------+
    102      |     8 - 15      |    o0 - o7     | Output Registers |
    103      +-----------------+----------------+------------------+
    104      |    16 - 23      |    l0 - l7     | Local Registers  |
    105      +-----------------+----------------+------------------+
    106      |    24 - 31      |    i0 - i7     | Input Registers  |
    107      +-----------------+----------------+------------------+
    108 @end group
    109 @end example
    110 @end ifset
    111 
    112 @ifset use-tex
    113 @sp 1
    114 @tex
    115 \centerline{\vbox{\offinterlineskip\halign{
    116 \vrule\strut#&
    117 \hbox to 1.75in{\enskip\hfil#\hfil}&
    118 \vrule#&
    119 \hbox to 1.75in{\enskip\hfil#\hfil}&
    120 \vrule#&
    121 \hbox to 1.75in{\enskip\hfil#\hfil}&
    122 \vrule#\cr
    123 \noalign{\hrule}
    124 &\bf Register Number &&\bf Register Names&&\bf Description&\cr\noalign{\hrule}
    125 &0 - 7&&g0 - g7&&Global Registers&\cr\noalign{\hrule}
    126 &8 - 15&&o0 - o7&&Output Registers&\cr\noalign{\hrule}
    127 &16 - 23&&l0 - l7&&Local Registers&\cr\noalign{\hrule}
    128 &24 - 31&&i0 - i7&&Input Registers&\cr\noalign{\hrule}
    129 }}\hfil}
    130 @end tex
    131 @end ifset
    132 
    133 @ifset use-html
    134 @html
    135 <CENTER>
    136   <TABLE COLS=3 WIDTH="80%" BORDER=2>
    137 <TR><TD ALIGN=center><STRONG>Register Number</STRONG></TD>
    138     <TD ALIGN=center><STRONG>Register Names</STRONG></TD>
    139     <TD ALIGN=center><STRONG>Description</STRONG></TD>
    140 <TR><TD ALIGN=center>0 - 7</TD>
    141     <TD ALIGN=center>g0 - g7</TD>
    142     <TD ALIGN=center>Global Registers</TD></TR>
    143 <TR><TD ALIGN=center>8 - 15</TD>
    144     <TD ALIGN=center>o0 - o7</TD>
    145     <TD ALIGN=center>Output Registers</TD></TR>
    146 <TR><TD ALIGN=center>16 - 23</TD>
    147     <TD ALIGN=center>l0 - l7</TD>
    148     <TD ALIGN=center>Local Registers</TD></TR>
    149 <TR><TD ALIGN=center>24 - 31</TD>
    150     <TD ALIGN=center>i0 - i7</TD>
    151     <TD ALIGN=center>Input Registers</TD></TR>
    152   </TABLE>
    153 </CENTER>
    154 @end html
    155 @end ifset
    156 
    157 As mentioned above, some of the registers serve
    158 defined roles in the programming model.  The following table
    159 describes the role of each of these registers:
     75The PowerPC architecture defines thirty-two non-floating point registers
     76directly visible to the programmer.  In thirty-two bit implementations, each
     77register is thirty-two bits wide.  In sixty-four bit implementations, each
     78register is sixty-four bits wide.
     79
     80These registers are referred to as @code{gpr0} to @code{gpr31}.
     81
     82Some of the registers serve defined roles in the EABI programming model. 
     83The following table describes the role of each of these registers:
    16084
    16185@ifset use-ascii
  • doc/supplements/powerpc/fatalerr.t

    r563f7e0 rce90366  
    4141the fatal_error_occurred directive when there is no user handler
    4242configured or the user handler returns control to RTEMS.  The
    43 default fatal error handler disables processor interrupts to
    44 level 15, places the error code in g1, and goes into an infinite
     43default fatal error handler disables all processor exceptions,
     44places the error code in r5, and goes into an infinite
    4545loop to simulate a halt processor instruction.
    4646
    47 
  • doc/supplements/powerpc/fatalerr.texi

    r563f7e0 rce90366  
    4141the fatal_error_occurred directive when there is no user handler
    4242configured or the user handler returns control to RTEMS.  The
    43 default fatal error handler disables processor interrupts to
    44 level 15, places the error code in g1, and goes into an infinite
     43default fatal error handler disables all processor exceptions,
     44places the error code in r5, and goes into an infinite
    4545loop to simulate a halt processor instruction.
    4646
    47 
  • doc/supplements/powerpc/memmodel.t

    r563f7e0 rce90366  
    3737@section Flat Memory Model
    3838
    39 The SPARC architecture supports a flat 32-bit address
     39The PowerPC architecture supports a variety of memory models.
     40RTEMS supports the PowerPC using a flat memory model with
     41paging disabled.  In this mode, the PowerPC automatically
     42converts every address from a logical to a physical address
     43each time it is used.  The PowerPC uses information provided
     44in the XXX to convert these addresses.
     45
     46Implementations of the PowerPC architecture may be thirty-two or sixty-four bit.
     47The PowerPC architecture supports a flat thirty-two or sixty-four bit address
    4048space with addresses ranging from 0x00000000 to 0xFFFFFFFF (4
    41 gigabytes).  Each address is represented by a 32-bit value and
    42 is byte addressable.  The address may be used to reference a
    43 single byte, half-word (2-bytes), word (4 bytes), or doubleword
    44 (8 bytes).  Memory accesses within this address space are
    45 performed in big endian fashion by the SPARC.  Memory accesses
    46 which are not properly aligned generate a "memory address not
    47 aligned" trap (type number 7).  The following table lists the
    48 alignment requirements for a variety of data accesses:
     49gigabytes) in thirty-two bit implementations or 0xFFFFFFFFFFFFFFFF
     50(XXX) in sixty-four bit implementations.  Each address is represented
     51by either a thirty-two bit or sixty-four bit value and is byte addressable. 
     52The address may be used to reference a single byte, half-word
     53(2-bytes), word (4 bytes), or in sixty-four bit implementations a
     54doubleword (8 bytes).  Memory accesses within the address space are
     55performed in big or little endian fashion by the PowerPC based
     56upon the current setting of the Little-endian mode enable bit (LE)
     57in the Machine State Register (MSR).  While the processor is in
     58big endian mode, memory accesses which are not properly aligned
     59generate an "alignment exception" (vector offset 0x00600).  In
     60little endian mode, the PowerPC architecture does not require
     61the processor to generate alignment exceptions.
     62
     63The following table lists the alignment requirements for a variety
     64of data accesses:
    4965
    5066@ifset use-ascii
     
    101117@end ifset
    102118
    103 Doubleword load and store operations must use a pair
    104 of registers as their source or destination.  This pair of
    105 registers must be an adjacent pair of registers with the first
    106 of the pair being even numbered.  For example, a valid
    107 destination for a doubleword load might be input registers 0 and
    108 1 (i0 and i1).  The pair i1 and i2 would be invalid.  [NOTE:
    109 Some assemblers for the SPARC do not generate an error if an odd
    110 numbered register is specified as the beginning register of the
    111 pair.  In this case, the assembler assumes that what the
    112 programmer meant was to use the even-odd pair which ends at the
    113 specified register.  This may or may not have been a correct
    114 assumption.]
     119Doubleword load and store operations are only available in
     120PowerPC CPU models which are sixty-four bit implementations.
    115121
    116 RTEMS does not support any SPARC Memory Management
     122RTEMS does not directly support any PowerPC Memory Management
    117123Units, therefore, virtual memory or segmentation systems
    118 involving the SPARC are not supported.
     124involving the PowerPC are not supported.
    119125
  • doc/supplements/powerpc/memmodel.texi

    r563f7e0 rce90366  
    3737@section Flat Memory Model
    3838
    39 The SPARC architecture supports a flat 32-bit address
     39The PowerPC architecture supports a variety of memory models.
     40RTEMS supports the PowerPC using a flat memory model with
     41paging disabled.  In this mode, the PowerPC automatically
     42converts every address from a logical to a physical address
     43each time it is used.  The PowerPC uses information provided
     44in the XXX to convert these addresses.
     45
     46Implementations of the PowerPC architecture may be thirty-two or sixty-four bit.
     47The PowerPC architecture supports a flat thirty-two or sixty-four bit address
    4048space with addresses ranging from 0x00000000 to 0xFFFFFFFF (4
    41 gigabytes).  Each address is represented by a 32-bit value and
    42 is byte addressable.  The address may be used to reference a
    43 single byte, half-word (2-bytes), word (4 bytes), or doubleword
    44 (8 bytes).  Memory accesses within this address space are
    45 performed in big endian fashion by the SPARC.  Memory accesses
    46 which are not properly aligned generate a "memory address not
    47 aligned" trap (type number 7).  The following table lists the
    48 alignment requirements for a variety of data accesses:
     49gigabytes) in thirty-two bit implementations or 0xFFFFFFFFFFFFFFFF
     50(XXX) in sixty-four bit implementations.  Each address is represented
     51by either a thirty-two bit or sixty-four bit value and is byte addressable. 
     52The address may be used to reference a single byte, half-word
     53(2-bytes), word (4 bytes), or in sixty-four bit implementations a
     54doubleword (8 bytes).  Memory accesses within the address space are
     55performed in big or little endian fashion by the PowerPC based
     56upon the current setting of the Little-endian mode enable bit (LE)
     57in the Machine State Register (MSR).  While the processor is in
     58big endian mode, memory accesses which are not properly aligned
     59generate an "alignment exception" (vector offset 0x00600).  In
     60little endian mode, the PowerPC architecture does not require
     61the processor to generate alignment exceptions.
     62
     63The following table lists the alignment requirements for a variety
     64of data accesses:
    4965
    5066@ifset use-ascii
     
    101117@end ifset
    102118
    103 Doubleword load and store operations must use a pair
    104 of registers as their source or destination.  This pair of
    105 registers must be an adjacent pair of registers with the first
    106 of the pair being even numbered.  For example, a valid
    107 destination for a doubleword load might be input registers 0 and
    108 1 (i0 and i1).  The pair i1 and i2 would be invalid.  [NOTE:
    109 Some assemblers for the SPARC do not generate an error if an odd
    110 numbered register is specified as the beginning register of the
    111 pair.  In this case, the assembler assumes that what the
    112 programmer meant was to use the even-odd pair which ends at the
    113 specified register.  This may or may not have been a correct
    114 assumption.]
     119Doubleword load and store operations are only available in
     120PowerPC CPU models which are sixty-four bit implementations.
    115121
    116 RTEMS does not support any SPARC Memory Management
     122RTEMS does not directly support any PowerPC Memory Management
    117123Units, therefore, virtual memory or segmentation systems
    118 involving the SPARC are not supported.
     124involving the PowerPC are not supported.
    119125
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