Changeset ce7d6e62 in rtems


Ignore:
Timestamp:
Mar 19, 2009, 10:49:55 AM (11 years ago)
Author:
Thomas Doerfler <Thomas.Doerfler@…>
Branches:
4.10, 4.11, master
Children:
8b074ee6
Parents:
434bc85b
Message:
  • start/start.S, include/hwreg_vals.h, startup/cpuinit.c: correct some init values for HSC_CM01 boards
Location:
c/src/lib/libbsp/powerpc/gen83xx
Files:
4 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/powerpc/gen83xx/ChangeLog

    r434bc85b rce7d6e62  
     12009-03-18      Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>
     2
     3        * start/start.S, include/hwreg_vals.h, startup/cpuinit.c:
     4        correct some init values for HSC_CM01 boards
     5
    162009-02-12      Joel Sherrill <joel.sherrill@oarcorp.com>
    27
  • c/src/lib/libbsp/powerpc/gen83xx/include/hwreg_vals.h

    r434bc85b rce7d6e62  
    208208#define LBLAWAR0_VAL   0x80000018
    209209#define LBLAWBAR1_VAL  (FPGA_CONFIG_START)
    210 #define LBLAWAR1_VAL   0x80000015
     210#define LBLAWAR1_VAL   0x80000018
    211211#define DDRLAWBAR0_VAL bsp_ram_start
    212212#define DDRLAWAR0_VAL  0x8000001B
     
    215215 * FIXME: decode bit settings
    216216 */
    217 #define BR0_VAL 0xFE001001
     217#define BR0_VAL (0xFE000000 | 0x01001)
    218218#define OR0_VAL 0xFE000E54
    219219// fpga config access range (UPM_A) (32 kByte)
    220220#define BR2_VAL (FPGA_CONFIG_START | 0x01881)
    221 #define OR2_VAL 0xFFF80100
     221#define OR2_VAL 0xFFFF9100
    222222
    223223// fpga register access range (UPM_B) (8 MByte)
    224224#define BR3_VAL (FPGA_REGISTER_START | 0x018A1)
    225 #define OR3_VAL 0xFF800100
    226 
    227 // fpga fifo access range (UPM_B) (8 MByte)
    228 #define BR4_VAL (FPGA_FIFO_START | 0x018A1)
    229 #define OR4_VAL 0xFF800100
     225#define OR3_VAL 0xFF801100
     226
     227// fpga fifo access range (UPM_C) (8 MByte)
     228#define BR4_VAL (FPGA_FIFO_START | 0x018C1)
     229#define OR4_VAL 0xFF801100
    230230
    231231/*
  • c/src/lib/libbsp/powerpc/gen83xx/start/start.S

    r434bc85b rce7d6e62  
    200200        SET_IMM_REGW r31,r30,OR3_OFF,OR3_VAL
    201201#endif
    202        
     202#ifdef BR4_VAL
     203        SET_IMM_REGW r31,r30,BR4_OFF,BR4_VAL
     204#endif
     205#ifdef OR4_VAL
     206        SET_IMM_REGW r31,r30,OR4_OFF,OR4_VAL
     207#endif
     208#ifdef BR5_VAL
     209        SET_IMM_REGW r31,r30,BR5_OFF,BR5_VAL
     210#endif
     211#ifdef OR5_VAL
     212        SET_IMM_REGW r31,r30,OR5_OFF,OR5_VAL
     213#endif
    203214        /*
    204215         * ROM startup: init SDRAM access window
  • c/src/lib/libbsp/powerpc/gen83xx/startup/cpuinit.c

    r434bc85b rce7d6e62  
    236236      (uint32_t) bsp_rom_size,
    237237    #endif /* HAS_UBOOT */
    238     false,
     238    true,
    239239    false,
    240240    false,
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