Changeset ce3bfb7 in rtems for c/src/lib/libcpu/sparc64/shared


Ignore:
Timestamp:
Aug 25, 2010, 8:33:25 PM (10 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.11, 5, master
Children:
f8b7c83d
Parents:
21e3de1
Message:

2010-08-25 Gedare Bloom <giddyup44@…>

PR 1688/libcpu

  • shared/score/interrupt.S: Fix bug in the sun4u _ISR_Dispatch code that ends up cloberring the global registers. It manifests primarily as a memory alignment error when the globals are used to read to/from memory.
File:
1 edited

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  • c/src/lib/libcpu/sparc64/shared/score/interrupt.S

    r21e3de1 rce3bfb7  
    358358
    359359    orcc     %o5, %g0, %g0   ! Is thread switch necessary?
    360     bnz      SYM(_ISR_Dispatch) ! yes, then invoke the dispatcher
     360    bz       simple_return   ! no, then do a simple return. otherwise fallthru
    361361    nop
    362362
     
    503503  ldx     [%sp + STACK_BIAS + ISF_G7_OFFSET], %g7    ! restore g7
    504504
    505 
    506 
     505  ! Assume the interrupted context is in TL 0 with GL 0 / normal globals.
     506  ! When tstate is restored at done/retry, the interrupted context is restored.
    507507  ! return to TL[1], GL[1], and restore TSTATE, TPC, and TNPC
    508508  wrpr  %g0, 1, %tl
     
    510510  ! return to GL=1 or AG
    511511#if defined(SUN4U)
    512     rdpr  %pstate, %g1
    513     andn  %g1, SPARC_PSTATE_AG_MASK, %g1
    514     wrpr  %g1, %g0, %pstate                 ! go to regular global
     512    rdpr  %pstate, %o1
     513    or  %o1, SPARC_PSTATE_AG_MASK, %o1
     514    wrpr  %o1, %g0, %pstate                 ! go to AG.
    515515#elif defined(SUN4V)
    516516  wrpr  %g0, 1, %gl
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