Changeset ce3bfb7 in rtems
- Timestamp:
- 08/25/10 20:33:25 (14 years ago)
- Branches:
- 4.11, 5, master
- Children:
- f8b7c83d
- Parents:
- 21e3de1
- Location:
- c/src/lib/libcpu/sparc64
- Files:
-
- 2 edited
Legend:
- Unmodified
- Added
- Removed
-
c/src/lib/libcpu/sparc64/ChangeLog
r21e3de1 rce3bfb7 1 2010-08-25 Gedare Bloom <giddyup44@yahoo.com> 2 3 PR 1688/libcpu 4 * shared/score/interrupt.S: Fix bug in the sun4u _ISR_Dispatch code 5 that ends up cloberring the global registers. It manifests primarily 6 as a memory alignment error when the globals are used to read to/from 7 memory. 8 1 9 2010-08-20 Gedare Bloom <giddyup44@yahoo.com> 2 10 -
c/src/lib/libcpu/sparc64/shared/score/interrupt.S
r21e3de1 rce3bfb7 358 358 359 359 orcc %o5, %g0, %g0 ! Is thread switch necessary? 360 b nz SYM(_ISR_Dispatch) ! yes, then invoke the dispatcher360 bz simple_return ! no, then do a simple return. otherwise fallthru 361 361 nop 362 362 … … 503 503 ldx [%sp + STACK_BIAS + ISF_G7_OFFSET], %g7 ! restore g7 504 504 505 506 505 ! Assume the interrupted context is in TL 0 with GL 0 / normal globals. 506 ! When tstate is restored at done/retry, the interrupted context is restored. 507 507 ! return to TL[1], GL[1], and restore TSTATE, TPC, and TNPC 508 508 wrpr %g0, 1, %tl … … 510 510 ! return to GL=1 or AG 511 511 #if defined(SUN4U) 512 rdpr %pstate, % g1513 andn %g1, SPARC_PSTATE_AG_MASK, %g1514 wrpr % g1, %g0, %pstate ! go to regular global512 rdpr %pstate, %o1 513 or %o1, SPARC_PSTATE_AG_MASK, %o1 514 wrpr %o1, %g0, %pstate ! go to AG. 515 515 #elif defined(SUN4V) 516 516 wrpr %g0, 1, %gl
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