Index: c/src/lib/libcpu/sh/ChangeLog
===================================================================
--- c/src/lib/libcpu/sh/ChangeLog	(revision 3adc6c13f3b8425d8f08595f409e33e09f33e26a)
+++ c/src/lib/libcpu/sh/ChangeLog	(revision cd53898a04224b347427bf563be867d439b64ac5)
@@ -1,2 +1,6 @@
+2005-03-14	Joel Sherrill <joel@OARcorp.com>
+
+	* sh7750/sci/sh4uart.c: Now compiles under gcc 4.x and reformatted.
+
 2005-01-07	Ralf Corsepius <ralf.corsepius@rtems.org>
 
Index: c/src/lib/libcpu/sh/sh7750/sci/sh4uart.c
===================================================================
--- c/src/lib/libcpu/sh/sh7750/sci/sh4uart.c	(revision 3adc6c13f3b8425d8f08595f409e33e09f33e26a)
+++ c/src/lib/libcpu/sh/sh7750/sci/sh4uart.c	(revision cd53898a04224b347427bf563be867d439b64ac5)
@@ -54,18 +54,18 @@
 sh4uart_init(sh4uart *uart, void *tty, int chn, int int_driven)
 {
-    if (uart == NULL)
-        return RTEMS_INVALID_ADDRESS;
-
-    if ((chn != SH4_SCI) && (chn != SH4_SCIF))
-                return RTEMS_INVALID_NUMBER;
-
-    uart->chn = chn;
-    uart->tty = tty;
-    uart->int_driven = int_driven;
+  if (uart == NULL)
+    return RTEMS_INVALID_ADDRESS;
+
+  if ((chn != SH4_SCI) && (chn != SH4_SCIF))
+    return RTEMS_INVALID_NUMBER;
+
+  uart->chn = chn;
+  uart->tty = tty;
+  uart->int_driven = int_driven;
 
 #if 0
-    sh4uart_poll_write(uart, "init", 4);
+  sh4uart_poll_write(uart, "init", 4);
 #endif
-    return RTEMS_SUCCESSFUL;
+  return RTEMS_SUCCESSFUL;
 }
 
@@ -84,63 +84,29 @@
 sh4uart_get_Pph(void)
 {
-    uint16_t   frqcr = *(volatile uint16_t*)SH7750_FRQCR;
-    uint32_t   Pph = CPU_CLOCK_RATE_HZ;
-
-    switch (frqcr & SH7750_FRQCR_IFC)
-    {
-        case SH7750_FRQCR_IFCDIV1:
-            break;
-
-        case SH7750_FRQCR_IFCDIV2:
-            Pph *= 2;
-            break;
-
-        case SH7750_FRQCR_IFCDIV3:
-            Pph *= 3;
-            break;
-
-        case SH7750_FRQCR_IFCDIV4:
-            Pph *= 4;
-            break;
-
-        case SH7750_FRQCR_IFCDIV6:
-            Pph *= 6;
-            break;
-
-        case SH7750_FRQCR_IFCDIV8:
-            Pph *= 8;
-            break;
-
-        default: /* unreachable */
-            break;
-    }
-
-    switch (frqcr & SH7750_FRQCR_PFC)
-    {
-        case SH7750_FRQCR_PFCDIV2:
-            Pph /= 2;
-            break;
-
-        case SH7750_FRQCR_PFCDIV3:
-            Pph /= 3;
-            break;
-
-        case SH7750_FRQCR_PFCDIV4:
-            Pph /= 4;
-            break;
-
-        case SH7750_FRQCR_PFCDIV6:
-            Pph /= 6;
-            break;
-
-        case SH7750_FRQCR_PFCDIV8:
-            Pph /= 8;
-            break;
-
-        default: /* unreachable */
-            break;
-    }
-
-    return Pph;
+  uint16_t   frqcr = *(volatile uint16_t*)SH7750_FRQCR;
+  uint32_t   Pph = CPU_CLOCK_RATE_HZ;
+
+  switch (frqcr & SH7750_FRQCR_IFC) {
+    case SH7750_FRQCR_IFCDIV1: break;
+    case SH7750_FRQCR_IFCDIV2: Pph *= 2; break;
+    case SH7750_FRQCR_IFCDIV3: Pph *= 3; break;
+    case SH7750_FRQCR_IFCDIV4: Pph *= 4; break;
+    case SH7750_FRQCR_IFCDIV6: Pph *= 6; break;
+    case SH7750_FRQCR_IFCDIV8: Pph *= 8; break;
+    default: /* unreachable */
+      break;
+  }
+
+  switch (frqcr & SH7750_FRQCR_PFC) {
+    case SH7750_FRQCR_PFCDIV2: Pph /= 2; break;
+    case SH7750_FRQCR_PFCDIV3: Pph /= 3; break;
+    case SH7750_FRQCR_PFCDIV4: Pph /= 4; break;
+    case SH7750_FRQCR_PFCDIV6: Pph /= 6; break;
+    case SH7750_FRQCR_PFCDIV8: Pph /= 8; break;
+    default: /* unreachable */
+      break;
+  }
+
+  return Pph;
 }
 
@@ -162,51 +128,57 @@
 sh4uart_set_baudrate(sh4uart *uart, speed_t baud)
 {
-    uint32_t   rate;
-    int16_t   div;
-    int n;
-    uint32_t   Pph = sh4uart_get_Pph();
-
-    switch (baud)
-    {
-        case B50:     rate = 50; break;
-        case B75:     rate = 75; break;
-        case B110:    rate = 110; break;
-        case B134:    rate = 134; break;
-        case B150:    rate = 150; break;
-        case B200:    rate = 200; break;
-        case B300:    rate = 300; break;
-        case B600:    rate = 600; break;
-        case B1200:   rate = 1200; break;
-        case B2400:   rate = 2400; break;
-        case B4800:   rate = 4800; break;
-        case B9600:   rate = 9600; break;
-        case B19200:  rate = 19200; break;
-        case B38400:  rate = 38400; break;
-        case B57600:  rate = 57600; break;
+  uint32_t   rate;
+  int16_t   div;
+  int n;
+  uint32_t   Pph = sh4uart_get_Pph();
+
+  switch (baud) {
+    case B50:     rate = 50; break;
+    case B75:     rate = 75; break;
+    case B110:    rate = 110; break;
+    case B134:    rate = 134; break;
+    case B150:    rate = 150; break;
+    case B200:    rate = 200; break;
+    case B300:    rate = 300; break;
+    case B600:    rate = 600; break;
+    case B1200:   rate = 1200; break;
+    case B2400:   rate = 2400; break;
+    case B4800:   rate = 4800; break;
+    case B9600:   rate = 9600; break;
+    case B19200:  rate = 19200; break;
+    case B38400:  rate = 38400; break;
+    case B57600:  rate = 57600; break;
 #ifdef B115200
-        case B115200: rate = 115200; break;
+    case B115200: rate = 115200; break;
 #endif
 #ifdef B230400
-        case B230400: rate = 230400; break;
+    case B230400: rate = 230400; break;
 #endif
-        default:      rate = 9600; break;
-    }
-
-    for (n = 0; n < 4; n++)
-    {
-        div = Pph / (32 * (1 << (2 * n)) * rate) - 1;
-        if (div < 0x100)
-            break;
-    }
-
-    /* Set default baudrate if specified baudrate is impossible */
-    if (n >= 4)
-        sh4uart_set_baudrate(uart, B9600);
-
-    SCSMR(uart->chn) &= ~SH7750_SCSMR_CKS;
-    SCSMR(uart->chn) |= n << SH7750_SCSMR_CKS_S;
-    SCBRR(uart->chn) = div;
-    /* Whait at least 1 bit interwal */
-    rtems_task_wake_after(RTEMS_MILLISECONDS_TO_TICKS(1000 / rate));
+    default:      rate = 9600; break;
+  }
+
+  for (n = 0; n < 4; n++) {
+    div = Pph / (32 * (1 << (2 * n)) * rate) - 1;
+    if (div < 0x100)
+      break;
+  }
+
+  /* Set default baudrate if specified baudrate is impossible */
+  if (n >= 4)
+    sh4uart_set_baudrate(uart, B9600);
+
+  if ( uart->chn == 1 ) {
+    volatile uint8_t *smr1 = (volatile uint8_t *)SH7750_SCSMR1;
+    *smr1 &= ~SH7750_SCSMR_CKS;
+    *smr1 |= n << SH7750_SCSMR_CKS_S;
+  } else { 
+    volatile uint16_t *smr2 = (volatile uint16_t *)SH7750_SCSMR2;
+    *smr2 &= ~SH7750_SCSMR_CKS;
+    *smr2 |= n << SH7750_SCSMR_CKS_S;
+  }
+
+  SCBRR(uart->chn) = div;
+  /* Wait at least 1 bit interwal */
+  rtems_task_wake_after(RTEMS_MILLISECONDS_TO_TICKS(1000 / rate));
 }
 
@@ -227,78 +199,93 @@
 sh4uart_reset(sh4uart *uart)
 {
-    register int chn;
-    register int int_driven;
-    rtems_status_code rc;
-
-    if (uart == NULL)
-        return RTEMS_INVALID_ADDRESS;
-
-    chn = uart->chn;
-    int_driven = uart->int_driven;
-
-    SCSCR(chn) = 0x0;       /* Is set properly at the end of this function */
-    SCSMR(chn) = 0x0;       /* 8-bit, non-parity, 1 stop bit, pf/1 clock */
-
-    if (chn == SH4_SCIF)
-        SCFCR2 = SH7750_SCFCR2_TFRST | SH7750_SCFCR2_RFRST |
-                SH7750_SCFCR2_RTRG_1 | SH7750_SCFCR2_TTRG_4;
-
-    if (chn == SH4_SCI)
-        SCSPTR1 = int_driven ? 0x0 : SH7750_SCSPTR1_EIO;
-    else
-        SCSPTR2 = SH7750_SCSPTR2_RTSDT;
-
-    if (int_driven)
-    {
-        uint16_t   ipr;
-
-        if (chn == SH4_SCI)
-        {
-            ipr = IPRB;
-            ipr &= ~SH7750_IPRB_SCI1;
-            ipr |= SH4_UART_INTERRUPT_LEVEL << SH7750_IPRB_SCI1_S;
-            IPRB = ipr;
-
-            rc = rtems_interrupt_catch(sh4uart1_interrupt_transmit,
-                    SH7750_EVT_TO_NUM(SH7750_EVT_SCI_TXI),
-                    &uart->old_handler_transmit);
-            if (rc != RTEMS_SUCCESSFUL)
-                return rc;
-            rc = rtems_interrupt_catch(sh4uart1_interrupt_receive,
-                    SH7750_EVT_TO_NUM(SH7750_EVT_SCI_RXI),
-                    &uart->old_handler_receive);
-            if (rc != RTEMS_SUCCESSFUL)
-                return rc;
-        }
-        else
-        {
-            ipr = IPRC;
-            ipr &= ~SH7750_IPRC_SCIF;
-            ipr |= SH4_UART_INTERRUPT_LEVEL << SH7750_IPRC_SCIF_S;
-            IPRC = ipr;
-
-            rc = rtems_interrupt_catch(sh4uart2_interrupt_transmit,
-                    SH7750_EVT_TO_NUM(SH7750_EVT_SCIF_TXI),
-                    &uart->old_handler_transmit);
-            if (rc != RTEMS_SUCCESSFUL)
-                return rc;
-            rc = rtems_interrupt_catch(sh4uart2_interrupt_receive,
-                    SH7750_EVT_TO_NUM(SH7750_EVT_SCIF_RXI),
-                    &uart->old_handler_receive);
-            if (rc != RTEMS_SUCCESSFUL)
-                return rc;
-        }
-        uart->tx_buf = NULL;
-        uart->tx_ptr = uart->tx_buf_len = 0;
+  register int chn;
+  register int int_driven;
+  rtems_status_code rc;
+  uint16_t tmp;
+
+  if (uart == NULL)
+    return RTEMS_INVALID_ADDRESS;
+
+  chn = uart->chn;
+  int_driven = uart->int_driven;
+
+  if ( chn == 1 ) {
+    volatile uint8_t *scr1 = (volatile uint8_t *)SH7750_SCSCR1;
+    volatile uint8_t *smr1 = (volatile uint8_t *)SH7750_SCSMR1;
+    *scr1 = 0x0;       /* Is set properly at the end of this function */
+    *smr1 = 0x0;       /* 8-bit, non-parity, 1 stop bit, pf/1 clock */
+  } else {
+    volatile uint16_t *scr2 = (volatile uint16_t *)SH7750_SCSCR2;
+    volatile uint16_t *smr2 = (volatile uint16_t *)SH7750_SCSMR2;
+    *scr2 = 0x0;       /* Is set properly at the end of this function */
+    *smr2 = 0x0;       /* 8-bit, non-parity, 1 stop bit, pf/1 clock */
+  }
+
+  if (chn == SH4_SCIF)
+    SCFCR2 = SH7750_SCFCR2_TFRST | SH7750_SCFCR2_RFRST |
+             SH7750_SCFCR2_RTRG_1 | SH7750_SCFCR2_TTRG_4;
+
+  if (chn == SH4_SCI)
+    SCSPTR1 = int_driven ? 0x0 : SH7750_SCSPTR1_EIO;
+  else
+    SCSPTR2 = SH7750_SCSPTR2_RTSDT;
+
+  if (int_driven) {
+    uint16_t   ipr;
+
+    if (chn == SH4_SCI) {
+      ipr = IPRB;
+      ipr &= ~SH7750_IPRB_SCI1;
+      ipr |= SH4_UART_INTERRUPT_LEVEL << SH7750_IPRB_SCI1_S;
+      IPRB = ipr;
+
+      rc = rtems_interrupt_catch(sh4uart1_interrupt_transmit,
+                                 SH7750_EVT_TO_NUM(SH7750_EVT_SCI_TXI),
+                                 &uart->old_handler_transmit);
+      if (rc != RTEMS_SUCCESSFUL)
+        return rc;
+
+      rc = rtems_interrupt_catch(sh4uart1_interrupt_receive,
+                                 SH7750_EVT_TO_NUM(SH7750_EVT_SCI_RXI),
+                                 &uart->old_handler_receive);
+      if (rc != RTEMS_SUCCESSFUL)
+        return rc;
+    } else {
+      ipr = IPRC;
+      ipr &= ~SH7750_IPRC_SCIF;
+      ipr |= SH4_UART_INTERRUPT_LEVEL << SH7750_IPRC_SCIF_S;
+      IPRC = ipr;
+
+      rc = rtems_interrupt_catch(sh4uart2_interrupt_transmit,
+                                 SH7750_EVT_TO_NUM(SH7750_EVT_SCIF_TXI),
+                                 &uart->old_handler_transmit);
+      if (rc != RTEMS_SUCCESSFUL)
+        return rc;
+      rc = rtems_interrupt_catch(sh4uart2_interrupt_receive,
+                                 SH7750_EVT_TO_NUM(SH7750_EVT_SCIF_RXI),
+                                 &uart->old_handler_receive);
+      if (rc != RTEMS_SUCCESSFUL)
+        return rc;
     }
-
-    sh4uart_set_baudrate(uart, B38400); /* debug defaults (unfortunately,
-                                           it is differ to termios default */
-
-    SCSCR(chn) = SH7750_SCSCR_TE | SH7750_SCSCR_RE |
-            (chn == SH4_SCI ? 0x0 : SH7750_SCSCR2_REIE) |
-            (int_driven ? (SH7750_SCSCR_RIE | SH7750_SCSCR_TIE) : 0x0);
-
-    return RTEMS_SUCCESSFUL;
+    uart->tx_buf = NULL;
+    uart->tx_ptr = uart->tx_buf_len = 0;
+  }
+
+  sh4uart_set_baudrate(uart, B38400); /* debug defaults (unfortunately,
+                                         it is differ to termios default */
+
+  tmp = SH7750_SCSCR_TE | SH7750_SCSCR_RE |
+          (chn == SH4_SCI ? 0x0 : SH7750_SCSCR2_REIE) |
+          (int_driven ? (SH7750_SCSCR_RIE | SH7750_SCSCR_TIE) : 0x0);
+
+  if ( chn == 1 ) {
+    volatile uint8_t *scr = (volatile uint8_t *)SH7750_SCSCR1;
+    *scr = tmp;
+  } else {
+    volatile uint16_t *scr = (volatile uint16_t *)SH7750_SCSCR2;
+    *scr = tmp;
+  }
+
+  return RTEMS_SUCCESSFUL;
 }
 
@@ -318,26 +305,30 @@
 sh4uart_disable(sh4uart *uart, int disable_port)
 {
-    rtems_status_code rc;
-
-    if (disable_port)
-        SCSCR(uart->chn) &= ~(SH7750_SCSCR_TE | SH7750_SCSCR_RE);
-
-    if (uart->int_driven)
-    {
-        rc = rtems_interrupt_catch(uart->old_handler_transmit,
-                uart->chn == SH4_SCI ?
-                        SH7750_EVT_SCI_TXI : SH7750_EVT_SCIF_TXI,
-                NULL);
-        if (rc != RTEMS_SUCCESSFUL)
-            return rc;
-        rc = rtems_interrupt_catch(uart->old_handler_receive,
-                uart->chn == SH4_SCI ?
-                        SH7750_EVT_SCI_RXI : SH7750_EVT_SCIF_RXI,
-                NULL);
-        if (rc != RTEMS_SUCCESSFUL)
-            return rc;
+  rtems_status_code rc;
+
+  if (disable_port) {
+    if ( uart->chn == 1 ) {
+      volatile uint8_t *scr = (volatile uint8_t *)SH7750_SCSCR1;
+      *scr &= ~(SH7750_SCSCR_TE | SH7750_SCSCR_RE);
+    } else {
+      volatile uint16_t *scr = (volatile uint16_t *)SH7750_SCSCR2;
+      *scr &= ~(SH7750_SCSCR_TE | SH7750_SCSCR_RE);
     }
-
-    return RTEMS_SUCCESSFUL;
+  }
+
+  if (uart->int_driven) {
+    rc = rtems_interrupt_catch(uart->old_handler_transmit,
+           uart->chn == SH4_SCI ?  SH7750_EVT_SCI_TXI : SH7750_EVT_SCIF_TXI,
+           NULL);
+    if (rc != RTEMS_SUCCESSFUL)
+      return rc;
+    rc = rtems_interrupt_catch(uart->old_handler_receive,
+           uart->chn == SH4_SCI ?  SH7750_EVT_SCI_RXI : SH7750_EVT_SCIF_RXI,
+           NULL);
+    if (rc != RTEMS_SUCCESSFUL)
+      return rc;
+  }
+
+  return RTEMS_SUCCESSFUL;
 }
 
@@ -357,58 +348,66 @@
 sh4uart_set_attributes(sh4uart *uart, const struct termios *t)
 {
-    int level;
-    speed_t baud;
-    uint16_t   smr;
-
-    smr = (uint16_t)(*(uint8_t*)SH7750_SCSMR(uart->chn));
-
-    baud = cfgetospeed(t);
-
-    /* Set flow control XXX*/
-    if ((t->c_cflag & CRTSCTS) != 0)
-    {
-    }
-
-    /* Set character size -- only 7 or 8 bit */
-    switch (t->c_cflag & CSIZE)
-    {
-        case CS5:
-        case CS6:
-        case CS7: smr |= SH7750_SCSMR_CHR_7; break;
-        case CS8: smr &= ~SH7750_SCSMR_CHR_7; break;
-    }
+  int level;
+  speed_t baud;
+  uint16_t   smr;
+
+  smr = (uint16_t)(*(uint8_t*)SH7750_SCSMR(uart->chn));
+
+  baud = cfgetospeed(t);
+
+  /* Set flow control XXX*/
+  if ((t->c_cflag & CRTSCTS) != 0) {
+  }
+
+  /* Set character size -- only 7 or 8 bit */
+  switch (t->c_cflag & CSIZE) {
+    case CS5:
+    case CS6:
+    case CS7: smr |= SH7750_SCSMR_CHR_7; break;
+    case CS8: smr &= ~SH7750_SCSMR_CHR_7; break;
+  }
 
     /* Set number of stop bits */
-    if ((t->c_cflag & CSTOPB) != 0)
-        smr |= SH7750_SCSMR_STOP_2;
+  if ((t->c_cflag & CSTOPB) != 0)
+    smr |= SH7750_SCSMR_STOP_2;
+  else
+    smr &= ~SH7750_SCSMR_STOP_2;
+
+  /* Set parity mode */
+  if ((t->c_cflag & PARENB) != 0) {
+    smr |= SH7750_SCSMR_PE;
+    if ((t->c_cflag & PARODD) != 0)
+       smr |= SH7750_SCSMR_PM_ODD;
     else
-        smr &= ~SH7750_SCSMR_STOP_2;
-
-    /* Set parity mode */
-    if ((t->c_cflag & PARENB) != 0)
-    {
-        smr |= SH7750_SCSMR_PE;
-        if ((t->c_cflag & PARODD) != 0)
-           smr |= SH7750_SCSMR_PM_ODD;
-        else
-           smr &= ~SH7750_SCSMR_PM_ODD;
-    }
-    else
-        smr &= ~SH7750_SCSMR_PE;
-
-    rtems_interrupt_disable(level);
-    /* wait untill all data is transmitted */
-    rtems_task_wake_after(RTEMS_MILLISECONDS_TO_TICKS(100));
-    /* disable operations */
-    SCSCR(uart->chn) &= ~(SH7750_SCSCR_TE | SH7750_SCSCR_RE);
-
+       smr &= ~SH7750_SCSMR_PM_ODD;
+  } else
+    smr &= ~SH7750_SCSMR_PE;
+
+  rtems_interrupt_disable(level);
+  /* wait untill all data is transmitted */
+  /* XXX JOEL says this is broken -- interrupts are OFF so NO ticks  */
+  rtems_task_wake_after(RTEMS_MILLISECONDS_TO_TICKS(100));
+
+  if ( uart->chn == 1 ) {
+    volatile uint8_t *scrP = (volatile uint8_t *)SH7750_SCSCR1;
+    volatile uint8_t *smrP = (volatile uint8_t *)SH7750_SCSMR1;
+
+    *scrP &= ~(SH7750_SCSCR_TE | SH7750_SCSCR_RE); /* disable operations */
     sh4uart_set_baudrate(uart, baud);
-    SCSMR(uart->chn) = (uint8_t)smr;
-
-    /* enable operations */
-    SCSCR(uart->chn) |= SH7750_SCSCR_TE | SH7750_SCSCR_RE;
-    rtems_interrupt_enable(level);
-
-    return RTEMS_SUCCESSFUL;
+    *smrP = (uint8_t)smr;
+    *scrP |= SH7750_SCSCR_TE | SH7750_SCSCR_RE;    /* enable operations */
+  } else {
+    volatile uint16_t *scrP = (volatile uint16_t *)SH7750_SCSCR2;
+    volatile uint16_t *smrP = (volatile uint16_t *)SH7750_SCSMR2;
+
+    *scrP &= ~(SH7750_SCSCR_TE | SH7750_SCSCR_RE); /* disable operations */
+    sh4uart_set_baudrate(uart, baud);
+    *smrP = (uint8_t)smr;
+    *scrP |= SH7750_SCSCR_TE | SH7750_SCSCR_RE;    /* enable operations */
+  }
+
+  rtems_interrupt_enable(level);
+
+  return RTEMS_SUCCESSFUL;
 }
 
@@ -426,17 +425,12 @@
 sh4uart_handle_error(sh4uart *uart)
 {
-#if 0
-    int status_reg = SCSSR(uart->chn);
-#endif
-
-    if(uart->chn == SH4_SCI)
-    {
-        SCSSR1 &= ~(SH7750_SCSSR1_ORER | SH7750_SCSSR1_FER | SH7750_SCSSR1_PER);
-    }
-    else
-    {
-        SCSSR2 &= ~(SH7750_SCSSR2_ER | SH7750_SCSSR2_BRK | SH7750_SCSSR2_FER);
-        SCLSR2 &= ~(SH7750_SCLSR2_ORER);
-    }
+  if (uart->chn == SH4_SCI) {
+    volatile uint8_t *scr = (volatile uint8_t *)SH7750_SCSCR1;
+    *scr &= ~(SH7750_SCSSR1_ORER | SH7750_SCSSR1_FER | SH7750_SCSSR1_PER);
+  } else {
+    volatile uint16_t *scr = (volatile uint16_t *)SH7750_SCSCR2;
+    *scr &= ~(SH7750_SCSSR2_ER | SH7750_SCSSR2_BRK | SH7750_SCSSR2_FER);
+    *scr &= ~(SH7750_SCLSR2_ORER);
+  }
 }
 
@@ -460,72 +454,66 @@
 sh4uart_poll_read(sh4uart *uart)
 {
-    int chn = uart->chn;
-    int error_occured = 0;
-    int parity_error = 0;
-    int break_occured = 0;
-    int ch;
-
-    if (uart->parerr_mark_flag == 1)
-    {
-        uart->parerr_mark_flag = 0;
-        return 0;
+  int chn = uart->chn;
+  int error_occured = 0;
+  int parity_error = 0;
+  int break_occured = 0;
+  int ch;
+
+  if (uart->parerr_mark_flag == 1) {
+    uart->parerr_mark_flag = 0;
+    return 0;
+  }
+
+  if (chn == SH4_SCI) {
+    if ((SCSSR1 & (SH7750_SCSSR1_PER | SH7750_SCSSR1_FER |
+                 SH7750_SCSSR1_ORER)) != 0) {
+      error_occured = 1;
+      if (SCSSR1 & (SH7750_SCSSR1_PER | SH7750_SCSSR1_FER))
+        parity_error = 1;
+      sh4uart_handle_error(uart);
     }
-
-    if (chn == SH4_SCI)
-    {
-        if ((SCSSR1 & (SH7750_SCSSR1_PER | SH7750_SCSSR1_FER |
-                     SH7750_SCSSR1_ORER)) != 0)
-        {
-            error_occured = 1;
-            if (SCSSR1 & (SH7750_SCSSR1_PER | SH7750_SCSSR1_FER))
-                parity_error = 1;
-            sh4uart_handle_error(uart);
-        }
-        if ((SCSSR1 & SH7750_SCSSR1_RDRF) == 0)
-            return -1;
+    if ((SCSSR1 & SH7750_SCSSR1_RDRF) == 0)
+      return -1;
+  } else {
+    if ((SCSSR2 & (SH7750_SCSSR2_ER | SH7750_SCSSR2_DR |
+                 SH7750_SCSSR2_BRK)) != 0 ||
+            (SCLSR2 & SH7750_SCLSR2_ORER) != 0) {
+      error_occured = 1;
+      if (SCSSR2 & (SH7750_SCSSR1_PER | SH7750_SCSSR1_FER))
+        parity_error = 1;
+      if (SCSSR2 & SH7750_SCSSR2_BRK)
+        break_occured = 1;
+      sh4uart_handle_error(uart);
     }
+    if ((SCSSR2 & SH7750_SCSSR2_RDF) == 0)
+      return -1;
+  }
+
+  if (parity_error && !(uart->c_iflag & IGNPAR)) {
+    if (uart->c_iflag & PARMRK) {
+      uart->parerr_mark_flag = 1;
+      return 0xff;
+    } else
+      return 0;
+  }
+
+  if (break_occured && !(uart->c_iflag & BRKINT)) {
+    if (uart->c_iflag & IGNBRK)
+      return 0;
     else
-    {
-        if ((SCSSR2 & (SH7750_SCSSR2_ER | SH7750_SCSSR2_DR |
-                     SH7750_SCSSR2_BRK)) != 0 ||
-                (SCLSR2 & SH7750_SCLSR2_ORER) != 0)
-        {
-            error_occured = 1;
-            if (SCSSR2 & (SH7750_SCSSR1_PER | SH7750_SCSSR1_FER))
-                parity_error = 1;
-            if (SCSSR2 & SH7750_SCSSR2_BRK)
-                break_occured = 1;
-            sh4uart_handle_error(uart);
-        }
-        if ((SCSSR2 & SH7750_SCSSR2_RDF) == 0)
-            return -1;
-    }
-
-    if (parity_error && !(uart->c_iflag & IGNPAR))
-    {
-        if (uart->c_iflag & PARMRK)
-        {
-            uart->parerr_mark_flag = 1;
-            return 0xff;
-        }
-        else
-            return 0;
-    }
-
-    if (break_occured && !(uart->c_iflag & BRKINT))
-    {
-        if (uart->c_iflag & IGNBRK)
-            return 0;
-        else
-            return 0;   /* XXX -- SIGINT */
-    }
-
-    ch = SCRDR(chn);
-    if (uart->chn == SH4_SCI)
-        SCSSR1 &= ~SH7750_SCSSR1_RDRF;
-    else
-        SCSSR2 &= ~SH7750_SCSSR2_RDF;
-
-    return ch;
+      return 0;   /* XXX -- SIGINT */
+  }
+
+  ch = SCRDR(chn);
+
+  if (uart->chn == SH4_SCI) {
+    volatile uint8_t *scr = (volatile uint8_t *)SH7750_SCSCR1;
+    *scr &= ~SH7750_SCSSR1_RDRF;
+  } else {
+    volatile uint16_t *scr = (volatile uint16_t *)SH7750_SCSCR2;
+    *scr &= ~SH7750_SCSSR2_RDF;
+  }
+
+  return ch;
 }
 
@@ -545,35 +533,31 @@
 sh4uart_poll_write(sh4uart *uart, const char *buf, int len)
 {
-    while (len)
-    {
-        if (uart->chn == SH4_SCI)
-        {
-            while ((SCSSR1 & SH7750_SCSSR1_TDRE) != 0)
-            {
-                SCTDR1 = *buf++;
-                len--;
-                SCSSR1 &= ~SH7750_SCSSR1_TDRE;
-            }
+  volatile uint8_t *ssr1 = (volatile uint8_t *)SH7750_SCSSR1;
+  volatile uint16_t *ssr2 = (volatile uint16_t *)SH7750_SCSSR2;
+
+  while (len) {
+    if (uart->chn == SH4_SCI) {
+      while ((SCSSR1 & SH7750_SCSSR1_TDRE) != 0) {
+          SCTDR1 = *buf++;
+          len--;
+          *ssr1 &= ~SH7750_SCSSR1_TDRE;
+      }
+    } else {
+      while ((SCSSR2 & SH7750_SCSSR2_TDFE) != 0) {
+        int i;
+        for (i = 0;
+                i < 16 - TRANSMIT_TRIGGER_VALUE(SCFCR2 &
+                    SH7750_SCFCR2_TTRG);
+                i++) {
+            SCTDR2 = *buf++;
+            len--;
         }
-        else
-        {
-            while ((SCSSR2 & SH7750_SCSSR2_TDFE) != 0)
-            {
-                int i;
-                for (i = 0;
-                        i < 16 - TRANSMIT_TRIGGER_VALUE(SCFCR2 &
-                            SH7750_SCFCR2_TTRG);
-                        i++)
-                {
-                    SCTDR2 = *buf++;
-                    len--;
-                }
-                while ((SCSSR2 & SH7750_SCSSR2_TDFE) == 0 ||
-                        (SCSSR2 & SH7750_SCSSR2_TEND) == 0);
-                    SCSSR2 &= ~(SH7750_SCSSR1_TDRE | SH7750_SCSSR2_TEND);
-            }
-        }
+        while ((SCSSR2 & SH7750_SCSSR2_TDFE) == 0 ||
+                (SCSSR2 & SH7750_SCSSR2_TEND) == 0);
+            *ssr2 &= ~(SH7750_SCSSR1_TDRE | SH7750_SCSSR2_TEND);
+      }
     }
-    return 0;
+  }
+  return 0;
 }
 
@@ -594,46 +578,37 @@
 sh4uart1_interrupt_receive(rtems_vector_number vec)
 {
-    register int bp = 0;
-    char buf[32];
-
-    /* Find UART descriptor from vector number */
-    sh4uart *uart = &sh4_uarts[0];
-
-    while (1)
-    {
-        if ((bp < sizeof(buf) - 1) && ((SCSSR1 & SH7750_SCSSR1_RDRF) != 0))
-        {
-            /* Receive character and handle frame/parity errors */
-            if ((SCSSR1 & (SH7750_SCSSR1_PER | SH7750_SCSSR1_FER |
-                            SH7750_SCSSR1_ORER)) != 0)
-            {
-                if (SCSSR1 & (SH7750_SCSSR1_PER | SH7750_SCSSR1_FER))
-                {
-                    if(!(uart->c_iflag & IGNPAR))
-                    {
-                        if (uart->c_iflag & PARMRK)
-                        {
-                            buf[bp++] = 0xff;
-                            buf[bp++] = 0x00;
-                        }
-                        else
-                            buf[bp++] = 0x00;
-                    }
-                    else
-                        buf[bp++] = SCRDR1;
-                }
-                sh4uart_handle_error(uart);
-            }
-            else
-                buf[bp++] = SCRDR1;
-            SCSSR1 &= ~SH7750_SCSSR1_RDRF;
-        }
-        else
-        {
-            if (bp != 0)
-                rtems_termios_enqueue_raw_characters(uart->tty, buf, bp);
-            break;
-        }
+  register int bp = 0;
+  char buf[32];
+  volatile uint8_t *ssr1 = (volatile uint8_t *)SH7750_SCSSR1;
+
+
+  /* Find UART descriptor from vector number */
+  sh4uart *uart = &sh4_uarts[0];
+
+  while (1) {
+    if ((bp < sizeof(buf) - 1) && ((SCSSR1 & SH7750_SCSSR1_RDRF) != 0)) {
+      /* Receive character and handle frame/parity errors */
+      if ((SCSSR1 & (SH7750_SCSSR1_PER | SH7750_SCSSR1_FER |
+                      SH7750_SCSSR1_ORER)) != 0) {
+        if (SCSSR1 & (SH7750_SCSSR1_PER | SH7750_SCSSR1_FER)) {
+            if (!(uart->c_iflag & IGNPAR)) {
+              if (uart->c_iflag & PARMRK) {
+                buf[bp++] = 0xff;
+                buf[bp++] = 0x00;
+              } else
+                buf[bp++] = 0x00;
+            } else
+              buf[bp++] = SCRDR1;
+          }
+          sh4uart_handle_error(uart);
+      } else
+          buf[bp++] = SCRDR1;
+      *ssr1 &= ~SH7750_SCSSR1_RDRF;
+    } else {
+      if (bp != 0)
+        rtems_termios_enqueue_raw_characters(uart->tty, buf, bp);
+      break;
     }
+  }
 }
 
@@ -651,55 +626,45 @@
 sh4uart2_interrupt_receive(rtems_vector_number vec)
 {
-    register int bp = 0;
-    char buf[32];
-
-    /* Find UART descriptor from vector number */
-    sh4uart *uart = &sh4_uarts[1];
-
-    while (1)
-    {
-        if ((bp < sizeof(buf) - 1) && ((SCSSR2 & SH7750_SCSSR2_RDF) != 0))
-        {
-            if ((SCSSR2 & (SH7750_SCSSR2_ER | SH7750_SCSSR2_DR |
-                            SH7750_SCSSR2_BRK)) != 0 ||
-                    (SH7750_SCLSR2 & SH7750_SCLSR2_ORER) != 0)
-            {
-                if (SCSSR2 & SH7750_SCSSR2_ER)
-                {
-                    if(!(uart->c_iflag & IGNPAR))
-                    {
-                        if (uart->c_iflag & PARMRK)
-                        {
-                            buf[bp++] = 0xff;
-                            buf[bp++] = 0x00;
-                        }
-                        else
-                            buf[bp++] = 0x00;
-                    }
-                    else
-                        buf[bp++] = SCRDR1;
-                }
-
-                if (SCSSR2 & SH7750_SCSSR2_BRK)
-                {
-                    if (uart->c_iflag & IGNBRK)
-                        buf[bp++] = 0x00;
-                    else
-                        buf[bp++] = 0x00;   /* XXX -- SIGINT */
-                }
-
-                sh4uart_handle_error(uart);
-            }
-            else
-                buf[bp++] = SCRDR1;
-            SCSSR2 &= ~SH7750_SCSSR2_RDF;
+  register int bp = 0;
+  char buf[32];
+  volatile uint16_t *ssr2 = (volatile uint16_t *)SH7750_SCSSR2;
+
+
+  /* Find UART descriptor from vector number */
+  sh4uart *uart = &sh4_uarts[1];
+
+  while (1) {
+    if ((bp < sizeof(buf) - 1) && ((SCSSR2 & SH7750_SCSSR2_RDF) != 0)) {
+      if ((SCSSR2 & (SH7750_SCSSR2_ER | SH7750_SCSSR2_DR |
+                      SH7750_SCSSR2_BRK)) != 0 ||
+              (SH7750_SCLSR2 & SH7750_SCLSR2_ORER) != 0) {
+        if (SCSSR2 & SH7750_SCSSR2_ER) {
+          if (!(uart->c_iflag & IGNPAR)) {
+            if (uart->c_iflag & PARMRK) {
+              buf[bp++] = 0xff;
+              buf[bp++] = 0x00;
+            } else
+              buf[bp++] = 0x00;
+          } else
+              buf[bp++] = SCRDR1;
         }
-        else
-        {
-            if (bp != 0)
-                rtems_termios_enqueue_raw_characters(uart->tty, buf, bp);
-            break;
+
+        if (SCSSR2 & SH7750_SCSSR2_BRK) {
+          if (uart->c_iflag & IGNBRK)
+            buf[bp++] = 0x00;
+          else
+            buf[bp++] = 0x00;   /* XXX -- SIGINT */
         }
+
+        sh4uart_handle_error(uart);
+      } else
+        buf[bp++] = SCRDR1;
+      *ssr2 &= ~SH7750_SCSSR2_RDF;
+    } else {
+      if (bp != 0)
+        rtems_termios_enqueue_raw_characters(uart->tty, buf, bp);
+      break;
     }
+  }
 }
 
@@ -718,28 +683,27 @@
 sh4uart1_interrupt_transmit(rtems_vector_number vec)
 {
-    /* Find UART descriptor from vector number */
-    sh4uart *uart = &sh4_uarts[0];
-
-    if (uart->tx_buf != NULL && uart->tx_ptr < uart->tx_buf_len)
-    {
-        while ((SCSSR1 & SH7750_SCSSR1_TDRE) != 0 &&
-                uart->tx_ptr < uart->tx_buf_len)
-        {
-            SCTDR1 = uart->tx_buf[uart->tx_ptr++];
-            SCSSR1 &= ~SH7750_SCSSR1_TDRE;
-        }
+  volatile uint8_t *scr1 = (volatile uint8_t *)SH7750_SCSCR1;
+  volatile uint8_t *ssr1 = (volatile uint8_t *)SH7750_SCSSR1;
+
+  /* Find UART descriptor from vector number */
+  sh4uart *uart = &sh4_uarts[0];
+
+  if (uart->tx_buf != NULL && uart->tx_ptr < uart->tx_buf_len) {
+    while ((SCSSR1 & SH7750_SCSSR1_TDRE) != 0 &&
+            uart->tx_ptr < uart->tx_buf_len) {
+        SCTDR1 = uart->tx_buf[uart->tx_ptr++];
+        *ssr1 &= ~SH7750_SCSSR1_TDRE;
     }
-    else
-    {
-        register int dequeue = uart->tx_buf_len;
-
-        uart->tx_buf = NULL;
-        uart->tx_ptr = uart->tx_buf_len = 0;
-
-        /* Disable interrupts while we do not have any data to transmit */
-        SCSCR1 &= ~SH7750_SCSCR_TIE;
-
-        rtems_termios_dequeue_characters(uart->tty, dequeue);
-    }
+  } else {
+    register int dequeue = uart->tx_buf_len;
+
+    uart->tx_buf = NULL;
+    uart->tx_ptr = uart->tx_buf_len = 0;
+
+    /* Disable interrupts while we do not have any data to transmit */
+    *scr1 &= ~SH7750_SCSCR_TIE;
+
+    rtems_termios_dequeue_characters(uart->tty, dequeue);
+  }
 }
 
@@ -757,34 +721,32 @@
 sh4uart2_interrupt_transmit(rtems_vector_number vec)
 {
-    /* Find UART descriptor from vector number */
-    sh4uart *uart = &sh4_uarts[1];
-
-    if (uart->tx_buf != NULL && uart->tx_ptr < uart->tx_buf_len)
-    {
-            while ((SCSSR2 & SH7750_SCSSR2_TDFE) != 0)
-            {
-                int i;
-                for (i = 0;
-                        i < 16 - TRANSMIT_TRIGGER_VALUE(SCFCR2 &
-                            SH7750_SCFCR2_TTRG);
-                        i++)
-                    SCTDR2 = uart->tx_buf[uart->tx_ptr++];
-                while ((SCSSR1 & SH7750_SCSSR1_TDRE) == 0 ||
-                        (SCSSR1 & SH7750_SCSSR1_TEND) == 0);
-                    SCSSR1 &= ~(SH7750_SCSSR1_TDRE | SH7750_SCSSR2_TEND);
-            }
+  volatile uint8_t *ssr1 = (volatile uint8_t *)SH7750_SCSSR1;
+  volatile uint16_t *scr2 = (volatile uint16_t *)SH7750_SCSCR2;
+
+  /* Find UART descriptor from vector number */
+  sh4uart *uart = &sh4_uarts[1];
+
+  if (uart->tx_buf != NULL && uart->tx_ptr < uart->tx_buf_len) {
+    while ((SCSSR2 & SH7750_SCSSR2_TDFE) != 0) {
+        int i;
+        for (i = 0;
+             i < 16 - TRANSMIT_TRIGGER_VALUE(SCFCR2 & SH7750_SCFCR2_TTRG);
+             i++)
+          SCTDR2 = uart->tx_buf[uart->tx_ptr++];
+        while ((SCSSR1 & SH7750_SCSSR1_TDRE) == 0 ||
+                (SCSSR1 & SH7750_SCSSR1_TEND) == 0);
+        *ssr1 &= ~(SH7750_SCSSR1_TDRE | SH7750_SCSSR2_TEND);
     }
-    else
-    {
-        register int dequeue = uart->tx_buf_len;
-
-        uart->tx_buf = NULL;
-        uart->tx_ptr = uart->tx_buf_len = 0;
-
-        /* Disable interrupts while we do not have any data to transmit */
-        SCSCR2 &= ~SH7750_SCSCR_TIE;
-
-        rtems_termios_dequeue_characters(uart->tty, dequeue);
-    }
+  } else {
+    register int dequeue = uart->tx_buf_len;
+
+    uart->tx_buf = NULL;
+    uart->tx_ptr = uart->tx_buf_len = 0;
+
+    /* Disable interrupts while we do not have any data to transmit */
+    *scr2 &= ~SH7750_SCSCR_TIE;
+
+    rtems_termios_dequeue_characters(uart->tty, dequeue);
+  }
 }
 
@@ -803,24 +765,24 @@
 sh4uart_interrupt_write(sh4uart *uart, const char *buf, int len)
 {
-    int level;
-
-    while ((SCSSR1 & SH7750_SCSSR1_TEND) == 0);
-
-    rtems_interrupt_disable(level);
-
-    uart->tx_buf = buf;
-    uart->tx_buf_len = len;
-    uart->tx_ptr = 0;
-
-    if (uart->chn == SH4_SCI)
-    {
-        SCSCR1 |= SH7750_SCSCR_TIE;
-    }
-    else
-        SCSCR2 |= SH7750_SCSCR_TIE;
-
-    rtems_interrupt_enable(level);
-
-    return RTEMS_SUCCESSFUL;
+  volatile uint8_t  *scr1 = (volatile uint8_t *)SH7750_SCSCR1;
+  volatile uint16_t *scr2 = (volatile uint16_t *)SH7750_SCSCR2;
+  int level;
+
+  while ((SCSSR1 & SH7750_SCSSR1_TEND) == 0);
+
+  rtems_interrupt_disable(level);
+
+  uart->tx_buf = buf;
+  uart->tx_buf_len = len;
+  uart->tx_ptr = 0;
+
+  if (uart->chn == SH4_SCI)
+    *scr1 |= SH7750_SCSCR_TIE;
+  else
+    *scr2 |= SH7750_SCSCR_TIE;
+
+  rtems_interrupt_enable(level);
+
+  return RTEMS_SUCCESSFUL;
 }
 
@@ -837,6 +799,13 @@
 sh4uart_stop_remote_tx(sh4uart *uart)
 {
-    SCSCR(uart->chn) &= ~(SH7750_SCSCR_RIE | SH7750_SCSCR_RE);
-    return RTEMS_SUCCESSFUL;
+  if ( uart->chn == 1 ) {
+    volatile uint8_t *scr = (volatile uint8_t *)SH7750_SCSCR1;
+    *scr &= ~(SH7750_SCSCR_RIE | SH7750_SCSCR_RE);
+  } else {
+    volatile uint16_t *scr = (volatile uint16_t *)SH7750_SCSCR2;
+    *scr &= ~(SH7750_SCSCR_RIE | SH7750_SCSCR_RE);
+  }
+
+  return RTEMS_SUCCESSFUL;
 }
 
@@ -853,6 +822,13 @@
 sh4uart_start_remote_tx(sh4uart *uart)
 {
-    SCSCR(uart->chn) |= SH7750_SCSCR_RIE | SH7750_SCSCR_RE;
-    return RTEMS_SUCCESSFUL;
+  if ( uart->chn == 1 ) {
+    volatile uint8_t *scr = (volatile uint8_t *)SH7750_SCSCR1;
+    *scr |= SH7750_SCSCR_RIE | SH7750_SCSCR_RE;
+  } else {
+    volatile uint16_t *scr = (volatile uint16_t *)SH7750_SCSCR2;
+    *scr |= SH7750_SCSCR_RIE | SH7750_SCSCR_RE;
+  }
+
+  return RTEMS_SUCCESSFUL;
 }
 
@@ -932,13 +908,12 @@
 ipl_console_poll_write(int minor, const char *buf, int len)
 {
-    int c;
-    while (len > 0)
-    {
-        c = (len < 64 ? len : 64);
-        ipl_serial_output(buf, c);
-        len -= c;
-        buf += c;
-    }
-    return 0;
+  int c;
+  while (len > 0) {
+    c = (len < 64 ? len : 64);
+    ipl_serial_output(buf, c);
+    len -= c;
+    buf += c;
+  }
+  return 0;
 }
 #endif
