Changeset cd3d747 in rtems


Ignore:
Timestamp:
Mar 27, 2017, 6:01:38 AM (3 years ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
master
Children:
0027682
Parents:
82c0836
git-author:
Sebastian Huber <sebastian.huber@…> (03/27/17 06:01:38)
git-committer:
Sebastian Huber <sebastian.huber@…> (03/28/17 08:32:37)
Message:

arm: Optimize context switch

Set CPU_ENABLE_ROBUST_THREAD_DISPATCH to TRUE. In this case the
interrupts are always enabled during a context switch even after
interrupt processing (see #2751). Remove the CPSR from the context
control since it contains only volatile bits.

Close #2954.

Files:
4 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/arm/tms570/startup/bspstart.c

    r82c0836 rcd3d747  
    3535  void *need_remap_ptr;
    3636  unsigned int need_remap_int;
    37 
    38   #if BYTE_ORDER == BIG_ENDIAN
    39     /*
    40      * If CPU is big endian (TMS570 family variant)
    41      * set the CPU mode to supervisor and big endian.
    42      * Do not set mode if CPU is little endian
    43      * (RM48 family variant) for which default mode 0x13
    44      * defined in cpukit/score/cpu/arm/cpu.c
    45      * is right.
    46      */
    47     arm_cpu_mode = 0x213;
    48   #endif
    4937
    5038  tms570_initialize_and_clear();
  • cpukit/score/cpu/arm/cpu.c

    r82c0836 rcd3d747  
    1616 *  Copyright (c) 2007 Ray xu <rayx.cn@gmail.com>
    1717 *
    18  *  Copyright (c) 2009, 2016 embedded brains GmbH
     18 *  Copyright (c) 2009, 2017 embedded brains GmbH
    1919 *
    2020 *  The license and distribution terms for this file may be
     
    2727#endif
    2828
    29 #include <rtems/system.h>
    30 #include <rtems.h>
    31 #include <rtems/bspIo.h>
    32 #include <rtems/score/isr.h>
    33 #include <rtems/score/wkspace.h>
     29#include <rtems/score/assert.h>
     30#include <rtems/score/cpu.h>
    3431#include <rtems/score/thread.h>
    3532#include <rtems/score/tls.h>
    36 #include <rtems/score/cpu.h>
    3733
    3834#ifdef ARM_MULTILIB_VFP
     
    9086#ifdef ARM_MULTILIB_ARCH_V4
    9187
    92 /*
    93  * This variable can be used to change the running mode of the execution
    94  * contexts.
    95  */
    96 uint32_t arm_cpu_mode = 0x13;
    97 
    9888void _CPU_Context_Initialize(
    9989  Context_Control *the_context,
     
    10696)
    10797{
     98  (void) new_level;
     99
    108100  the_context->register_sp = (uint32_t) stack_area_begin + stack_area_size;
    109101  the_context->register_lr = (uint32_t) entry_point;
    110   the_context->register_cpsr = ( ( new_level != 0 ) ? ARM_PSR_I : 0 )
    111     | arm_cpu_mode;
    112102  the_context->isr_dispatch_disable = 0;
    113103
     
    121111}
    122112
    123 /* Preprocessor magic for stringification of x */
    124 #define _CPU_ISR_LEVEL_DO_STRINGOF( x) #x
    125 #define _CPU_ISR_LEVEL_STRINGOF( x) _CPU_ISR_LEVEL_DO_STRINGOF( x)
    126 
    127113void _CPU_ISR_Set_level( uint32_t level )
    128114{
    129115  uint32_t arm_switch_reg;
    130116
    131   level = ( level != 0 ) ? ARM_PSR_I : 0;
     117  /* Ignore the level parameter and just enable interrupts */
     118  (void) level;
    132119
    133120  __asm__ volatile (
    134121    ARM_SWITCH_TO_ARM
    135122    "mrs %[arm_switch_reg], cpsr\n"
    136     "bic %[arm_switch_reg], #" _CPU_ISR_LEVEL_STRINGOF( ARM_PSR_I ) "\n"
    137     "orr %[arm_switch_reg], %[level]\n"
     123    "bic %[arm_switch_reg], #" RTEMS_XSTRING( ARM_PSR_I ) "\n"
    138124    "msr cpsr, %0\n"
    139125    ARM_SWITCH_BACK
    140126    : [arm_switch_reg] "=&r" (arm_switch_reg)
    141     : [level] "r" (level)
    142127  );
    143128}
     
    151136    ARM_SWITCH_TO_ARM
    152137    "mrs %[level], cpsr\n"
    153     "and %[level], #" _CPU_ISR_LEVEL_STRINGOF( ARM_PSR_I ) "\n"
     138    "and %[level], #" RTEMS_XSTRING( ARM_PSR_I ) "\n"
    154139    ARM_SWITCH_BACK
    155140    : [level] "=&r" (level) ARM_SWITCH_ADDITIONAL_OUTPUT
  • cpukit/score/cpu/arm/cpu_asm.S

    r82c0836 rcd3d747  
    2020 *  Emmanuel Raguet, mailto:raguet@crf.canon.fr
    2121 *
    22  *  Copyright (c) 2013, 2016 embedded brains GmbH
     22 *  Copyright (c) 2013, 2017 embedded brains GmbH
    2323 *
    2424 *  The license and distribution terms for this file may be
     
    5656DEFINE_FUNCTION_ARM(_CPU_Context_switch)
    5757/* Start saving context */
    58         mrs     r2, CPSR
    59         stmia   r0,  {r2, r4, r5, r6, r7, r8, r9, r10, r11, r13, r14}
     58        GET_SELF_CPU_CONTROL    r2
     59        stm     r0, {r4, r5, r6, r7, r8, r9, r10, r11, r13, r14}
    6060
    61         GET_SELF_CPU_CONTROL    r2
     61#ifdef ARM_MULTILIB_HAS_THREAD_ID_REGISTER
     62        mrc     p15, 0, r3, c13, c0, 3
     63#endif
     64
    6265        ldr     r4, [r2, #PER_CPU_ISR_DISPATCH_DISABLE]
    6366
    6467#ifdef ARM_MULTILIB_VFP
    65         add     r3, r0, #ARM_CONTEXT_CONTROL_D8_OFFSET
    66         vstm    r3, {d8-d15}
     68        add     r5, r0, #ARM_CONTEXT_CONTROL_D8_OFFSET
     69        vstm    r5, {d8-d15}
    6770#endif
    6871
    6972#ifdef ARM_MULTILIB_HAS_THREAD_ID_REGISTER
    70         mrc     p15, 0, r3, c13, c0, 3
    7173        str     r3, [r0, #ARM_CONTEXT_CONTROL_THREAD_ID_OFFSET]
    7274#endif
     
    107109#endif
    108110
     111#ifdef ARM_MULTILIB_HAS_THREAD_ID_REGISTER
     112        ldr     r3, [r1, #ARM_CONTEXT_CONTROL_THREAD_ID_OFFSET]
     113#endif
     114
    109115        ldr     r4, [r1, #ARM_CONTEXT_CONTROL_ISR_DISPATCH_DISABLE]
    110116
    111 #ifdef ARM_MULTILIB_HAS_THREAD_ID_REGISTER
    112         ldr     r3, [r1, #ARM_CONTEXT_CONTROL_THREAD_ID_OFFSET]
    113         mcr     p15, 0, r3, c13, c0, 3
     117#ifdef ARM_MULTILIB_VFP
     118        add     r5, r1, #ARM_CONTEXT_CONTROL_D8_OFFSET
     119        vldm    r5, {d8-d15}
    114120#endif
    115121
    116 #ifdef ARM_MULTILIB_VFP
    117         add     r3, r1, #ARM_CONTEXT_CONTROL_D8_OFFSET
    118         vldm    r3, {d8-d15}
     122#ifdef ARM_MULTILIB_HAS_THREAD_ID_REGISTER
     123        mcr     p15, 0, r3, c13, c0, 3
    119124#endif
    120125
    121126        str     r4, [r2, #PER_CPU_ISR_DISPATCH_DISABLE]
    122127
    123         ldmia   r1,  {r2, r4, r5, r6, r7, r8, r9, r10, r11, r13, r14}
    124         msr     CPSR_fsxc, r2
    125 #ifdef __thumb__
     128        /* In ARMv5T and above the load of PC is an interworking branch */
     129#if __ARM_ARCH >= 5
     130        ldm     r1, {r4, r5, r6, r7, r8, r9, r10, r11, r13, pc}
     131#else
     132        ldm     r1, {r4, r5, r6, r7, r8, r9, r10, r11, r13, r14}
    126133        bx      lr
    127         nop
    128 #else
    129         mov     pc, lr
    130134#endif
     135
    131136/*
    132137 *  void _CPU_Context_restore( new_context )
  • cpukit/score/cpu/arm/rtems/score/cpu.h

    r82c0836 rcd3d747  
    99 *  processor.
    1010 *
    11  *  Copyright (c) 2009, 2016 embedded brains GmbH
     11 *  Copyright (c) 2009, 2017 embedded brains GmbH
    1212 *
    1313 *  Copyright (c) 2007 Ray Xu <Rayx.cn@gmail.com>
     
    121121#define CPU_USE_DEFERRED_FP_SWITCH FALSE
    122122
    123 #if defined(ARM_MULTILIB_ARCH_V7M)
    124   #define CPU_ENABLE_ROBUST_THREAD_DISPATCH TRUE
    125 #else
    126   #define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE
    127 #endif
     123#define CPU_ENABLE_ROBUST_THREAD_DISPATCH TRUE
    128124
    129125#if defined(ARM_MULTILIB_HAS_WFI)
     
    143139#define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES )
    144140
    145 /*
    146  * The interrupt mask disables only normal interrupts (IRQ).
    147  *
    148  * In order to support fast interrupts (FIQ) such that they can do something
    149  * useful, we have to disable the operating system support for FIQs.  Having
    150  * operating system support for them would require that FIQs are disabled
    151  * during critical sections of the operating system and application.  At this
    152  * level IRQs and FIQs would be equal.  It is true that FIQs could interrupt
    153  * the non critical sections of IRQs, so here they would have a small
    154  * advantage.  Without operating system support, the FIQs can execute at any
    155  * time (of course not during the service of another FIQ). If someone needs
    156  * operating system support for a FIQ, she can trigger a software interrupt and
    157  * service the request in a two-step process.
    158  */
    159141#define CPU_MODES_INTERRUPT_MASK 0x1
    160142
     
    207189
    208190#ifdef ARM_MULTILIB_ARCH_V4
     191  #define ARM_CONTEXT_CONTROL_ISR_DISPATCH_DISABLE 40
     192#endif
     193
     194#ifdef RTEMS_SMP
    209195  #if defined(ARM_MULTILIB_VFP)
    210     #define ARM_CONTEXT_CONTROL_ISR_DISPATCH_DISABLE 112
     196    #define ARM_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 112
    211197  #elif defined(ARM_MULTILIB_HAS_THREAD_ID_REGISTER)
    212     #define ARM_CONTEXT_CONTROL_ISR_DISPATCH_DISABLE 48
     198    #define ARM_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 48
    213199  #else
    214     #define ARM_CONTEXT_CONTROL_ISR_DISPATCH_DISABLE 44
    215   #endif
    216 #endif
    217 
    218 #ifdef RTEMS_SMP
    219   #ifdef ARM_MULTILIB_VFP
    220     #define ARM_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 116
    221   #else
    222     #define ARM_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 52
     200    #define ARM_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 44
    223201  #endif
    224202#endif
     
    245223typedef struct {
    246224#if defined(ARM_MULTILIB_ARCH_V4)
    247   uint32_t register_cpsr;
    248225  uint32_t register_r4;
    249226  uint32_t register_r5;
     
    256233  uint32_t register_sp;
    257234  uint32_t register_lr;
     235  uint32_t isr_dispatch_disable;
    258236#elif defined(ARM_MULTILIB_ARCH_V6M) || defined(ARM_MULTILIB_ARCH_V7M)
    259237  uint32_t register_r4;
     
    284262  uint64_t register_d15;
    285263#endif
    286 #ifdef ARM_MULTILIB_ARCH_V4
    287   uint32_t isr_dispatch_disable;
    288 #endif
    289264#ifdef RTEMS_SMP
    290265  volatile bool is_executing;
     
    296271} Context_Control_fp;
    297272
    298 extern uint32_t arm_cpu_mode;
    299 
    300273static inline void _ARM_Data_memory_barrier( void )
    301274{
     
    332305  uint32_t arm_switch_reg;
    333306
     307  /*
     308   * Disable only normal interrupts (IRQ).
     309   *
     310   * In order to support fast interrupts (FIQ) such that they can do something
     311   * useful, we have to disable the operating system support for FIQs.  Having
     312   * operating system support for them would require that FIQs are disabled
     313   * during critical sections of the operating system and application.  At this
     314   * level IRQs and FIQs would be equal.  It is true that FIQs could interrupt
     315   * the non critical sections of IRQs, so here they would have a small
     316   * advantage.  Without operating system support, the FIQs can execute at any
     317   * time (of course not during the service of another FIQ). If someone needs
     318   * operating system support for a FIQ, she can trigger a software interrupt and
     319   * service the request in a two-step process.
     320   */
    334321  __asm__ volatile (
    335322    ARM_SWITCH_TO_ARM
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