Changeset cc4c524b in rtems


Ignore:
Timestamp:
Aug 19, 2008, 8:02:37 PM (11 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.9, master
Children:
0e4e56b
Parents:
14afc13
Message:

2008-08-19 Joel Sherrill <joel.sherrill@…>

  • libchip/display/disp_hcms29xx.c: Initialize softc_ptr to NULL.
  • libchip/network/dec21140.c, libchip/network/if_dc.c: Use uint32_t.
Location:
c/src
Files:
4 edited

Legend:

Unmodified
Added
Removed
  • c/src/ChangeLog

    r14afc13 rcc4c524b  
     12008-08-19      Joel Sherrill <joel.sherrill@OARcorp.com>
     2
     3        * libchip/display/disp_hcms29xx.c: Initialize softc_ptr to NULL.
     4        * libchip/network/dec21140.c, libchip/network/if_dc.c: Use uint32_t.
     5
    162008-08-19      Joel Sherrill <joel.sherrill@OARcorp.com>
    27
  • c/src/libchip/display/disp_hcms29xx.c

    r14afc13 rcc4c524b  
    750750  rtems_status_code rc = RTEMS_SUCCESSFUL;
    751751  static char *devname = {"/dev/disp"};
    752   disp_hcms29xx_drv_t *softc_ptr;
     752  disp_hcms29xx_drv_t *softc_ptr = NULL;
    753753  /*
    754754   * FIXME: get softc_ptr
     
    835835\*=========================================================================*/
    836836{
    837   disp_hcms29xx_drv_t *softc_ptr;
     837  disp_hcms29xx_drv_t *softc_ptr = NULL;
    838838  /*
    839839   * FIXME: get softc_ptr
     
    869869  rtems_libio_rw_args_t *args = arg;
    870870  uint32_t cnt;
    871   disp_hcms29xx_drv_t *softc_ptr;
     871  disp_hcms29xx_drv_t *softc_ptr = NULL;
    872872  /*
    873873   * FIXME: get softc_ptr
  • c/src/libchip/network/dec21140.c

    r14afc13 rcc4c524b  
    9696
    9797/* note: the 21143 isn't really a DEC, it's an Intel chip */
    98 #define PCI_INVALID_VENDORDEVICEID      0xffffffff
     98#define PCI_INVALID_VENDORDEVICEID      0xffffffff
    9999#define PCI_VENDOR_ID_DEC               0x1011
    100100#define PCI_DEVICE_ID_DEC_21140         0x0009
     
    107107
    108108/* command and status registers, 32-bit access, only if IO-ACCESS */
    109 #define ioCSR0  0x00    /* bus mode register */
    110 #define ioCSR1  0x08    /* transmit poll demand */
    111 #define ioCSR2  0x10    /* receive poll demand */
    112 #define ioCSR3  0x18    /* receive list base address */
    113 #define ioCSR4  0x20    /* transmit list base address */
    114 #define ioCSR5  0x28    /* status register */
    115 #define ioCSR6  0x30    /* operation mode register */
    116 #define ioCSR7  0x38    /* interrupt mask register */
    117 #define ioCSR8  0x40    /* missed frame counter */
    118 #define ioCSR9  0x48    /* Ethernet ROM register */
    119 #define ioCSR10 0x50    /* reserved */
    120 #define ioCSR11 0x58    /* full-duplex register */
    121 #define ioCSR12 0x60    /* SIA status register */
     109#define ioCSR0  0x00    /* bus mode register */
     110#define ioCSR1  0x08    /* transmit poll demand */
     111#define ioCSR2  0x10    /* receive poll demand */
     112#define ioCSR3  0x18    /* receive list base address */
     113#define ioCSR4  0x20    /* transmit list base address */
     114#define ioCSR5  0x28    /* status register */
     115#define ioCSR6  0x30    /* operation mode register */
     116#define ioCSR7  0x38    /* interrupt mask register */
     117#define ioCSR8  0x40    /* missed frame counter */
     118#define ioCSR9  0x48    /* Ethernet ROM register */
     119#define ioCSR10 0x50    /* reserved */
     120#define ioCSR11 0x58    /* full-duplex register */
     121#define ioCSR12 0x60    /* SIA status register */
    122122#define ioCSR13 0x68
    123123#define ioCSR14 0x70
    124 #define ioCSR15 0x78    /* SIA general register */
     124#define ioCSR15 0x78    /* SIA general register */
    125125
    126126/* command and status registers, 32-bit access, only if MEMORY-ACCESS */
    127 #define memCSR0  0x00   /* bus mode register */
    128 #define memCSR1  0x02   /* transmit poll demand */
    129 #define memCSR2  0x04   /* receive poll demand */
    130 #define memCSR3  0x06   /* receive list base address */
    131 #define memCSR4  0x08   /* transmit list base address */
    132 #define memCSR5  0x0A   /* status register */
    133 #define memCSR6  0x0C   /* operation mode register */
    134 #define memCSR7  0x0E   /* interrupt mask register */
    135 #define memCSR8  0x10   /* missed frame counter */
    136 #define memCSR9  0x12   /* Ethernet ROM register */
    137 #define memCSR10 0x14   /* reserved */
    138 #define memCSR11 0x16   /* full-duplex register */
    139 #define memCSR12 0x18   /* SIA status register */
     127#define memCSR0  0x00    /* bus mode register */
     128#define memCSR1  0x02    /* transmit poll demand */
     129#define memCSR2  0x04    /* receive poll demand */
     130#define memCSR3  0x06    /* receive list base address */
     131#define memCSR4  0x08    /* transmit list base address */
     132#define memCSR5  0x0A    /* status register */
     133#define memCSR6  0x0C    /* operation mode register */
     134#define memCSR7  0x0E    /* interrupt mask register */
     135#define memCSR8  0x10    /* missed frame counter */
     136#define memCSR9  0x12    /* Ethernet ROM register */
     137#define memCSR10 0x14    /* reserved */
     138#define memCSR11 0x16    /* full-duplex register */
     139#define memCSR12 0x18    /* SIA status register */
    140140#define memCSR13 0x1A
    141141#define memCSR14 0x1C
    142 #define memCSR15 0x1E   /* SIA general register */
     142#define memCSR15 0x1E    /* SIA general register */
    143143
    144144#define DEC_REGISTER_SIZE    0x100   /* to reserve virtual memory */
     
    188188*/
    189189
    190 #define NRXBUFS 16      /* number of receive buffers */
    191 #define NTXBUFS 16      /* number of transmit buffers */
     190#define NRXBUFS 16    /* number of receive buffers */
     191#define NTXBUFS 16    /* number of transmit buffers */
    192192
    193193/*
    194194 * Number of DEC boards supported by this driver
    195195 */
    196 #define NDECDRIVER      8
     196#define NDECDRIVER    8
    197197
    198198/*
    199199 * Receive buffer size -- Allow for a full ethernet packet including CRC
    200200 */
    201 #define RBUF_SIZE       1536
    202 
    203 #define ET_MINLEN       60      /* minimum message length */
     201#define RBUF_SIZE    1536
     202
     203#define ET_MINLEN       60    /* minimum message length */
    204204
    205205/*
     
    240240struct dec21140_softc {
    241241
    242       struct arpcom             arpcom;
     242      struct arpcom             arpcom;
    243243
    244244      rtems_irq_connect_data    irqInfo;
     
    247247      int                       numRxbuffers, numTxbuffers;
    248248
    249       volatile struct MD        *MDbase;
     249      volatile struct MD        *MDbase;
    250250      volatile struct MD        *nextRxMD;
    251       volatile unsigned char    *bufferBase;
    252       int                       acceptBroadcast;
    253 
    254       volatile struct MD   *TxMD;
    255       volatile struct MD   *SentTxMD;
    256       int         PendingTxCount;
    257       int         TxSuspended;
    258 
    259       unsigned int                      port;
    260       volatile unsigned int             *base;
     251      volatile unsigned char   *bufferBase;
     252      int                       acceptBroadcast;
     253
     254      volatile struct MD       *TxMD;
     255      volatile struct MD       *SentTxMD;
     256      int                       PendingTxCount;
     257      int                       TxSuspended;
     258
     259      unsigned int              port;
     260      volatile uint32_t        *base;
    261261
    262262      /*
    263263       * Statistics
    264264       */
    265       unsigned long     rxInterrupts;
    266       unsigned long     rxNotFirst;
    267       unsigned long     rxNotLast;
    268       unsigned long     rxGiant;
    269       unsigned long     rxNonOctet;
    270       unsigned long     rxRunt;
    271       unsigned long     rxBadCRC;
    272       unsigned long     rxOverrun;
    273       unsigned long     rxCollision;
    274 
    275       unsigned long     txInterrupts;
    276       unsigned long     txDeferred;
    277       unsigned long     txHeartbeat;
    278       unsigned long     txLateCollision;
    279       unsigned long     txRetryLimit;
    280       unsigned long     txUnderrun;
    281       unsigned long     txLostCarrier;
    282       unsigned long     txRawWait;
     265      unsigned long     rxInterrupts;
     266      unsigned long     rxNotFirst;
     267      unsigned long     rxNotLast;
     268      unsigned long     rxGiant;
     269      unsigned long     rxNonOctet;
     270      unsigned long     rxRunt;
     271      unsigned long     rxBadCRC;
     272      unsigned long     rxOverrun;
     273      unsigned long     rxCollision;
     274
     275      unsigned long     txInterrupts;
     276      unsigned long     txDeferred;
     277      unsigned long     txHeartbeat;
     278      unsigned long     txLateCollision;
     279      unsigned long     txRetryLimit;
     280      unsigned long     txUnderrun;
     281      unsigned long     txLostCarrier;
     282      unsigned long     txRawWait;
    283283};
    284284
    285285static struct dec21140_softc dec21140_softc[NDECDRIVER];
    286 static rtems_id rxDaemonTid;
    287 static rtems_id txDaemonTid;
     286static rtems_id rxDaemonTid;
     287static rtems_id txDaemonTid;
    288288
    289289/*
     
    291291 */
    292292/*  EEPROM_Ctrl bits. */
    293 #define EE_SHIFT_CLK            0x02    /* EEPROM shift clock. */
    294 #define EE_CS                   0x01    /* EEPROM chip select. */
    295 #define EE_DATA_WRITE           0x04    /* EEPROM chip data in. */
    296 #define EE_WRITE_0              0x01
    297 #define EE_WRITE_1              0x05
    298 #define EE_DATA_READ            0x08    /* EEPROM chip data out. */
    299 #define EE_ENB                  (0x4800 | EE_CS)
     293#define EE_SHIFT_CLK    0x02    /* EEPROM shift clock. */
     294#define EE_CS           0x01    /* EEPROM chip select. */
     295#define EE_DATA_WRITE   0x04    /* EEPROM chip data in. */
     296#define EE_WRITE_0      0x01
     297#define EE_WRITE_1      0x05
     298#define EE_DATA_READ    0x08    /* EEPROM chip data out. */
     299#define EE_ENB          (0x4800 | EE_CS)
    300300
    301301/* The EEPROM commands include the alway-set leading bit. */
    302 #define EE_WRITE_CMD    (5 << 6)
    303 #define EE_READ_CMD     (6 << 6)
    304 #define EE_ERASE_CMD    (7 << 6)
    305 
    306 static int eeget16(volatile unsigned int *ioaddr, int location)
     302#define EE_WRITE_CMD    (5 << 6)
     303#define EE_READ_CMD     (6 << 6)
     304#define EE_ERASE_CMD    (7 << 6)
     305
     306static int eeget16(volatile uint32_t *ioaddr, int location)
    307307{
    308308   int i;
     
    398398{
    399399   int i,st;
    400    volatile unsigned int  *tbase;
     400   volatile uint32_t      *tbase;
    401401   volatile unsigned char *cp, *setup_frm, *eaddrs;
    402402   volatile unsigned char *buffer;
     
    555555dec21140_rxDaemon (void *arg)
    556556{
    557    volatile unsigned int *tbase;
     557   volatile uint32_t    *tbase;
    558558   volatile struct MD    *rmd;
    559559   struct dec21140_softc *sc;
     
    627627   struct mbuf             *n;
    628628   unsigned int            len;
    629    volatile unsigned int   *tbase;
     629   volatile uint32_t      *tbase;
    630630
    631631   tbase = dp->base;
     
    730730   struct dec21140_softc *sc = arg;
    731731   struct ifnet *ifp = &sc->arpcom.ac_if;
    732    volatile unsigned int *tbase;
     732   volatile uint32_t *tbase;
    733733
    734734   /*
     
    746746   st_le32( (tbase+memCSR5), IT_SETUP);
    747747   st_le32( (tbase+memCSR7), IT_SETUP);
    748    st_le32( (unsigned int*)(tbase+memCSR6), CSR6_INIT | CSR6_TXRX);
     748   st_le32( (tbase+memCSR6), CSR6_INIT | CSR6_TXRX);
    749749
    750750   /*
     
    760760dec21140_stop (struct dec21140_softc *sc)
    761761{
    762   volatile unsigned int *tbase;
     762  volatile uint32_t *tbase;
    763763  struct ifnet *ifp = &sc->arpcom.ac_if;
    764764
     
    781781dec21140_stats (struct dec21140_softc *sc)
    782782{
    783         printf ("      Rx Interrupts:%-8lu", sc->rxInterrupts);
    784         printf ("       Not First:%-8lu", sc->rxNotFirst);
    785         printf ("        Not Last:%-8lu\n", sc->rxNotLast);
    786         printf ("              Giant:%-8lu", sc->rxGiant);
    787         printf ("            Runt:%-8lu", sc->rxRunt);
    788         printf ("       Non-octet:%-8lu\n", sc->rxNonOctet);
    789         printf ("            Bad CRC:%-8lu", sc->rxBadCRC);
    790         printf ("         Overrun:%-8lu", sc->rxOverrun);
    791         printf ("       Collision:%-8lu\n", sc->rxCollision);
    792 
    793         printf ("      Tx Interrupts:%-8lu", sc->txInterrupts);
    794         printf ("        Deferred:%-8lu", sc->txDeferred);
    795         printf (" Missed Hearbeat:%-8lu\n", sc->txHeartbeat);
    796         printf ("         No Carrier:%-8lu", sc->txLostCarrier);
    797         printf ("Retransmit Limit:%-8lu", sc->txRetryLimit);
    798         printf ("  Late Collision:%-8lu\n", sc->txLateCollision);
    799         printf ("           Underrun:%-8lu", sc->txUnderrun);
    800         printf (" Raw output wait:%-8lu\n", sc->txRawWait);
     783  printf ("      Rx Interrupts:%-8lu", sc->rxInterrupts);
     784  printf ("       Not First:%-8lu", sc->rxNotFirst);
     785  printf ("        Not Last:%-8lu\n", sc->rxNotLast);
     786  printf ("              Giant:%-8lu", sc->rxGiant);
     787  printf ("            Runt:%-8lu", sc->rxRunt);
     788  printf ("       Non-octet:%-8lu\n", sc->rxNonOctet);
     789  printf ("            Bad CRC:%-8lu", sc->rxBadCRC);
     790  printf ("         Overrun:%-8lu", sc->rxOverrun);
     791  printf ("       Collision:%-8lu\n", sc->rxCollision);
     792
     793  printf ("      Tx Interrupts:%-8lu", sc->txInterrupts);
     794  printf ("        Deferred:%-8lu", sc->txDeferred);
     795  printf (" Missed Hearbeat:%-8lu\n", sc->txHeartbeat);
     796  printf ("         No Carrier:%-8lu", sc->txLostCarrier);
     797  printf ("Retransmit Limit:%-8lu", sc->txRetryLimit);
     798  printf ("  Late Collision:%-8lu\n", sc->txLateCollision);
     799  printf ("           Underrun:%-8lu", sc->txUnderrun);
     800  printf (" Raw output wait:%-8lu\n", sc->txRawWait);
    801801}
    802802
     
    882882   unsigned char cvalue;
    883883#if defined(__i386__)
    884    uint32_t     value;
    885    uint8_t      interrupt;
     884   uint32_t     value;
     885   uint8_t      interrupt;
    886886#endif
    887887   int          pbus, pdev, pfun;
    888888#if defined(__PPC__)
    889    int          tmp;
    890    uint32_t     lvalue;
     889   int          tmp;
     890   uint32_t     lvalue;
    891891#endif
    892892
     
    975975                            PTE_CACHE_DISABLE | PTE_WRITABLE);
    976976   else
    977       sc->base = (unsigned int *)(value & ~MEM_MASK);
     977      sc->base = (uint32_t *)(value & ~MEM_MASK);
    978978
    979979   pci_read_config_byte(pbus, pdev, pfun, 60, &interrupt);
  • c/src/libchip/network/if_dc.c

    r14afc13 rcc4c524b  
    16051605{
    16061606        struct dc_type          *t;
    1607         unsigned int            rev;
     1607        uint32_t                rev;
    16081608        int                     rc;
    16091609
     
    19091909        int                     unitNumber;
    19101910       
    1911         unsigned int            command;
     1911        uint32_t                command;
    19121912        struct dc_softc         *sc;
    19131913        struct ifnet            *ifp;
    19141914        struct dc_type          *t;
    1915         unsigned int            revision;
     1915        uint32_t                revision;
    19161916        int                     error = 0, mac_offset;
    1917         unsigned int            value;
     1917        uint32_t                value;
    19181918       
    19191919        /*
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