Changeset cc40f0b in rtems


Ignore:
Timestamp:
Oct 10, 2017, 3:22:40 PM (22 months ago)
Author:
Javier Jalle <javier.jalle@…>
Branches:
master
Children:
56cf340
Parents:
59af2cc
git-author:
Javier Jalle <javier.jalle@…> (10/10/17 15:22:40)
git-committer:
Daniel Hellstrom <daniel@…> (11/14/17 09:27:20)
Message:

leon, grspw_router: Move register bit defs to header

Location:
c/src/lib/libbsp/sparc/shared
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/sparc/shared/include/grspw_router.h

    r59af2cc rcc40f0b  
    142142                struct router_routing_table *cfg);
    143143
     144/*
     145 * ROUTER PCTRL register fields
     146 */
     147#define PCTRL_RD (0xff << PCTRL_RD_BIT)
     148#define PCTRL_ST (0x1 << PCTRL_ST_BIT)
     149#define PCTRL_SR (0x1 << PCTRL_SR_BIT)
     150#define PCTRL_AD (0x1 << PCTRL_AD_BIT)
     151#define PCTRL_LR (0x1 << PCTRL_LR_BIT)
     152#define PCTRL_PL (0x1 << PCTRL_PL_BIT)
     153#define PCTRL_TS (0x1 << PCTRL_TS_BIT)
     154#define PCTRL_IC (0x1 << PCTRL_IC_BIT)
     155#define PCTRL_ET (0x1 << PCTRL_ET_BIT)
     156#define PCTRL_NP (0x1 << PCTRL_NP_BIT)
     157#define PCTRL_PS (0x1 << PCTRL_PS_BIT)
     158#define PCTRL_BE (0x1 << PCTRL_BE_BIT)
     159#define PCTRL_DI (0x1 << PCTRL_DI_BIT)
     160#define PCTRL_TR (0x1 << PCTRL_TR_BIT)
     161#define PCTRL_PR (0x1 << PCTRL_PR_BIT)
     162#define PCTRL_TF (0x1 << PCTRL_TF_BIT)
     163#define PCTRL_RS (0x1 << PCTRL_RS_BIT)
     164#define PCTRL_TE (0x1 << PCTRL_TE_BIT)
     165#define PCTRL_CE (0x1 << PCTRL_CE_BIT)
     166#define PCTRL_AS (0x1 << PCTRL_AS_BIT)
     167#define PCTRL_LS (0x1 << PCTRL_LS_BIT)
     168#define PCTRL_LD (0x1 << PCTRL_LD_BIT)
     169
     170#define PCTRL_RD_BIT 24
     171#define PCTRL_ST_BIT 21
     172#define PCTRL_SR_BIT 20
     173#define PCTRL_AD_BIT 19
     174#define PCTRL_LR_BIT 18
     175#define PCTRL_PL_BIT 17
     176#define PCTRL_TS_BIT 16
     177#define PCTRL_IC_BIT 15
     178#define PCTRL_ET_BIT 14
     179#define PCTRL_NP_BIT 13
     180#define PCTRL_PS_BIT 12
     181#define PCTRL_BE_BIT 11
     182#define PCTRL_DI_BIT 10
     183#define PCTRL_TR_BIT 9
     184#define PCTRL_PR_BIT 8
     185#define PCTRL_TF_BIT 7
     186#define PCTRL_RS_BIT 6
     187#define PCTRL_TE_BIT 5
     188#define PCTRL_CE_BIT 3
     189#define PCTRL_AS_BIT 2
     190#define PCTRL_LS_BIT 1
     191#define PCTRL_LD_BIT 0
     192
     193/*
     194 * ROUTER PCTRL2 register fields
     195 */
     196#define PCTRL2_SM (0xff << PCTRL2_SM_BIT)
     197#define PCTRL2_SV (0xff << PCTRL2_SV_BIT)
     198#define PCTRL2_OR (0x1 << PCTRL2_OR_BIT)
     199#define PCTRL2_UR (0x1 << PCTRL2_UR_BIT)
     200#define PCTRL2_AT (0x1 << PCTRL2_AT_BIT)
     201#define PCTRL2_AR (0x1 << PCTRL2_AR_BIT)
     202#define PCTRL2_IT (0x1 << PCTRL2_IT_BIT)
     203#define PCTRL2_IR (0x1 << PCTRL2_IR_BIT)
     204#define PCTRL2_SD (0x1f << PCTRL2_SD_BIT)
     205#define PCTRL2_SC (0x1f << PCTRL2_SC_BIT)
     206
     207#define PCTRL2_SM_BIT 24
     208#define PCTRL2_SV_BIT 16
     209#define PCTRL2_OR_BIT 15
     210#define PCTRL2_UR_BIT 14
     211#define PCTRL2_AT_BIT 12
     212#define PCTRL2_AR_BIT 11
     213#define PCTRL2_IT_BIT 10
     214#define PCTRL2_IR_BIT 9
     215#define PCTRL2_SD_BIT 1
     216#define PCTRL2_SC_BIT 0
     217
    144218/* Router Set/Get Port configuration */
    145219extern int router_port_ioc(void *d, int port, struct router_port *cfg);
     
    162236extern int router_port_maxplen_set(void *d, int port, uint32_t length);
    163237
     238/*
     239 * ROUTER PSTSCFG register fields
     240 */
     241#define PSTSCFG_EO (0x1 << PSTSCFG_EO_BIT)
     242#define PSTSCFG_EE (0x1 << PSTSCFG_EE_BIT)
     243#define PSTSCFG_PL (0x1 << PSTSCFG_PL_BIT)
     244#define PSTSCFG_TT (0x1 << PSTSCFG_TT_BIT)
     245#define PSTSCFG_PT (0x1 << PSTSCFG_PT_BIT)
     246#define PSTSCFG_HC (0x1 << PSTSCFG_HC_BIT)
     247#define PSTSCFG_PI (0x1 << PSTSCFG_PI_BIT)
     248#define PSTSCFG_CE (0x1 << PSTSCFG_CE_BIT)
     249#define PSTSCFG_EC (0xf << PSTSCFG_EC_BIT)
     250#define PSTSCFG_TS (0x1 << PSTSCFG_TS_BIT)
     251#define PSTSCFG_ME (0x1 << PSTSCFG_ME_BIT)
     252#define PSTSCFG_IP (0x1f << PSTSCFG_IP_BIT)
     253#define PSTSCFG_CP (0x1 << PSTSCFG_CP_BIT)
     254#define PSTSCFG_PC (0xf << PSTSCFG_PC_BIT)
     255#define PSTSCFG_WCLEAR (PSTSCFG_EO | PSTSCFG_EE | PSTSCFG_PL | \
     256                                                PSTSCFG_TT | PSTSCFG_PT | PSTSCFG_HC | \
     257                                                PSTSCFG_PI | PSTSCFG_CE | PSTSCFG_TS | \
     258                                                PSTSCFG_ME | PSTSCFG_CP)
     259#define PSTSCFG_WCLEAR2 (PSTSCFG_CE | PSTSCFG_CP)
     260
     261#define PSTSCFG_EO_BIT 31
     262#define PSTSCFG_EE_BIT 30
     263#define PSTSCFG_PL_BIT 29
     264#define PSTSCFG_TT_BIT 28
     265#define PSTSCFG_PT_BIT 27
     266#define PSTSCFG_HC_BIT 26
     267#define PSTSCFG_PI_BIT 25
     268#define PSTSCFG_CE_BIT 24
     269#define PSTSCFG_EC_BIT 20
     270#define PSTSCFG_TS_BIT 18
     271#define PSTSCFG_ME_BIT 17
     272#define PSTSCFG_IP_BIT 7
     273#define PSTSCFG_CP_BIT 4
     274#define PSTSCFG_PC_BIT 0
     275
     276/*
     277 * ROUTER PSTS register fields
     278 */
     279#define PSTS_PT (0x3 << PSTS_PT_BIT)
     280#define PSTS_PL (0x1 << PSTS_PL_BIT)
     281#define PSTS_TT (0x1 << PSTS_TT_BIT)
     282#define PSTS_RS (0x1 << PSTS_RS_BIT)
     283#define PSTS_SR (0x1 << PSTS_SR_BIT)
     284#define PSTS_LR (0x1 << PSTS_LR_BIT)
     285#define PSTS_SP (0x1 << PSTS_SP_BIT)
     286#define PSTS_AC (0x1 << PSTS_AC_BIT)
     287#define PSTS_TS (0x1 << PSTS_TS_BIT)
     288#define PSTS_ME (0x1 << PSTS_ME_BIT)
     289#define PSTS_TF (0x1 << PSTS_TF_BIT)
     290#define PSTS_RE (0x1 << PSTS_RE_BIT)
     291#define PSTS_LS (0x7 << PSTS_LS_BIT)
     292#define PSTS_IP (0x1f << PSTS_IP_BIT)
     293#define PSTS_PR (0x1 << PSTS_PR_BIT)
     294#define PSTS_PB (0x1 << PSTS_PB_BIT)
     295#define PSTS_IA (0x1 << PSTS_IA_BIT)
     296#define PSTS_CE (0x1 << PSTS_CE_BIT)
     297#define PSTS_ER (0x1 << PSTS_ER_BIT)
     298#define PSTS_DE (0x1 << PSTS_DE_BIT)
     299#define PSTS_PE (0x1 << PSTS_PE_BIT)
     300#define PSTS_WCLEAR (PSTS_PL | PSTS_TT | PSTS_RS | PSTS_SR | \
     301                                         PSTS_TS | PSTS_ME | PSTS_IA | PSTS_CE | \
     302                                         PSTS_ER | PSTS_DE | PSTS_PE)
     303
     304#define PSTS_PT_BIT 30
     305#define PSTS_PL_BIT 29
     306#define PSTS_TT_BIT 28
     307#define PSTS_RS_BIT 27
     308#define PSTS_SR_BIT 26
     309#define PSTS_LR_BIT 22
     310#define PSTS_SP_BIT 21
     311#define PSTS_AC_BIT 20
     312#define PSTS_TS_BIT 18
     313#define PSTS_ME_BIT 17
     314#define PSTS_TF_BIT 16
     315#define PSTS_RE_BIT 15
     316#define PSTS_LS_BIT 12
     317#define PSTS_IP_BIT 7
     318#define PSTS_PR_BIT 6
     319#define PSTS_PB_BIT 5
     320#define PSTS_IA_BIT 4
     321#define PSTS_CE_BIT 3
     322#define PSTS_ER_BIT 2
     323#define PSTS_DE_BIT 1
     324#define PSTS_PE_BIT 0
     325
    164326/* Check Port Status register and clear errors if there are */
    165327extern int router_port_status(void *d, int port, uint32_t *sts);
  • c/src/lib/libbsp/sparc/shared/spw/grspw_router.c

    r59af2cc rcc40f0b  
    105105/*
    106106 * ROUTER PCTRL register fields
    107  */
    108 #define PCTRL_RD (0xff << PCTRL_RD_BIT)
    109 #define PCTRL_ST (0x1 << PCTRL_ST_BIT)
    110 #define PCTRL_SR (0x1 << PCTRL_SR_BIT)
    111 #define PCTRL_AD (0x1 << PCTRL_AD_BIT)
    112 #define PCTRL_LR (0x1 << PCTRL_LR_BIT)
    113 #define PCTRL_PL (0x1 << PCTRL_PL_BIT)
    114 #define PCTRL_TS (0x1 << PCTRL_TS_BIT)
    115 #define PCTRL_IC (0x1 << PCTRL_IC_BIT)
    116 #define PCTRL_ET (0x1 << PCTRL_ET_BIT)
    117 #define PCTRL_NP (0x1 << PCTRL_NP_BIT)
    118 #define PCTRL_PS (0x1 << PCTRL_PS_BIT)
    119 #define PCTRL_BE (0x1 << PCTRL_BE_BIT)
    120 #define PCTRL_DI (0x1 << PCTRL_DI_BIT)
    121 #define PCTRL_TR (0x1 << PCTRL_TR_BIT)
    122 #define PCTRL_PR (0x1 << PCTRL_PR_BIT)
    123 #define PCTRL_TF (0x1 << PCTRL_TF_BIT)
    124 #define PCTRL_RS (0x1 << PCTRL_RS_BIT)
    125 #define PCTRL_TE (0x1 << PCTRL_TE_BIT)
    126 #define PCTRL_CE (0x1 << PCTRL_CE_BIT)
    127 #define PCTRL_AS (0x1 << PCTRL_AS_BIT)
    128 #define PCTRL_LS (0x1 << PCTRL_LS_BIT)
    129 #define PCTRL_LD (0x1 << PCTRL_LD_BIT)
    130 
    131 #define PCTRL_RD_BIT 24
    132 #define PCTRL_ST_BIT 21
    133 #define PCTRL_SR_BIT 20
    134 #define PCTRL_AD_BIT 19
    135 #define PCTRL_LR_BIT 18
    136 #define PCTRL_PL_BIT 17
    137 #define PCTRL_TS_BIT 16
    138 #define PCTRL_IC_BIT 15
    139 #define PCTRL_ET_BIT 14
    140 #define PCTRL_NP_BIT 13
    141 #define PCTRL_PS_BIT 12
    142 #define PCTRL_BE_BIT 11
    143 #define PCTRL_DI_BIT 10
    144 #define PCTRL_TR_BIT 9
    145 #define PCTRL_PR_BIT 8
    146 #define PCTRL_TF_BIT 7
    147 #define PCTRL_RS_BIT 6
    148 #define PCTRL_TE_BIT 5
    149 #define PCTRL_CE_BIT 3
    150 #define PCTRL_AS_BIT 2
    151 #define PCTRL_LS_BIT 1
    152 #define PCTRL_LD_BIT 0
     107 * DEFINED IN HEADER
     108 */
    153109
    154110/*
    155111 * ROUTER PSTSCFG register fields
    156  */
    157 #define PSTSCFG_EO (0x1 << PSTSCFG_EO_BIT)
    158 #define PSTSCFG_EE (0x1 << PSTSCFG_EE_BIT)
    159 #define PSTSCFG_PL (0x1 << PSTSCFG_PL_BIT)
    160 #define PSTSCFG_TT (0x1 << PSTSCFG_TT_BIT)
    161 #define PSTSCFG_PT (0x1 << PSTSCFG_PT_BIT)
    162 #define PSTSCFG_HC (0x1 << PSTSCFG_HC_BIT)
    163 #define PSTSCFG_PI (0x1 << PSTSCFG_PI_BIT)
    164 #define PSTSCFG_CE (0x1 << PSTSCFG_CE_BIT)
    165 #define PSTSCFG_EC (0xf << PSTSCFG_EC_BIT)
    166 #define PSTSCFG_TS (0x1 << PSTSCFG_TS_BIT)
    167 #define PSTSCFG_ME (0x1 << PSTSCFG_ME_BIT)
    168 #define PSTSCFG_IP (0x1f << PSTSCFG_IP_BIT)
    169 #define PSTSCFG_CP (0x1 << PSTSCFG_CP_BIT)
    170 #define PSTSCFG_PC (0xf << PSTSCFG_PC_BIT)
    171 #define PSTSCFG_WCLEAR (PSTSCFG_EO | PSTSCFG_EE | PSTSCFG_PL | \
    172                                                 PSTSCFG_TT | PSTSCFG_PT | PSTSCFG_HC | \
    173                                                 PSTSCFG_PI | PSTSCFG_CE | PSTSCFG_TS | \
    174                                                 PSTSCFG_ME | PSTSCFG_CP)
    175 
    176 #define PSTSCFG_EO_BIT 31
    177 #define PSTSCFG_EE_BIT 30
    178 #define PSTSCFG_PL_BIT 29
    179 #define PSTSCFG_TT_BIT 28
    180 #define PSTSCFG_PT_BIT 27
    181 #define PSTSCFG_HC_BIT 26
    182 #define PSTSCFG_PI_BIT 25
    183 #define PSTSCFG_CE_BIT 24
    184 #define PSTSCFG_EC_BIT 20
    185 #define PSTSCFG_TS_BIT 18
    186 #define PSTSCFG_ME_BIT 17
    187 #define PSTSCFG_IP_BIT 7
    188 #define PSTSCFG_CP_BIT 4
    189 #define PSTSCFG_PC_BIT 0
     112 * DEFINED IN HEADER
     113 */
    190114
    191115/*
    192116 * ROUTER PSTS register fields
    193  */
    194 #define PSTS_PT (0x3 << PSTS_PT_BIT)
    195 #define PSTS_PL (0x1 << PSTS_PL_BIT)
    196 #define PSTS_TT (0x1 << PSTS_TT_BIT)
    197 #define PSTS_RS (0x1 << PSTS_RS_BIT)
    198 #define PSTS_SR (0x1 << PSTS_SR_BIT)
    199 #define PSTS_LR (0x1 << PSTS_LR_BIT)
    200 #define PSTS_SP (0x1 << PSTS_SP_BIT)
    201 #define PSTS_AC (0x1 << PSTS_AC_BIT)
    202 #define PSTS_TS (0x1 << PSTS_TS_BIT)
    203 #define PSTS_ME (0x1 << PSTS_ME_BIT)
    204 #define PSTS_TF (0x1 << PSTS_TF_BIT)
    205 #define PSTS_RE (0x1 << PSTS_RE_BIT)
    206 #define PSTS_LS (0x7 << PSTS_LS_BIT)
    207 #define PSTS_IP (0x1f << PSTS_IP_BIT)
    208 #define PSTS_PR (0x1 << PSTS_PR_BIT)
    209 #define PSTS_PB (0x1 << PSTS_PB_BIT)
    210 #define PSTS_IA (0x1 << PSTS_IA_BIT)
    211 #define PSTS_CE (0x1 << PSTS_CE_BIT)
    212 #define PSTS_ER (0x1 << PSTS_ER_BIT)
    213 #define PSTS_DE (0x1 << PSTS_DE_BIT)
    214 #define PSTS_PE (0x1 << PSTS_PE_BIT)
    215 #define PSTS_WCLEAR (PSTS_PL | PSTS_TT | PSTS_RS | PSTS_SR | \
    216                                          PSTS_TS | PSTS_ME | PSTS_IA | PSTS_CE | \
    217                                          PSTS_ER | PSTS_DE | PSTS_PE)
    218 
    219 #define PSTS_PT_BIT 30
    220 #define PSTS_PL_BIT 29
    221 #define PSTS_TT_BIT 28
    222 #define PSTS_RS_BIT 27
    223 #define PSTS_SR_BIT 26
    224 #define PSTS_LR_BIT 22
    225 #define PSTS_SP_BIT 21
    226 #define PSTS_AC_BIT 20
    227 #define PSTS_TS_BIT 18
    228 #define PSTS_ME_BIT 17
    229 #define PSTS_TF_BIT 16
    230 #define PSTS_RE_BIT 15
    231 #define PSTS_LS_BIT 12
    232 #define PSTS_IP_BIT 7
    233 #define PSTS_PR_BIT 6
    234 #define PSTS_PB_BIT 5
    235 #define PSTS_IA_BIT 4
    236 #define PSTS_CE_BIT 3
    237 #define PSTS_ER_BIT 2
    238 #define PSTS_DE_BIT 1
    239 #define PSTS_PE_BIT 0
     117 * DEFINED IN HEADER
     118 */
    240119
    241120/*
     
    248127/*
    249128 * ROUTER PCTRL2 register fields
    250  */
    251 #define PCTRL2_SM (0xff << PCTRL2_SM_BIT)
    252 #define PCTRL2_SV (0xff << PCTRL2_SV_BIT)
    253 #define PCTRL2_OR (0x1 << PCTRL2_OR_BIT)
    254 #define PCTRL2_UR (0x1 << PCTRL2_UR_BIT)
    255 #define PCTRL2_AT (0x1 << PCTRL2_AT_BIT)
    256 #define PCTRL2_AR (0x1 << PCTRL2_AR_BIT)
    257 #define PCTRL2_IT (0x1 << PCTRL2_IT_BIT)
    258 #define PCTRL2_IR (0x1 << PCTRL2_IR_BIT)
    259 #define PCTRL2_SD (0x1f << PCTRL2_SD_BIT)
    260 #define PCTRL2_SC (0x1f << PCTRL2_SC_BIT)
    261 
    262 #define PCTRL2_SM_BIT 24
    263 #define PCTRL2_SV_BIT 16
    264 #define PCTRL2_OR_BIT 15
    265 #define PCTRL2_UR_BIT 14
    266 #define PCTRL2_AT_BIT 12
    267 #define PCTRL2_AR_BIT 11
    268 #define PCTRL2_IT_BIT 10
    269 #define PCTRL2_IR_BIT 9
    270 #define PCTRL2_SD_BIT 1
    271 #define PCTRL2_SC_BIT 0
     129 * DEFINED IN HEADER
     130 */
    272131
    273132/*
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