Changeset cc2fcc1 in rtems


Ignore:
Timestamp:
Oct 20, 2005, 6:38:26 PM (14 years ago)
Author:
Eric Norum <WENorum@…>
Branches:
4.10, 4.11, 4.8, 4.9, master
Children:
fab9046
Parents:
991522a2
Message:

Numerous changes and cleanups to support MVME2100.

Location:
c/src
Files:
10 edited

Legend:

Unmodified
Added
Removed
  • c/src/ChangeLog

    r991522a2 rcc2fcc1  
     12005-10-20  Eric Norum <norume@aps.anl.gov>
     2
     3    * libchip/network/dec21140.c: Clean up PCI mapping
     4
    152005-09-19      Ralf Corsepius <ralf.corsepius@rtems.org>
    26
  • c/src/lib/libbsp/powerpc/ChangeLog

    r991522a2 rcc2fcc1  
     12005-10-20      Eric Norum <norume@aps.anl.gov>
     2
     3    shared/pci/detect_raven_bridge.c: Support MVME2100
     4    shared/startup/bspstart.c: Support MVME2100
     5    shared/vme/VMEConfig.h: Support MVME2100
     6
    172005-10-17      Ralf Corsepius <ralf.corsepius@rtems.org>
    28
  • c/src/lib/libbsp/powerpc/motorola_powerpc/ChangeLog

    r991522a2 rcc2fcc1  
     12005-10-20      Eric Norum <norume@aps.anl.gov>
     2
     3    * include/bsp.h: Support MVME2100.
     4
    152005-05-26      Ralf Corsepius <ralf.corsepius@rtems.org>
    26
  • c/src/lib/libbsp/powerpc/motorola_powerpc/include/bsp.h

    r991522a2 rcc2fcc1  
    3939/* address of our ram on the PCI bus   */
    4040#define PCI_DRAM_OFFSET         CHRP_PCI_DRAM_OFFSET
    41 #define PCI_MEM_BASE            0x80000000
    42 #define PCI_MEM_BASE_ADJUSTMENT 0
     41#define PCI_MEM_BASE            0
     42#define PCI_MEM_WIN0            0x80000000
    4343
    4444#else
     
    4949/* offset of pci memory as seen from the CPU */
    5050#define PCI_MEM_BASE            PREP_ISA_MEM_BASE
    51 #define PCI_MEM_BASE_ADJUSTMENT PREP_ISA_MEM_BASE
     51#define PCI_MEM_WIN0            0
    5252#endif
    5353
  • c/src/lib/libbsp/powerpc/shared/pci/detect_raven_bridge.c

    r991522a2 rcc2fcc1  
    3333extern const pci_config_access_functions pci_indirect_functions;
    3434
     35#define PCI_ERR_BITS        0xf900
     36#define PCI_STATUS_OK(x)    (!((x)&PCI_ERR_BITS))
     37
     38/* For now, just clear errors in the PCI status reg.
     39 *
     40 * Returns: (for diagnostic purposes)
     41 *          original settings (i.e. before applying the clearing
     42 *          sequence) or the error bits or 0 if there were no errors.
     43 *
     44 */
     45
    3546unsigned long
    3647_BSP_clear_hostbridge_errors(int enableMCP, int quiet)
    3748{
    38 unsigned merst;
     49unsigned long   rval;
     50unsigned short  pcistat;
     51int             count;
    3952
    40     merst = in_be32(RAVEN_MPIC_MERST);
    41     /* write back value to clear status */
    42     out_be32(RAVEN_MPIC_MERST, merst);
     53    if (enableMCP)
     54        return -1; /* exceptions not supported / MCP not wired */
    4355
    44     if (enableMCP) {
    45       if (!quiet)
    46         printk("Enabling MCP generation on hostbridge errors\n");
    47       out_be32(RAVEN_MPIC_MEREN, MEREN_VAL);
    48     } else {
    49       out_be32(RAVEN_MPIC_MEREN, 0);
    50       if ( !quiet && enableMCP ) {
    51         printk("leaving MCP interrupt disabled\n");
    52       }
     56    /* read error status for info return */
     57    pci_read_config_word(0,0,0,PCI_STATUS,&pcistat);
     58    rval = pcistat;
     59
     60    count=10;
     61    do {
     62        /* clear error reporting registers */
     63
     64        /* clear PCI status register */
     65        pci_write_config_word(0,0,0,PCI_STATUS, PCI_ERR_BITS);
     66
     67        /* read  new status */
     68        pci_read_config_word(0,0,0,PCI_STATUS, &pcistat);
     69
     70    } while ( ! PCI_STATUS_OK(pcistat) && count-- );
     71
     72    if ( !PCI_STATUS_OK(rval) && !quiet) {
     73        printk("Cleared PCI errors: pci_stat was 0x%04x\n", rval);
    5374    }
    54     return (merst & 0xffff);
     75    if ( !PCI_STATUS_OK(pcistat) ) {
     76        printk("Unable to clear PCI errors: still 0x%04x after 10 attempts\n", pcistat);
     77    }
     78    return rval & PCI_ERR_BITS;
    5579}
    5680
  • c/src/lib/libbsp/powerpc/shared/startup/bspstart.c

    r991522a2 rcc2fcc1  
    334334   * T. Straumann: give more PCI address space
    335335   */
    336   setdbat(2, PCI_MEM_BASE, PCI_MEM_BASE, 0x10000000, IO_PAGE);
     336  setdbat(2, PCI_MEM_BASE+PCI_MEM_WIN0, PCI_MEM_BASE+PCI_MEM_WIN0, 0x10000000, IO_PAGE);
    337337
    338338  /*
  • c/src/lib/libbsp/powerpc/shared/vme/VMEConfig.h

    r991522a2 rcc2fcc1  
    1212 * layout:
    1313 */
     14#if defined(mvme2100)
     15#define _VME_A32_WIN0_ON_PCI    0x90000000
     16#define _VME_A24_ON_PCI                 0x9f000000
     17#define _VME_A16_ON_PCI                 0x9fff0000
     18#else
    1419#define _VME_A32_WIN0_ON_PCI    0x10000000
    1520#define _VME_A24_ON_PCI                 0x1f000000
    1621#define _VME_A16_ON_PCI                 0x1fff0000
     22#endif
    1723
    1824/* start of the A32 window on the VME bus
  • c/src/lib/libbsp/shared/ChangeLog

    r991522a2 rcc2fcc1  
     12005-10-20  Eric Norum <norume@aps.anl.gov>
     2
     3    vmeUniverse/vmeUniverse.c: Support MVME2100
     4
    152005-09-02      Joel Sherrill <joel@OARcorp.com>
    26
  • c/src/lib/libbsp/shared/vmeUniverse/vmeUniverse.c

    r991522a2 rcc2fcc1  
    7171typedef unsigned int pci_ulong;
    7272#define PCI_TO_LOCAL_ADDR(memaddr) \
    73     ((pci_ulong)(memaddr) + PCI_MEM_BASE_ADJUSTMENT)
     73    ((pci_ulong)(memaddr) + PCI_MEM_BASE)
    7474
    7575#elif defined(__vxworks)
  • c/src/libchip/network/dec21140.c

    r991522a2 rcc2fcc1  
    11191119
    11201120   tmp = (unsigned int)(lvalue & (unsigned int)(~MEM_MASK))
    1121       + (unsigned int)PCI_MEM_BASE_ADJUSTMENT;
     1121      + (unsigned int)PCI_MEM_BASE;
    11221122
    11231123   sc->base = (unsigned int *)(tmp);
Note: See TracChangeset for help on using the changeset viewer.