Changeset cbd9e63 in rtems


Ignore:
Timestamp:
Apr 17, 2014, 8:30:54 AM (5 years ago)
Author:
Ralf Kirchner <ralf.kirchner@…>
Branches:
4.11, master
Children:
92e2757
Parents:
9ee2ec5
git-author:
Ralf Kirchner <ralf.kirchner@…> (04/17/14 08:30:54)
git-committer:
Sebastian Huber <sebastian.huber@…> (04/17/14 11:25:11)
Message:

bsp/arm: Remove arm erratum 764369 from L2 cache

Arm erratum 764369 only applies to the level 1 cache.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h

    r9ee2ec5 rcbd9e63  
    899899#endif /* CACHE_ERRATA_CHECKS_FOR_IMPLEMENTED_ERRATAS */
    900900
    901 /* Errata Handlers */
    902 #if ( defined( RTEMS_SMP ) )
    903   #define CACHE_ARM_ERRATA_764369_HANDLER()                    \
    904     if( arm_errata_is_applicable_processor_errata_764369() ) { \
    905       _ARM_Data_synchronization_barrier();                     \
    906     }                                           
    907 #else /* #if ( defined( RTEMS_SMP ) ) */
    908   #define CACHE_ARM_ERRATA_764369_HANDLER()
    909 #endif /* #if ( defined( RTEMS_SMP ) ) */
    910 
    911901/* The common workaround for this erratum would be to add a
    912902 * data synchronization barrier to the beginning of the abort handler.
     
    10741064      ( (uint32_t) addr + n_bytes - 1 ) & ~CACHE_L2C_310_DATA_LINE_MASK;
    10751065    volatile L2CC *l2cc      = (volatile L2CC *) BSP_ARM_L2CC_BASE;
    1076 
    1077     CACHE_ARM_ERRATA_764369_HANDLER();
    10781066
    10791067    for (; adx <= ADDR_LAST; adx += CPU_DATA_CACHE_ALIGNMENT ) {
     
    14061394{
    14071395  if ( n_bytes > 0 ) {
    1408     CACHE_ARM_ERRATA_764369_HANDLER();
    14091396   
    14101397    cache_l2c_310_invalidate_range(
     
    14711458{
    14721459  if ( n_bytes != 0 ) {
    1473    CACHE_ARM_ERRATA_764369_HANDLER();
    14741460   
    14751461    /* Invalidate L2 cache lines */
Note: See TracChangeset for help on using the changeset viewer.