Changeset cbb615b in rtems
- Timestamp:
- 03/10/05 19:52:35 (19 years ago)
- Branches:
- 4.10, 4.11, 4.8, 4.9, 5, master
- Children:
- c995cd6
- Parents:
- 8008148
- Location:
- c/src/lib/libbsp/m68k/uC5282
- Files:
-
- 2 edited
Legend:
- Unmodified
- Added
- Removed
-
c/src/lib/libbsp/m68k/uC5282/ChangeLog
r8008148 rcbb615b 1 2005-03-10 Eric Norum <norume@aps.anl.gov> 2 3 * startup/bspstart.c: Add NOP after CACR writes. (work around hardware bug) 4 1 5 2005-02-14 Eric Norum <norume@aps.anl.gov> 2 6 -
c/src/lib/libbsp/m68k/uC5282/startup/bspstart.c
r8008148 rcbb615b 46 46 /* 47 47 * CPU-space access 48 */ 49 #define m68k_set_cacr(_cacr) asm volatile ("movec %0,%%cacr" : : "d" (_cacr)) 48 * The NOP after writing the CACR is there to address the following issue as 49 * described in "Device Errata MCF5282DE", Rev. 1.7, 09/2004: 50 * 51 * 6 Possible Cache Corruption after Setting CACR[CINV] 52 * 6.1 Description 53 * The cache on the MCF5282 was enhanced to function as a unified data and 54 * instruction cache, an instruction cache, or an operand cache. The cache 55 * function and organization is controlled by the cache control register (CACR). 56 * The CINV (Bit 24 = cache invalidate) bit in the CACR causes a cache clear. 57 * If the cache is configured as a unified cache and the CINV bit is set, the 58 * scope of the cache clear is controlled by two other bits in the CACR, 59 * INVI (BIT 21 = CINV instruction cache only) and INVD (BIT 20 = CINV data 60 * cache only). These bits allow the entire cache, just the instruction 61 * portion of the cache, or just the data portion of the cache to be cleared. 62 * If a write to the CACR is performed to clear the cache (CINV = BIT 24 set) 63 * and only a partial clear will be done (INVI = BIT 21 or INVD = BIT 20 set), 64 * then cache corruption may occur. 65 * 66 * 6.2 Workaround 67 * All loads of the CACR that perform a cache clear operation (CINV = BIT 24) 68 * should be followed immediately by a NOP instruction. This avoids the cache 69 * corruption problem. 70 * DATECODES AFFECTED: All 71 */ 72 #define m68k_set_cacr(_cacr) asm volatile ("movec %0,%%cacr ; nop" : : "d" (_cacr)) 50 73 #define m68k_set_acr0(_acr0) asm volatile ("movec %0,%%acr0" : : "d" (_acr0)) 51 74 #define m68k_set_acr1(_acr1) asm volatile ("movec %0,%%acr1" : : "d" (_acr1))
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