Index: bsps/m68k/shared/cache/cache.h
===================================================================
--- bsps/m68k/shared/cache/cache.h	(revision 4cf93658eff5cf6b0c02e98a0d1ec33dea5ed85c)
+++ bsps/m68k/shared/cache/cache.h	(revision cba349cf304527562ed34fdfe9c5f1b7656dacc4)
@@ -55,5 +55,5 @@
  */
 #define _CPU_CACR_OR(mask)                                         \
-	{                                                                \
+  {                                                                \
   register unsigned long _value = mask;                            \
   register unsigned long _ctl = 0;                                 \
@@ -77,9 +77,10 @@
 /* Only the mc68030 has a data cache; it is writethrough only. */
 
-void _CPU_cache_flush_1_data_line ( const void * d_addr ) {}
-void _CPU_cache_flush_entire_data ( void ) {}
-
-void _CPU_cache_invalidate_1_data_line (
-  const void * d_addr )
+RTEMS_INLINE_ROUTINE void _CPU_cache_flush_1_data_line(const void * d_addr) {}
+RTEMS_INLINE_ROUTINE void _CPU_cache_flush_entire_data(void) {}
+
+RTEMS_INLINE_ROUTINE void _CPU_cache_invalidate_1_data_line(
+  const void * d_addr
+)
 {
   void * p_address = (void *) _CPU_virtual_to_physical( d_addr );
@@ -88,24 +89,25 @@
 }
 
-void _CPU_cache_invalidate_entire_data ( void )
+RTEMS_INLINE_ROUTINE void _CPU_cache_invalidate_entire_data(void)
 {
   _CPU_CACR_OR( 0x00000800 );
 }
 
-void _CPU_cache_freeze_data ( void )
+RTEMS_INLINE_ROUTINE void _CPU_cache_freeze_data(void)
 {
   _CPU_CACR_OR( 0x00000200 );
 }
 
-void _CPU_cache_unfreeze_data ( void )
+RTEMS_INLINE_ROUTINE void _CPU_cache_unfreeze_data(void)
 {
   _CPU_CACR_AND( 0xFFFFFDFF );
 }
 
-void _CPU_cache_enable_data ( void )
+RTEMS_INLINE_ROUTINE void _CPU_cache_enable_data(void)
 {
   _CPU_CACR_OR( 0x00000100 );
 }
-void _CPU_cache_disable_data (	void )
+
+RTEMS_INLINE_ROUTINE void _CPU_cache_disable_data(void)
 {
   _CPU_CACR_AND( 0xFFFFFEFF );
@@ -116,33 +118,34 @@
 /* Both the 68020 and 68030 have instruction caches */
 
-void _CPU_cache_invalidate_1_instruction_line (
-  const void * d_addr )
-{
-  void * p_address = (void *) _CPU_virtual_to_physical( d_addr );
-  __asm__ volatile ( "movec %0, %%caar" :: "a" (p_address) );      /* write caar */
+RTEMS_INLINE_ROUTINE void _CPU_cache_invalidate_1_instruction_line(
+  const void * d_addr
+)
+{
+  void * p_address = (void *) _CPU_virtual_to_physical( d_addr );
+  __asm__ volatile ( "movec %0, %%caar" :: "a" (p_address) ); /* write caar */
   _CPU_CACR_OR( 0x00000004 );
 }
 
-void _CPU_cache_invalidate_entire_instruction ( void )
+RTEMS_INLINE_ROUTINE void _CPU_cache_invalidate_entire_instruction(void)
 {
   _CPU_CACR_OR( 0x00000008 );
 }
 
-void _CPU_cache_freeze_instruction ( void )
+RTEMS_INLINE_ROUTINE void _CPU_cache_freeze_instruction(void)
 {
   _CPU_CACR_OR( 0x00000002);
 }
 
-void _CPU_cache_unfreeze_instruction ( void )
+RTEMS_INLINE_ROUTINE void _CPU_cache_unfreeze_instruction(void)
 {
   _CPU_CACR_AND( 0xFFFFFFFD );
 }
 
-void _CPU_cache_enable_instruction ( void )
+RTEMS_INLINE_ROUTINE void _CPU_cache_enable_instruction(void)
 {
   _CPU_CACR_OR( 0x00000001 );
 }
 
-void _CPU_cache_disable_instruction (	void )
+RTEMS_INLINE_ROUTINE void _CPU_cache_disable_instruction(void)
 {
   _CPU_CACR_AND( 0xFFFFFFFE );
@@ -153,11 +156,12 @@
 
 /* Cannot be frozen */
-void _CPU_cache_freeze_data ( void ) {}
-void _CPU_cache_unfreeze_data ( void ) {}
-void _CPU_cache_freeze_instruction ( void ) {}
-void _CPU_cache_unfreeze_instruction ( void ) {}
-
-void _CPU_cache_flush_1_data_line (
-  const void * d_addr )
+RTEMS_INLINE_ROUTINE void _CPU_cache_freeze_data(void) {}
+RTEMS_INLINE_ROUTINE void _CPU_cache_unfreeze_data(void) {}
+RTEMS_INLINE_ROUTINE void _CPU_cache_freeze_instruction(void) {}
+RTEMS_INLINE_ROUTINE void _CPU_cache_unfreeze_instruction(void) {}
+
+RTEMS_INLINE_ROUTINE void _CPU_cache_flush_1_data_line(
+  const void * d_addr
+)
 {
   void * p_address = (void *) _CPU_virtual_to_physical( d_addr );
@@ -165,6 +169,7 @@
 }
 
-void _CPU_cache_invalidate_1_data_line (
-  const void * d_addr )
+RTEMS_INLINE_ROUTINE void _CPU_cache_invalidate_1_data_line(
+  const void * d_addr
+)
 {
   void * p_address = (void *) _CPU_virtual_to_physical( d_addr );
@@ -172,25 +177,25 @@
 }
 
-void _CPU_cache_flush_entire_data ( void )
-{
-	asm volatile ( "cpusha %%dc" :: );
-}
-
-void _CPU_cache_invalidate_entire_data ( void )
-{
-	asm volatile ( "cinva %%dc" :: );
-}
-
-void _CPU_cache_enable_data ( void )
+RTEMS_INLINE_ROUTINE void _CPU_cache_flush_entire_data(void)
+{
+  __asm__ volatile ( "cpusha %%dc" :: );
+}
+
+RTEMS_INLINE_ROUTINE void _CPU_cache_invalidate_entire_data(void)
+{
+  __asm__ volatile ( "cinva %%dc" :: );
+}
+
+RTEMS_INLINE_ROUTINE void _CPU_cache_enable_data(void)
 {
   _CPU_CACR_OR( 0x80000000 );
 }
 
-void _CPU_cache_disable_data ( void )
+RTEMS_INLINE_ROUTINE void _CPU_cache_disable_data(void)
 {
   _CPU_CACR_AND( 0x7FFFFFFF );
 }
 
-void _CPU_cache_invalidate_1_instruction_line (
+RTEMS_INLINE_ROUTINE void _CPU_cache_invalidate_1_instruction_line(
   const void * i_addr )
 {
@@ -199,17 +204,17 @@
 }
 
-void _CPU_cache_invalidate_entire_instruction ( void )
-{
-		asm volatile ( "cinva %%ic" :: );
-}
-
-void _CPU_cache_enable_instruction ( void )
+RTEMS_INLINE_ROUTINE void _CPU_cache_invalidate_entire_instruction(void)
+{
+  __asm__ volatile ( "cinva %%ic" :: );
+}
+
+RTEMS_INLINE_ROUTINE void _CPU_cache_enable_instruction(void)
 {
   _CPU_CACR_OR( 0x00008000 );
 }
 
-void _CPU_cache_disable_instruction ( void )
-{
-	_CPU_CACR_AND( 0xFFFF7FFF );
-}
-#endif
+RTEMS_INLINE_ROUTINE void _CPU_cache_disable_instruction(void)
+{
+  _CPU_CACR_AND( 0xFFFF7FFF );
+}
+#endif
