Changeset cba349c in rtems


Ignore:
Timestamp:
Aug 17, 2018, 6:30:19 PM (11 months ago)
Author:
Joel Sherrill <joel@…>
Branches:
master
Children:
14a218f
Parents:
9e8bba5
git-author:
Joel Sherrill <joel@…> (08/17/18 18:30:19)
git-committer:
Joel Sherrill <joel@…> (08/29/18 17:52:08)
Message:

bsps/m68k/shared/cache/cache.h: Fix warnings and clean up

File:
1 edited

Legend:

Unmodified
Added
Removed
  • bsps/m68k/shared/cache/cache.h

    r9e8bba5 rcba349c  
    5555 */
    5656#define _CPU_CACR_OR(mask)                                         \
    57         {                                                                \
     57  {                                                                \
    5858  register unsigned long _value = mask;                            \
    5959  register unsigned long _ctl = 0;                                 \
     
    7777/* Only the mc68030 has a data cache; it is writethrough only. */
    7878
    79 void _CPU_cache_flush_1_data_line ( const void * d_addr ) {}
    80 void _CPU_cache_flush_entire_data ( void ) {}
    81 
    82 void _CPU_cache_invalidate_1_data_line (
    83   const void * d_addr )
     79RTEMS_INLINE_ROUTINE void _CPU_cache_flush_1_data_line(const void * d_addr) {}
     80RTEMS_INLINE_ROUTINE void _CPU_cache_flush_entire_data(void) {}
     81
     82RTEMS_INLINE_ROUTINE void _CPU_cache_invalidate_1_data_line(
     83  const void * d_addr
     84)
    8485{
    8586  void * p_address = (void *) _CPU_virtual_to_physical( d_addr );
     
    8889}
    8990
    90 void _CPU_cache_invalidate_entire_data ( void )
     91RTEMS_INLINE_ROUTINE void _CPU_cache_invalidate_entire_data(void)
    9192{
    9293  _CPU_CACR_OR( 0x00000800 );
    9394}
    9495
    95 void _CPU_cache_freeze_data ( void )
     96RTEMS_INLINE_ROUTINE void _CPU_cache_freeze_data(void)
    9697{
    9798  _CPU_CACR_OR( 0x00000200 );
    9899}
    99100
    100 void _CPU_cache_unfreeze_data ( void )
     101RTEMS_INLINE_ROUTINE void _CPU_cache_unfreeze_data(void)
    101102{
    102103  _CPU_CACR_AND( 0xFFFFFDFF );
    103104}
    104105
    105 void _CPU_cache_enable_data ( void )
     106RTEMS_INLINE_ROUTINE void _CPU_cache_enable_data(void)
    106107{
    107108  _CPU_CACR_OR( 0x00000100 );
    108109}
    109 void _CPU_cache_disable_data (  void )
     110
     111RTEMS_INLINE_ROUTINE void _CPU_cache_disable_data(void)
    110112{
    111113  _CPU_CACR_AND( 0xFFFFFEFF );
     
    116118/* Both the 68020 and 68030 have instruction caches */
    117119
    118 void _CPU_cache_invalidate_1_instruction_line (
    119   const void * d_addr )
    120 {
    121   void * p_address = (void *) _CPU_virtual_to_physical( d_addr );
    122   __asm__ volatile ( "movec %0, %%caar" :: "a" (p_address) );      /* write caar */
     120RTEMS_INLINE_ROUTINE void _CPU_cache_invalidate_1_instruction_line(
     121  const void * d_addr
     122)
     123{
     124  void * p_address = (void *) _CPU_virtual_to_physical( d_addr );
     125  __asm__ volatile ( "movec %0, %%caar" :: "a" (p_address) ); /* write caar */
    123126  _CPU_CACR_OR( 0x00000004 );
    124127}
    125128
    126 void _CPU_cache_invalidate_entire_instruction ( void )
     129RTEMS_INLINE_ROUTINE void _CPU_cache_invalidate_entire_instruction(void)
    127130{
    128131  _CPU_CACR_OR( 0x00000008 );
    129132}
    130133
    131 void _CPU_cache_freeze_instruction ( void )
     134RTEMS_INLINE_ROUTINE void _CPU_cache_freeze_instruction(void)
    132135{
    133136  _CPU_CACR_OR( 0x00000002);
    134137}
    135138
    136 void _CPU_cache_unfreeze_instruction ( void )
     139RTEMS_INLINE_ROUTINE void _CPU_cache_unfreeze_instruction(void)
    137140{
    138141  _CPU_CACR_AND( 0xFFFFFFFD );
    139142}
    140143
    141 void _CPU_cache_enable_instruction ( void )
     144RTEMS_INLINE_ROUTINE void _CPU_cache_enable_instruction(void)
    142145{
    143146  _CPU_CACR_OR( 0x00000001 );
    144147}
    145148
    146 void _CPU_cache_disable_instruction (   void )
     149RTEMS_INLINE_ROUTINE void _CPU_cache_disable_instruction(void)
    147150{
    148151  _CPU_CACR_AND( 0xFFFFFFFE );
     
    153156
    154157/* Cannot be frozen */
    155 void _CPU_cache_freeze_data ( void ) {}
    156 void _CPU_cache_unfreeze_data ( void ) {}
    157 void _CPU_cache_freeze_instruction ( void ) {}
    158 void _CPU_cache_unfreeze_instruction ( void ) {}
    159 
    160 void _CPU_cache_flush_1_data_line (
    161   const void * d_addr )
     158RTEMS_INLINE_ROUTINE void _CPU_cache_freeze_data(void) {}
     159RTEMS_INLINE_ROUTINE void _CPU_cache_unfreeze_data(void) {}
     160RTEMS_INLINE_ROUTINE void _CPU_cache_freeze_instruction(void) {}
     161RTEMS_INLINE_ROUTINE void _CPU_cache_unfreeze_instruction(void) {}
     162
     163RTEMS_INLINE_ROUTINE void _CPU_cache_flush_1_data_line(
     164  const void * d_addr
     165)
    162166{
    163167  void * p_address = (void *) _CPU_virtual_to_physical( d_addr );
     
    165169}
    166170
    167 void _CPU_cache_invalidate_1_data_line (
    168   const void * d_addr )
     171RTEMS_INLINE_ROUTINE void _CPU_cache_invalidate_1_data_line(
     172  const void * d_addr
     173)
    169174{
    170175  void * p_address = (void *) _CPU_virtual_to_physical( d_addr );
     
    172177}
    173178
    174 void _CPU_cache_flush_entire_data ( void )
    175 {
    176         asm volatile ( "cpusha %%dc" :: );
    177 }
    178 
    179 void _CPU_cache_invalidate_entire_data ( void )
    180 {
    181         asm volatile ( "cinva %%dc" :: );
    182 }
    183 
    184 void _CPU_cache_enable_data ( void )
     179RTEMS_INLINE_ROUTINE void _CPU_cache_flush_entire_data(void)
     180{
     181  __asm__ volatile ( "cpusha %%dc" :: );
     182}
     183
     184RTEMS_INLINE_ROUTINE void _CPU_cache_invalidate_entire_data(void)
     185{
     186  __asm__ volatile ( "cinva %%dc" :: );
     187}
     188
     189RTEMS_INLINE_ROUTINE void _CPU_cache_enable_data(void)
    185190{
    186191  _CPU_CACR_OR( 0x80000000 );
    187192}
    188193
    189 void _CPU_cache_disable_data ( void )
     194RTEMS_INLINE_ROUTINE void _CPU_cache_disable_data(void)
    190195{
    191196  _CPU_CACR_AND( 0x7FFFFFFF );
    192197}
    193198
    194 void _CPU_cache_invalidate_1_instruction_line (
     199RTEMS_INLINE_ROUTINE void _CPU_cache_invalidate_1_instruction_line(
    195200  const void * i_addr )
    196201{
     
    199204}
    200205
    201 void _CPU_cache_invalidate_entire_instruction ( void )
    202 {
    203                 asm volatile ( "cinva %%ic" :: );
    204 }
    205 
    206 void _CPU_cache_enable_instruction ( void )
     206RTEMS_INLINE_ROUTINE void _CPU_cache_invalidate_entire_instruction(void)
     207{
     208  __asm__ volatile ( "cinva %%ic" :: );
     209}
     210
     211RTEMS_INLINE_ROUTINE void _CPU_cache_enable_instruction(void)
    207212{
    208213  _CPU_CACR_OR( 0x00008000 );
    209214}
    210215
    211 void _CPU_cache_disable_instruction ( void )
    212 {
    213         _CPU_CACR_AND( 0xFFFF7FFF );
    214 }
    215 #endif
     216RTEMS_INLINE_ROUTINE void _CPU_cache_disable_instruction(void)
     217{
     218  _CPU_CACR_AND( 0xFFFF7FFF );
     219}
     220#endif
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