- Timestamp:
- 06/26/15 19:39:16 (9 years ago)
- Branches:
- 4.11, 5, master
- Children:
- fdb45d6
- Parents:
- d84408a9
- File:
-
- 1 edited
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doc/cpu_supplement/arm.t
rd84408a9 rcb2b8f0 153 153 @subsection Interrupt Levels 154 154 155 The RTEMS interrupt level mapping scheme for the ARM is not a numeric level as 156 on most RTEMS ports. It is a bit mapping that corresponds the enable bit 157 postions in the Current Program Status Register (CPSR). There are only two 158 levels: IRQ enabled and IRQ disabled. 155 There are exactly two interrupt levels on ARM with respect to RTEMS. Level 156 zero corresponds to interrupts enabled. Level one corresponds to interrupts 157 disabled. 159 158 160 159 @subsection Interrupt Stack
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