Changeset cb2b8f0 in rtems


Ignore:
Timestamp:
Jun 26, 2015, 7:39:16 PM (4 years ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
4.11, master
Children:
fdb45d6
Parents:
d84408a9
Message:

doc: Fix interrupt level ARM documentation

File:
1 edited

Legend:

Unmodified
Added
Removed
  • doc/cpu_supplement/arm.t

    rd84408a9 rcb2b8f0  
    153153@subsection Interrupt Levels
    154154
    155 The RTEMS interrupt level mapping scheme for the ARM is not a numeric level as
    156 on most RTEMS ports.  It is a bit mapping that corresponds the enable bit
    157 postions in the Current Program Status Register (CPSR).  There are only two
    158 levels: IRQ enabled and IRQ disabled.
     155There are exactly two interrupt levels on ARM with respect to RTEMS.  Level
     156zero corresponds to interrupts enabled.  Level one corresponds to interrupts
     157disabled.
    159158 
    160159@subsection Interrupt Stack
Note: See TracChangeset for help on using the changeset viewer.