Changeset ca59217 in rtems


Ignore:
Timestamp:
Jun 28, 2013, 7:03:11 AM (6 years ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
4.11, master
Children:
4800ffe
Parents:
a3a4cd5
git-author:
Sebastian Huber <sebastian.huber@…> (06/28/13 07:03:11)
git-committer:
Sebastian Huber <sebastian.huber@…> (06/28/13 07:04:47)
Message:

bsps/arm: Set vector base on all processors

File:
1 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/arm/shared/include/arm-a9mpcore-start.h

    ra3a4cd5 rca59217  
    4343arm_cp15_set_vector_base_address(void *base);
    4444
     45BSP_START_TEXT_SECTION static inline arm_a9mpcore_start_set_vector_base(void)
     46{
     47  /*
     48   * Do not use bsp_vector_table_begin == 0, since this will get optimized away.
     49  */
     50  if (bsp_vector_table_end != bsp_vector_table_size) {
     51    uint32_t ctrl;
     52
     53    /*
     54     * For now we assume that every Cortex-A9 MPCore has the Security Extensions.
     55     * Later it might be necessary to evaluate the ID_PFR1 register.
     56     */
     57    arm_cp15_set_vector_base_address(bsp_vector_table_begin);
     58
     59    ctrl = arm_cp15_get_control();
     60    ctrl &= ~ARM_CP15_CTRL_V;
     61    arm_cp15_set_control(ctrl);
     62  }
     63}
     64
    4565BSP_START_TEXT_SECTION static inline arm_a9mpcore_start_hook_0(void)
    4666{
     
    6080  cpu_id = arm_cortex_a9_get_multiprocessor_cpu_id();
    6181  if (cpu_id != 0) {
     82    arm_a9mpcore_start_set_vector_base();
     83
    6284    if (cpu_id < rtems_configuration_get_maximum_processors()) {
    6385      uint32_t ctrl;
     
    93115BSP_START_TEXT_SECTION static inline arm_a9mpcore_start_hook_1(void)
    94116{
    95   /*
    96    * Do not use bsp_vector_table_begin == 0, since this will get optimized away.
    97   */
    98   if (bsp_vector_table_end != bsp_vector_table_size) {
    99     uint32_t ctrl;
    100 
    101     /*
    102      * For now we assume that every Cortex-A9 MPCore has the Security Extensions.
    103      * Later it might be necessary to evaluate the ID_PFR1 register.
    104      */
    105     arm_cp15_set_vector_base_address(bsp_vector_table_begin);
    106 
    107     ctrl = arm_cp15_get_control();
    108     ctrl &= ~ARM_CP15_CTRL_V;
    109     arm_cp15_set_control(ctrl);
    110   }
     117  arm_a9mpcore_start_set_vector_base();
    111118}
    112119
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