Changeset c9274ae in rtems for c/src/lib/libcpu/arm


Ignore:
Timestamp:
Oct 5, 2007, 6:57:52 PM (13 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.9, master
Children:
5a9f372
Parents:
9aab34c
Message:

2007-10-05 Ray Xu <xr@…>

  • lpc22xx/clock/clockdrv.c, lpc22xx/irq/irq.c, lpc22xx/irq/irq.h: Now runs in Skyeye.
Location:
c/src/lib/libcpu/arm
Files:
4 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libcpu/arm/ChangeLog

    r9aab34c rc9274ae  
     12007-10-05      Ray Xu <xr@trasin.net>
     2
     3        * lpc22xx/clock/clockdrv.c, lpc22xx/irq/irq.c, lpc22xx/irq/irq.h: Now
     4        runs in Skyeye.
     5
    162007-09-12      Joel Sherrill <joel.sherrill@OARcorp.com>
    27
  • c/src/lib/libcpu/arm/lpc22xx/clock/clockdrv.c

    r9aab34c rc9274ae  
    5353 do {                                                   \
    5454          if (!(T0IR & 0x01)) return;   \
    55           T0IR = 0x01;                          \
     55          T0IR = 0x01;                  \
    5656          VICVectAddr = 0x00;\
    5757 } while(0)
     
    8686  do { \
    8787        T0TCR &= 0;      /* disable and clear timer 0, set to  */ \
    88        T0PC  = 0;            /* TC is incrementet on every pclk.*/ \
     88        T0PC  = 0;            /* TC is incrementet on every pclk.*/ \
    8989        T0MR0 = ((LPC22xx_Fpclk/1000* BSP_Configuration.microseconds_per_tick) / 1000); /* initialize the timer period and prescaler */  \
    9090        /*T0PR = (((LPC22xx_Fpclk / 1000) * BSP_Configuration.microseconds_per_tick) / 1000-1); \ */ \
    9191        T0MCR |= 0x03;            /* generate interrupt when T0MR0 match T0TC and Reset Timer Count*/ \
    92        T0EMR = 0;  /*No external match*/ \
     92        T0EMR = 0;  /*No external match*/ \
    9393        T0TCR = 1; /*enable timer0*/ \
     94        T0IR|=0x01;/*enable interrupt, skyeye will check this*/\
    9495   } while (0)
    9596
  • c/src/lib/libcpu/arm/lpc22xx/irq/irq.c

    r9aab34c rc9274ae  
    3838    rtems_irq_hdl        *bsp_tbl;
    3939    int                  *vic_cntl;
    40     static int            irq_counter = 0;
    4140   
    4241    bsp_tbl = (rtems_irq_hdl *)VICVectAddrBase;
     
    5251     */
    5352
    54     if (bsp_tbl[irq_counter] != default_int_handler) {
     53    if (bsp_tbl[irq->name] != default_int_handler) {
    5554      return 0;
    5655    }
     
    6160     * store the new handler
    6261     */
    63     bsp_tbl[irq_counter] = irq->hdl;
     62    bsp_tbl[irq->name] = irq->hdl;
    6463    /* *(volatile unsigned long*)(VICVectAddr0+(irq->name * 4)&0x7c )= (uint32_t) irq->hdl;*/
    6564    /*
    6665     * Enable interrupt on device
    6766     */
    68     vic_cntl[irq_counter] = 0x20 | irq->name;
     67    vic_cntl[irq->name] = 0x20 | irq->name;
    6968
    7069    VICIntEnable |= 1 << irq->name;
     
    7574    }
    7675
    77     irq_counter++;   
    7876
    7977    rtems_interrupt_enable(level);
  • c/src/lib/libcpu/arm/lpc22xx/irq/irq.h

    r9aab34c rc9274ae  
    5555#define LPC22xx_INTERRUPT_EINT3 17      /* Externel Interrupt 3 */
    5656#define LPC22xx_INTERRUPT_ADC   18      /* AD Converter */
     57/* Following interrupt used by lpc229x */
    5758#define LPC22xx_INTERRUPT_CANERR 19     /* CAN LUTerr interrupt */
    5859#define LPC22xx_INTERRUPT_CAN1TX 20     /* CAN1 Tx interrupt */
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