Changeset c8df844 in rtems
- Timestamp:
- 06/19/18 12:59:51 (5 years ago)
- Branches:
- 5, master
- Children:
- 715d616
- Parents:
- 196ce18
- git-author:
- Sebastian Huber <sebastian.huber@…> (06/19/18 12:59:51)
- git-committer:
- Sebastian Huber <sebastian.huber@…> (06/27/18 06:58:16)
- Location:
- cpukit/score/cpu
- Files:
-
- 18 edited
Legend:
- Unmodified
- Added
- Removed
-
cpukit/score/cpu/arm/include/rtems/score/cpu.h
r196ce18 rc8df844 165 165 /* AAPCS, section 5.2.1.2, Stack constraints at a public interface */ 166 166 #define CPU_STACK_ALIGNMENT 8 167 168 #define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES 167 169 168 170 /* -
cpukit/score/cpu/bfin/include/rtems/score/cpu.h
r196ce18 rc8df844 563 563 */ 564 564 #define CPU_STACK_ALIGNMENT 8 565 566 #define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES 565 567 566 568 #ifndef ASM -
cpukit/score/cpu/epiphany/include/rtems/score/cpu.h
r196ce18 rc8df844 466 466 #define CPU_STACK_ALIGNMENT 8 467 467 468 #define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES 469 468 470 /* ISR handler macros */ 469 471 -
cpukit/score/cpu/i386/include/rtems/score/cpu.h
r196ce18 rc8df844 384 384 #define CPU_STACK_ALIGNMENT 16 385 385 386 #define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES 387 386 388 /* macros */ 387 389 -
cpukit/score/cpu/lm32/include/rtems/score/cpu.h
r196ce18 rc8df844 582 582 #define CPU_STACK_ALIGNMENT CPU_ALIGNMENT 583 583 584 #define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES 585 584 586 /* 585 587 * ISR handler macros -
cpukit/score/cpu/m32c/include/rtems/score/cpu.h
r196ce18 rc8df844 556 556 */ 557 557 #define CPU_STACK_ALIGNMENT 0 558 559 #define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES 558 560 559 561 /* -
cpukit/score/cpu/m68k/include/rtems/score/cpu.h
r196ce18 rc8df844 354 354 355 355 #define CPU_STACK_ALIGNMENT 0 356 357 #define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES 356 358 357 359 #ifndef ASM -
cpukit/score/cpu/mips/include/rtems/score/cpu.h
r196ce18 rc8df844 632 632 #define CPU_STACK_ALIGNMENT CPU_ALIGNMENT 633 633 634 #define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES 635 634 636 void mips_vector_exceptions( CPU_Interrupt_frame *frame ); 635 637 -
cpukit/score/cpu/moxie/include/rtems/score/cpu.h
r196ce18 rc8df844 466 466 #define CPU_STACK_ALIGNMENT 0 467 467 468 #define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES 469 468 470 /* 469 471 * ISR handler macros -
cpukit/score/cpu/nios2/include/rtems/score/cpu.h
r196ce18 rc8df844 87 87 */ 88 88 #define CPU_STACK_ALIGNMENT 4 89 90 #define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES 89 91 90 92 /* -
cpukit/score/cpu/no_cpu/include/rtems/score/cpu.h
r196ce18 rc8df844 696 696 #define CPU_STACK_ALIGNMENT 0 697 697 698 /** 699 * The alignment of the interrupt stack in bytes. 700 * 701 * The alignment should take the stack ABI and the cache line size into 702 * account. 703 */ 704 #define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES 705 698 706 /* 699 707 * ISR handler macros -
cpukit/score/cpu/or1k/include/rtems/score/cpu.h
r196ce18 rc8df844 463 463 #define CPU_STACK_ALIGNMENT 0 464 464 465 #define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES 466 465 467 /* ISR handler macros */ 466 468 -
cpukit/score/cpu/powerpc/include/rtems/score/cpu.h
r196ce18 rc8df844 762 762 #define CPU_STACK_ALIGNMENT (PPC_STACK_ALIGNMENT) 763 763 764 #define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES 765 764 766 #ifndef ASM 765 767 /* The following routine swaps the endian format of an unsigned int. -
cpukit/score/cpu/riscv/include/rtems/score/cpu.h
r196ce18 rc8df844 138 138 Context_Control_fp _CPU_Null_fp_context; 139 139 140 #define CPU_CACHE_LINE_BYTES 64 141 140 142 #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 141 143 #if __riscv_xlen == 32 … … 149 151 #define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT 150 152 #define CPU_STACK_ALIGNMENT 8 153 154 #define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES 155 151 156 #define _CPU_Initialize_vectors() 152 157 -
cpukit/score/cpu/sh/include/rtems/score/cpu.h
r196ce18 rc8df844 438 438 439 439 #define CPU_STACK_ALIGNMENT CPU_ALIGNMENT 440 441 #define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES 440 442 441 443 /* -
cpukit/score/cpu/sparc/include/rtems/score/cpu.h
r196ce18 rc8df844 824 824 #define CPU_STACK_ALIGNMENT CPU_ALIGNMENT 825 825 826 #define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES 827 826 828 #ifndef ASM 827 829 -
cpukit/score/cpu/sparc64/include/rtems/score/cpu.h
r196ce18 rc8df844 710 710 #define CPU_STACK_ALIGNMENT 16 711 711 712 #define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES 713 712 714 #ifndef ASM 713 715 -
cpukit/score/cpu/v850/include/rtems/score/cpu.h
r196ce18 rc8df844 525 525 #define CPU_STACK_ALIGNMENT 4 526 526 527 #define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES 528 527 529 /* 528 530 * ISR handler macros
Note: See TracChangeset
for help on using the changeset viewer.