Changeset c8df844 in rtems

Timestamp:

06/19/18 12:59:51 (5 years ago)

Author:

Sebastian Huber <sebastian.huber@…>

Branches:

5, master

Children:

715d616

Parents:

196ce18

git-author:

Sebastian Huber <sebastian.huber@…> (06/19/18 12:59:51)

git-committer:

Sebastian Huber <sebastian.huber@…> (06/27/18 06:58:16)

Message:

score: Add CPU_INTERRUPT_STACK_ALIGNMENT

Add CPU port define for the interrupt stack alignment. The alignment
should take the stack ABI and the cache line size into account.

Update #3459.

Location:

cpukit/score/cpu

Files:

• arm/include/rtems/score/cpu.h (modified) (1 diff)
• bfin/include/rtems/score/cpu.h (modified) (1 diff)
• epiphany/include/rtems/score/cpu.h (modified) (1 diff)
• i386/include/rtems/score/cpu.h (modified) (1 diff)
• lm32/include/rtems/score/cpu.h (modified) (1 diff)
• m32c/include/rtems/score/cpu.h (modified) (1 diff)
• m68k/include/rtems/score/cpu.h (modified) (1 diff)
• mips/include/rtems/score/cpu.h (modified) (1 diff)
• moxie/include/rtems/score/cpu.h (modified) (1 diff)
• nios2/include/rtems/score/cpu.h (modified) (1 diff)
• no_cpu/include/rtems/score/cpu.h (modified) (1 diff)
• or1k/include/rtems/score/cpu.h (modified) (1 diff)
• powerpc/include/rtems/score/cpu.h (modified) (1 diff)
• riscv/include/rtems/score/cpu.h (modified) (2 diffs)
• sh/include/rtems/score/cpu.h (modified) (1 diff)
• sparc/include/rtems/score/cpu.h (modified) (1 diff)
• sparc64/include/rtems/score/cpu.h (modified) (1 diff)
• v850/include/rtems/score/cpu.h (modified) (1 diff)

cpukit/score/cpu/arm/include/rtems/score/cpu.h

@@ -165 +165 @@
 /* AAPCS, section 5.2.1.2, Stack constraints at a public interface */
 #define CPU_STACK_ALIGNMENT 8
+
+#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
 
 /*

cpukit/score/cpu/bfin/include/rtems/score/cpu.h

@@ -563 +563 @@
  */
 #define CPU_STACK_ALIGNMENT        8
+
+#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
 
 #ifndef ASM

cpukit/score/cpu/epiphany/include/rtems/score/cpu.h

@@ -466 +466 @@
 #define CPU_STACK_ALIGNMENT        8
 
+#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
+
 /* ISR handler macros */
 

cpukit/score/cpu/i386/include/rtems/score/cpu.h

@@ -384 +384 @@
 #define CPU_STACK_ALIGNMENT             16
 
+#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
+
 /* macros */
 

cpukit/score/cpu/lm32/include/rtems/score/cpu.h

@@ -582 +582 @@
 #define CPU_STACK_ALIGNMENT        CPU_ALIGNMENT
 
+#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
+
 /*
  *  ISR handler macros

cpukit/score/cpu/m32c/include/rtems/score/cpu.h

@@ -556 +556 @@
  */
 #define CPU_STACK_ALIGNMENT        0
+
+#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
 
 /*

cpukit/score/cpu/m68k/include/rtems/score/cpu.h

@@ -354 +354 @@
 
 #define CPU_STACK_ALIGNMENT        0
+
+#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
 
 #ifndef ASM

cpukit/score/cpu/mips/include/rtems/score/cpu.h

@@ -632 +632 @@
 #define CPU_STACK_ALIGNMENT        CPU_ALIGNMENT
 
+#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
+
 void mips_vector_exceptions( CPU_Interrupt_frame *frame );
 

cpukit/score/cpu/moxie/include/rtems/score/cpu.h

@@ -466 +466 @@
 #define CPU_STACK_ALIGNMENT        0
 
+#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
+
 /*
  *  ISR handler macros

cpukit/score/cpu/nios2/include/rtems/score/cpu.h

@@ -87 +87 @@
  */
 #define CPU_STACK_ALIGNMENT 4
+
+#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
 
 /*

cpukit/score/cpu/no_cpu/include/rtems/score/cpu.h

@@ -696 +696 @@
 #define CPU_STACK_ALIGNMENT        0
 
+/**
+ * The alignment of the interrupt stack in bytes.
+ *
+ * The alignment should take the stack ABI and the cache line size into
+ * account.
+ */
+#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
+
 /*
  *  ISR handler macros

cpukit/score/cpu/or1k/include/rtems/score/cpu.h

@@ -463 +463 @@
 #define CPU_STACK_ALIGNMENT        0
 
+#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
+
 /* ISR handler macros */
 

cpukit/score/cpu/powerpc/include/rtems/score/cpu.h

@@ -762 +762 @@
 #define CPU_STACK_ALIGNMENT        (PPC_STACK_ALIGNMENT)
 
+#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
+
 #ifndef ASM
 /*  The following routine swaps the endian format of an unsigned int.

cpukit/score/cpu/riscv/include/rtems/score/cpu.h

@@ -138 +138 @@
 Context_Control_fp  _CPU_Null_fp_context;
 
+#define CPU_CACHE_LINE_BYTES 64
+
 #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
 #if __riscv_xlen == 32
@@ -149 +151 @@
 #define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
 #define CPU_STACK_ALIGNMENT        8
+
+#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
+
 #define _CPU_Initialize_vectors()
 

cpukit/score/cpu/sh/include/rtems/score/cpu.h

@@ -438 +438 @@
 
 #define CPU_STACK_ALIGNMENT        CPU_ALIGNMENT
+
+#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
 
 /*

cpukit/score/cpu/sparc/include/rtems/score/cpu.h

@@ -824 +824 @@
 #define CPU_STACK_ALIGNMENT CPU_ALIGNMENT
 
+#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
+
 #ifndef ASM
 

cpukit/score/cpu/sparc64/include/rtems/score/cpu.h

@@ -710 +710 @@
 #define CPU_STACK_ALIGNMENT        16
 
+#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
+
 #ifndef ASM
 

cpukit/score/cpu/v850/include/rtems/score/cpu.h

@@ -525 +525 @@
 #define CPU_STACK_ALIGNMENT        4
 
+#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
+
 /*
  *  ISR handler macros