Ignore:
Timestamp:
Aug 1, 1995, 3:33:39 PM (26 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, 5, master
Children:
4f90134
Parents:
4a6e64d
Message:

updated mvme162 code from Misha (mms@…)

File:
1 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/m68k/mvme162/clock/ckinit.c

    r4a6e64d rc6fb8e90  
    3333
    3434#define MS_COUNT          1000            /* T2's countdown constant (1 ms) */
    35 #define CLOCK_INT_LEVEL   6                         /* T2's interrupt level */
     35#define CLOCK_INT_LEVEL   6               /* T2's interrupt level */
    3636
    37 rtems_unsigned32 Clock_isrs;        /* ISRs until next tick */
    38 volatile rtems_unsigned32 Clock_driver_ticks;
    39                                     /* ticks since initialization */
     37rtems_unsigned32 Clock_isrs;                  /* ISRs until next tick */
     38volatile rtems_unsigned32 Clock_driver_ticks; /* ticks since initialization */
    4039rtems_isr_entry  Old_ticker;
    4140
    42 rtems_device_driver Clock_initialize(
     41rtems_device_driver Clock_initialize( 
    4342  rtems_device_major_number major,
    4443  rtems_device_minor_number minor,
     
    5150}
    5251
    53 void ReInstall_clock( clock_isr )
    54 rtems_isr_entry clock_isr;
     52void ReInstall_clock(rtems_isr_entry clock_isr)
    5553{
    5654  rtems_unsigned32 isrlevel;
    5755
    5856  rtems_interrupt_disable( isrlevel );
    59   (void) set_vector( clock_isr, (VECTOR_BASE >> 28) * 0x10 + 0x9, 1 );
     57  (void) set_vector( clock_isr, VBR0 * 0x10 + 0x9, 1 );
    6058  rtems_interrupt_enable( isrlevel );
    6159}
    6260
    63 void Install_clock( clock_isr )
    64 rtems_isr_entry clock_isr;
     61void Install_clock(rtems_isr_entry clock_isr )
    6562{
    6663
     
    6966
    7067  if ( BSP_Configuration.ticks_per_timeslice ) {
    71     Old_ticker = (rtems_isr_entry)
    72       set_vector( clock_isr, (VECTOR_BASE >> 28) * 0x10 + 0x9, 1 );
     68    Old_ticker =
     69      (rtems_isr_entry) set_vector( clock_isr, VBR0 * 0x10 + 0x9, 1 );
     70    lcsr->vector_base |= MASK_INT;   /* unmask VMEchip2 interrupts */
     71    lcsr->to_ctl = 0xE7;             /* prescaler to 1 MHz (see Appendix A1) */
     72    lcsr->timer_cmp_2 = MS_COUNT;
     73    lcsr->timer_cnt_2 = 0;           /* clear counter */
     74    lcsr->board_ctl |= 0x700;        /* increment, reset-on-compare, and */
     75                                     /*   clear-overflow-cnt */
    7376
    74     lcsr->vector_base = 0x67800000;              /* set vb, enable interrupts */
    75     lcsr->to_ctl = 0xE7;              /* prescaler to 1 MHz (see Appendix A1) */
    76     lcsr->timer_cmp_2 = MS_COUNT;
    77     lcsr->timer_cnt_2 = 0;                                   /* clear counter */
    78     lcsr->board_ctl |= 0x700;  /* increment, reset-on-compare, clear-ovfl-cnt */
    79 
    80     lcsr->intr_level[0] |= CLOCK_INT_LEVEL * 0x10;           /* set int level */
    81     lcsr->intr_ena |= 0x02000000;            /* enable tick timer 2 interrupt */
     77    lcsr->intr_level[0] |= CLOCK_INT_LEVEL * 0x10;      /* set int level */
     78    lcsr->intr_ena |= 0x02000000;       /* enable tick timer 2 interrupt */
    8279
    8380    atexit( Clock_exit );
    84   }
     81  } 
    8582
    8683}
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