Changeset c5ed148 in rtems


Ignore:
Timestamp:
09/24/11 12:56:51 (11 years ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
4.11, 5, master
Children:
e263c16
Parents:
86c847c1
Message:

2011-09-24 Sebastian Huber <sebastian.huber@…>

  • rtems/score/armv7m.h, armv7m-context-initialize.c, armv7m-context-restore.c, armv7m-context-switch.c, armv7m-exception-handler-get.c, armv7m-exception-handler-set.c, armv7m-exception-priority-get.c, armv7m-exception-priority-set.c, armv7m-initialize.c, armv7m-isr-dispatch.c, armv7m-isr-enter-leave.c, armv7m-isr-level-get.c, armv7m-isr-level-set.c, armv7m-isr-vector-install.c, armv7m-multitasking-start-stop.c: New files.
  • Makefile.am, preinstall.am: Reflect changes above.
  • rtems/score/arm.h: Define ARM_MULTILIB_ARCH_V4 and ARM_MULTILIB_ARCH_V7M.
  • rtems/score/cpu.h, cpu_asm.S, cpu.c, arm_exc_abort.S, arm_exc_handler_high.c, arm_exc_handler_low.S, arm_exc_interrupt.S: Define CPU_HAS_HARDWARE_INTERRUPT_STACK to FALSE. Use ARM_MULTILIB_ARCH_V4 and ARM_MULTILIB_ARCH_V7M.
Location:
cpukit/score/cpu/arm
Files:
15 added
11 edited

Legend:

Unmodified
Added
Removed

  • cpukit/score/cpu/arm/ChangeLog

    r86c847c1 rc5ed148  
     12011-09-24      Sebastian Huber <sebastian.huber@embedded-brains.de>
     2
     3        * rtems/score/armv7m.h, armv7m-context-initialize.c,
     4        armv7m-context-restore.c, armv7m-context-switch.c,
     5        armv7m-exception-handler-get.c, armv7m-exception-handler-set.c,
     6        armv7m-exception-priority-get.c, armv7m-exception-priority-set.c,
     7        armv7m-initialize.c, armv7m-isr-dispatch.c, armv7m-isr-enter-leave.c,
     8        armv7m-isr-level-get.c, armv7m-isr-level-set.c,
     9        armv7m-isr-vector-install.c, armv7m-multitasking-start-stop.c: New
     10        files.
     11        * Makefile.am, preinstall.am: Reflect changes above.
     12        * rtems/score/arm.h: Define ARM_MULTILIB_ARCH_V4 and
     13        ARM_MULTILIB_ARCH_V7M.
     14        * rtems/score/cpu.h, cpu_asm.S, cpu.c, arm_exc_abort.S,
     15        arm_exc_handler_high.c, arm_exc_handler_low.S, arm_exc_interrupt.S:
     16        Define CPU_HAS_HARDWARE_INTERRUPT_STACK to FALSE.  Use
     17        ARM_MULTILIB_ARCH_V4 and ARM_MULTILIB_ARCH_V7M.
     18
    1192011-09-16      Sebastian Huber <sebastian.huber@embedded-brains.de>
    220

  • cpukit/score/cpu/arm/Makefile.am

    r86c847c1 rc5ed148  
    1010include_rtems_score_HEADERS += rtems/score/cpu_asm.h
    1111include_rtems_score_HEADERS += rtems/score/arm.h
     12include_rtems_score_HEADERS += rtems/score/armv7m.h
    1213include_rtems_score_HEADERS += rtems/score/types.h
    1314
    1415noinst_LIBRARIES = libscorecpu.a
    1516libscorecpu_a_CPPFLAGS = $(AM_CPPFLAGS)
    16 libscorecpu_a_SOURCES = cpu.c \
    17         cpu_asm.S \
    18         arm_exc_abort.S \
    19         arm_exc_interrupt.S \
    20         arm_exc_handler_low.S \
    21         arm_exc_handler_high.c
     17libscorecpu_a_SOURCES =
     18libscorecpu_a_SOURCES += cpu.c
     19libscorecpu_a_SOURCES += cpu_asm.S
     20libscorecpu_a_SOURCES += arm_exc_abort.S
     21libscorecpu_a_SOURCES += arm_exc_interrupt.S
     22libscorecpu_a_SOURCES += arm_exc_handler_low.S
     23libscorecpu_a_SOURCES += arm_exc_handler_high.c
     24libscorecpu_a_SOURCES += armv7m-context-initialize.c
     25libscorecpu_a_SOURCES += armv7m-context-restore.c
     26libscorecpu_a_SOURCES += armv7m-context-switch.c
     27libscorecpu_a_SOURCES += armv7m-exception-handler-get.c
     28libscorecpu_a_SOURCES += armv7m-exception-handler-set.c
     29libscorecpu_a_SOURCES += armv7m-exception-priority-get.c
     30libscorecpu_a_SOURCES += armv7m-exception-priority-set.c
     31libscorecpu_a_SOURCES += armv7m-initialize.c
     32libscorecpu_a_SOURCES += armv7m-isr-dispatch.c
     33libscorecpu_a_SOURCES += armv7m-isr-enter-leave.c
     34libscorecpu_a_SOURCES += armv7m-isr-level-get.c
     35libscorecpu_a_SOURCES += armv7m-isr-level-set.c
     36libscorecpu_a_SOURCES += armv7m-isr-vector-install.c
     37libscorecpu_a_SOURCES += armv7m-multitasking-start-stop.c
    2238
    2339include $(srcdir)/preinstall.am

  • cpukit/score/cpu/arm/arm_exc_abort.S

    r86c847c1 rc5ed148  
    2626#include <rtems/asm.h>
    2727#include <rtems/system.h>
     28
     29#ifdef ARM_MULTILIB_ARCH_V4
    2830
    2931.extern rtems_fatal_error_occurred
    … …  
    134136        bx      r2
    135137#endif /* __thumb__ */
     138
     139#endif /* ARM_MULTILIB_ARCH_V4 */

  • cpukit/score/cpu/arm/arm_exc_handler_high.c

    r86c847c1 rc5ed148  
    3636#include <rtems/score/thread.h>
    3737#include <rtems/score/cpu.h>
     38
     39#ifdef ARM_MULTILIB_ARCH_V4
    3840
    3941static void _defaultExcHandler (CPU_Exception_frame *ctx)
    … …  
    120122      _CPU_ISR_Enable(level);
    121123}
     124
     125#endif /* ARM_MULTILIB_ARCH_V4 */

  • cpukit/score/cpu/arm/arm_exc_handler_low.S

    r86c847c1 rc5ed148  
    3333#include <rtems/asm.h>
    3434#include <rtems/score/cpu_asm.h>
     35
     36#ifdef ARM_MULTILIB_ARCH_V4
    3537
    3638        .text
    … …  
    163165#endif
    164166                                                /* _AFTER_ the aborted one */
     167
     168#endif /* ARM_MULTILIB_ARCH_V4 */

  • cpukit/score/cpu/arm/arm_exc_interrupt.S

    r86c847c1 rc5ed148  
    3232#include <rtems/asm.h>
    3333#include <rtems/score/percpu.h>
     34
     35#ifdef ARM_MULTILIB_ARCH_V4
    3436
    3537#define EXCHANGE_LR r4
    … …  
    176178        /* Return from interrupt */
    177179        subs    pc, lr, #4
     180
     181#endif /* ARM_MULTILIB_ARCH_V4 */

  • cpukit/score/cpu/arm/cpu.c

    r86c847c1 rc5ed148  
    1616 *  Copyright (c) 2007 Ray xu <rayx.cn@gmail.com>
    1717 *
    18  *  Copyright (c) 2009 embedded brains GmbH
     18 *  Copyright (c) 2009-2011 embedded brains GmbH
    1919 *
    2020 *  The license and distribution terms for this file may be
    … …  
    3737#include <rtems/score/cpu.h>
    3838
     39#ifdef ARM_MULTILIB_ARCH_V4
     40
    3941/*
    4042 * This variable can be used to change the running mode of the execution
    … …  
    4547void _CPU_Context_Initialize(
    4648  Context_Control *the_context,
    47   uint32_t *stack_base,
    48   uint32_t size,
     49  void *stack_area_begin,
     50  size_t stack_area_size,
    4951  uint32_t new_level,
    50   void *entry_point,
     52  void (*entry_point)( void ),
    5153  bool is_fp
    5254)
    5355{
    54   the_context->register_sp = (uint32_t) stack_base + size ;
     56  the_context->register_sp = (uint32_t) stack_area_begin + stack_area_size;
    5557  the_context->register_lr = (uint32_t) entry_point;
    5658  the_context->register_cpsr = new_level | arm_cpu_mode;
    … …  
    115117}
    116118
    117 void _CPU_Install_interrupt_stack( void )
    118 {
    119   /* This function is empty since the BSP must set up the interrupt stacks */
    120 }
    121 
    122119void _CPU_Initialize( void )
    123120{
    124121  /* Do nothing */
    125122}
     123
     124#endif /* ARM_MULTILIB_ARCH_V4 */

  • cpukit/score/cpu/arm/cpu_asm.S

    r86c847c1 rc5ed148  
    3434#include <rtems/asm.h>
    3535#include <rtems/score/cpu_asm.h>
     36
     37#ifdef ARM_MULTILIB_ARCH_V4
    3638
    3739        .text
    … …  
    7981        mov     r1, r0
    8082        b       _restore
     83
     84#endif /* ARM_MULTILIB_ARCH_V4 */

  • cpukit/score/cpu/arm/preinstall.am

    r86c847c1 rc5ed148  
    4040PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/arm.h
    4141
     42$(PROJECT_INCLUDE)/rtems/score/armv7m.h: rtems/score/armv7m.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
     43        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/armv7m.h
     44PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/armv7m.h
     45
    4246$(PROJECT_INCLUDE)/rtems/score/types.h: rtems/score/types.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
    4347        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/types.h

  • cpukit/score/cpu/arm/rtems/score/arm.h

    r86c847c1 rc5ed148  
    4545#if defined(__ARM_ARCH_4__)
    4646#  define CPU_MODEL_NAME  "ARMv4"
     47#  define ARM_MULTILIB_ARCH_V4
    4748
    4849#elif defined(__ARM_ARCH_4T__)
    4950#  define CPU_MODEL_NAME  "ARMv4T"
     51#  define ARM_MULTILIB_ARCH_V4
    5052
    5153#elif defined(__ARM_ARCH_5__)
    5254#  define CPU_MODEL_NAME  "ARMv5"
     55#  define ARM_MULTILIB_ARCH_V4
    5356
    5457#elif defined(__ARM_ARCH_5T__)
    5558#  define CPU_MODEL_NAME  "ARMv5T"
     59#  define ARM_MULTILIB_ARCH_V4
    5660
    5761#elif defined(__ARM_ARCH_5E__)
    5862#  define CPU_MODEL_NAME  "ARMv5E"
     63#  define ARM_MULTILIB_ARCH_V4
    5964
    6065#elif defined(__ARM_ARCH_5TE__)
    6166#  define CPU_MODEL_NAME  "ARMv5TE"
     67#  define ARM_MULTILIB_ARCH_V4
    6268
    6369#elif defined(__ARM_ARCH_5TEJ__)
    6470#  define CPU_MODEL_NAME  "ARMv5TEJ"
     71#  define ARM_MULTILIB_ARCH_V4
    6572
    6673#elif defined(__ARM_ARCH_6J__)
    … …  
    6976#elif defined(__ARM_ARCH_6M__)
    7077#  define CPU_MODEL_NAME  "ARMv6M"
     78#  define ARM_MULTILIB_ARCH_V7M
    7179
    7280#elif defined(__ARM_ARCH_7__)
    7381#  define CPU_MODEL_NAME  "ARMv7"
    7482
     83#elif defined(__ARM_ARCH_7A__)
     84#  define CPU_MODEL_NAME  "ARMv7A"
     85
     86#elif defined(__ARM_ARCH_7R__)
     87#  define CPU_MODEL_NAME  "ARMv7R"
     88
    7589#elif defined(__ARM_ARCH_7M__)
    7690#  define CPU_MODEL_NAME  "ARMv7M"
    77 
    78 #elif defined(__ARM_ARCH_7A__)
    79 #  define CPU_MODEL_NAME  "ARMv7A"
     91#  define ARM_MULTILIB_ARCH_V7M
    8092
    8193#else

  • cpukit/score/cpu/arm/rtems/score/cpu.h

    r86c847c1 rc5ed148  
    1313 *  processor.
    1414 *
    15  *  Copyright (c) 2009-2010 embedded brains GmbH.
     15 *  Copyright (c) 2009-2011 embedded brains GmbH.
    1616 *
    1717 *  Copyright (c) 2007 Ray Xu <Rayx.cn@gmail.com>
    … …  
    3636#include <rtems/score/types.h>
    3737#include <rtems/score/arm.h>
     38
     39#if defined(ARM_MULTILIB_ARCH_V4)
    3840
    3941/**
    … …  
    9496/** @} */
    9597
     98#endif /* defined(ARM_MULTILIB_ARCH_V4) */
     99
    96100/**
    97101 * @addtogroup ScoreCPU
    … …  
    121125#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
    122126
    123 #define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE
     127#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
    124128
    125129#define CPU_ALLOCATE_INTERRUPT_STACK FALSE
    … …  
    217221
    218222typedef struct {
     223#if defined(ARM_MULTILIB_ARCH_V4)
    219224  uint32_t register_cpsr;
    220225  uint32_t register_r4;
    … …  
    229234  uint32_t register_lr;
    230235  uint32_t register_pc;
     236#elif defined(ARM_MULTILIB_ARCH_V7M)
     237  uint32_t register_r4;
     238  uint32_t register_r5;
     239  uint32_t register_r6;
     240  uint32_t register_r7;
     241  uint32_t register_r8;
     242  uint32_t register_r9;
     243  uint32_t register_r10;
     244  uint32_t register_r11;
     245  void *register_lr;
     246  void *register_sp;
     247  uint32_t isr_nest_level;
     248#endif
    231249} Context_Control;
    232250
    … …  
    241259static inline uint32_t arm_interrupt_disable( void )
    242260{
     261#if defined(ARM_MULTILIB_ARCH_V4)
    243262  uint32_t arm_switch_reg;
    244263  uint32_t level;
    … …  
    254273
    255274  return level;
     275#elif defined(ARM_MULTILIB_ARCH_V7M)
     276  uint32_t level;
     277  uint32_t basepri = 0x80;
     278
     279  __asm__ volatile (
     280    "mrs %[level], basepri\n"
     281    "msr basepri_max, %[basepri]\n"
     282    : [level] "=&r" (level)
     283    : [basepri] "r" (basepri)
     284  );
     285
     286  return level;
     287#endif
    256288}
    257289
    258290static inline void arm_interrupt_enable( uint32_t level )
    259291{
     292#if defined(ARM_MULTILIB_ARCH_V4)
    260293  ARM_SWITCH_REGISTERS;
    261294
    … …  
    267300    : [level] "r" (level)
    268301  );
     302#elif defined(ARM_MULTILIB_ARCH_V7M)
     303  __asm__ volatile (
     304    "msr basepri, %[level]\n"
     305    :
     306    : [level] "r" (level)
     307  );
     308#endif
    269309}
    270310
    271311static inline void arm_interrupt_flash( uint32_t level )
    272312{
     313#if defined(ARM_MULTILIB_ARCH_V4)
    273314  uint32_t arm_switch_reg;
    274315
    … …  
    282323    : [level] "r" (level)
    283324  );
     325#elif defined(ARM_MULTILIB_ARCH_V7M)
     326  uint32_t basepri;
     327
     328  __asm__ volatile (
     329    "mrs %[basepri], basepri\n"
     330    "msr basepri, %[level]\n"
     331    "msr basepri, %[basepri]\n"
     332    : [basepri] "=&r" (basepri)
     333    : [level] "r" (level)
     334  );
     335#endif
    284336}
    285337
    … …  
    301353void _CPU_Context_Initialize(
    302354  Context_Control *the_context,
    303   uint32_t *stack_base,
    304   uint32_t size,
     355  void *stack_area_begin,
     356  size_t stack_area_size,
    305357  uint32_t new_level,
    306   void *entry_point,
     358  void (*entry_point)( void ),
    307359  bool is_fp
    308360);
    … …  
    344396);
    345397
    346 void _CPU_Install_interrupt_stack( void );
    347 
    348398void _CPU_Context_switch( Context_Control *run, Context_Control *heir );
    349399
    350400void _CPU_Context_restore( Context_Control *new_context )
    351        RTEMS_COMPILER_NO_RETURN_ATTRIBUTE;
     401  RTEMS_COMPILER_NO_RETURN_ATTRIBUTE;
     402
     403#if defined(ARM_MULTILIB_ARCH_V7M)
     404  void _ARMV7M_Start_multitasking( Context_Control *bsp, Context_Control *heir );
     405  void _ARMV7M_Stop_multitasking( Context_Control *bsp )
     406    RTEMS_COMPILER_NO_RETURN_ATTRIBUTE;
     407  #define _CPU_Start_multitasking _ARMV7M_Start_multitasking
     408  #define _CPU_Stop_multitasking _ARMV7M_Stop_multitasking
     409#endif
    352410
    353411void _CPU_Context_save_fp( Context_Control_fp **fp_context_ptr );
    … …  
    357415static inline uint32_t CPU_swap_u32( uint32_t value )
    358416{
    359 #if defined(__thumb__)
     417#if defined(__thumb2__)
     418  __asm__ volatile (
     419    "rev %0, %0"
     420    : "=r" (value)
     421    : "0" (value)
     422  );
     423  return value;
     424#elif defined(__thumb__)
    360425  uint32_t byte1, byte2, byte3, byte4, swapped;
    361426
    … …  
    381446static inline uint16_t CPU_swap_u16( uint16_t value )
    382447{
     448#if defined(__thumb2__)
     449  __asm__ volatile (
     450    "rev16 %0, %0"
     451    : "=r" (value)
     452    : "0" (value)
     453  );
     454  return value;
     455#else
    383456  return (uint16_t) (((value & 0xffU) << 8) | ((value >> 8) & 0xffU));
     457#endif
    384458}
    385459
    386460/** @} */
     461
     462#if defined(ARM_MULTILIB_ARCH_V4)
    387463
    388464/**
    … …  
    488564typedef CPU_Exception_frame CPU_Interrupt_frame;
    489565
     566#elif defined(ARM_MULTILIB_ARCH_V7M)
     567
     568typedef void CPU_Interrupt_frame;
     569
     570#endif /* defined(ARM_MULTILIB_ARCH_V7M) */
     571
    490572#ifdef __cplusplus
    491573}
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