Changeset c5ed148 in rtems
- Timestamp:
- Sep 24, 2011, 12:56:51 PM (9 years ago)
- Branches:
- 4.11, 5, master
- Children:
- e263c16
- Parents:
- 86c847c1
- Location:
- cpukit/score/cpu/arm
- Files:
-
- 15 added
- 11 edited
Legend:
- Unmodified
- Added
- Removed
-
cpukit/score/cpu/arm/ChangeLog
r86c847c1 rc5ed148 1 2011-09-24 Sebastian Huber <sebastian.huber@embedded-brains.de> 2 3 * rtems/score/armv7m.h, armv7m-context-initialize.c, 4 armv7m-context-restore.c, armv7m-context-switch.c, 5 armv7m-exception-handler-get.c, armv7m-exception-handler-set.c, 6 armv7m-exception-priority-get.c, armv7m-exception-priority-set.c, 7 armv7m-initialize.c, armv7m-isr-dispatch.c, armv7m-isr-enter-leave.c, 8 armv7m-isr-level-get.c, armv7m-isr-level-set.c, 9 armv7m-isr-vector-install.c, armv7m-multitasking-start-stop.c: New 10 files. 11 * Makefile.am, preinstall.am: Reflect changes above. 12 * rtems/score/arm.h: Define ARM_MULTILIB_ARCH_V4 and 13 ARM_MULTILIB_ARCH_V7M. 14 * rtems/score/cpu.h, cpu_asm.S, cpu.c, arm_exc_abort.S, 15 arm_exc_handler_high.c, arm_exc_handler_low.S, arm_exc_interrupt.S: 16 Define CPU_HAS_HARDWARE_INTERRUPT_STACK to FALSE. Use 17 ARM_MULTILIB_ARCH_V4 and ARM_MULTILIB_ARCH_V7M. 18 1 19 2011-09-16 Sebastian Huber <sebastian.huber@embedded-brains.de> 2 20 -
cpukit/score/cpu/arm/Makefile.am
r86c847c1 rc5ed148 10 10 include_rtems_score_HEADERS += rtems/score/cpu_asm.h 11 11 include_rtems_score_HEADERS += rtems/score/arm.h 12 include_rtems_score_HEADERS += rtems/score/armv7m.h 12 13 include_rtems_score_HEADERS += rtems/score/types.h 13 14 14 15 noinst_LIBRARIES = libscorecpu.a 15 16 libscorecpu_a_CPPFLAGS = $(AM_CPPFLAGS) 16 libscorecpu_a_SOURCES = cpu.c \ 17 cpu_asm.S \ 18 arm_exc_abort.S \ 19 arm_exc_interrupt.S \ 20 arm_exc_handler_low.S \ 21 arm_exc_handler_high.c 17 libscorecpu_a_SOURCES = 18 libscorecpu_a_SOURCES += cpu.c 19 libscorecpu_a_SOURCES += cpu_asm.S 20 libscorecpu_a_SOURCES += arm_exc_abort.S 21 libscorecpu_a_SOURCES += arm_exc_interrupt.S 22 libscorecpu_a_SOURCES += arm_exc_handler_low.S 23 libscorecpu_a_SOURCES += arm_exc_handler_high.c 24 libscorecpu_a_SOURCES += armv7m-context-initialize.c 25 libscorecpu_a_SOURCES += armv7m-context-restore.c 26 libscorecpu_a_SOURCES += armv7m-context-switch.c 27 libscorecpu_a_SOURCES += armv7m-exception-handler-get.c 28 libscorecpu_a_SOURCES += armv7m-exception-handler-set.c 29 libscorecpu_a_SOURCES += armv7m-exception-priority-get.c 30 libscorecpu_a_SOURCES += armv7m-exception-priority-set.c 31 libscorecpu_a_SOURCES += armv7m-initialize.c 32 libscorecpu_a_SOURCES += armv7m-isr-dispatch.c 33 libscorecpu_a_SOURCES += armv7m-isr-enter-leave.c 34 libscorecpu_a_SOURCES += armv7m-isr-level-get.c 35 libscorecpu_a_SOURCES += armv7m-isr-level-set.c 36 libscorecpu_a_SOURCES += armv7m-isr-vector-install.c 37 libscorecpu_a_SOURCES += armv7m-multitasking-start-stop.c 22 38 23 39 include $(srcdir)/preinstall.am -
cpukit/score/cpu/arm/arm_exc_abort.S
r86c847c1 rc5ed148 26 26 #include <rtems/asm.h> 27 27 #include <rtems/system.h> 28 29 #ifdef ARM_MULTILIB_ARCH_V4 28 30 29 31 .extern rtems_fatal_error_occurred … … 134 136 bx r2 135 137 #endif /* __thumb__ */ 138 139 #endif /* ARM_MULTILIB_ARCH_V4 */ -
cpukit/score/cpu/arm/arm_exc_handler_high.c
r86c847c1 rc5ed148 36 36 #include <rtems/score/thread.h> 37 37 #include <rtems/score/cpu.h> 38 39 #ifdef ARM_MULTILIB_ARCH_V4 38 40 39 41 static void _defaultExcHandler (CPU_Exception_frame *ctx) … … 120 122 _CPU_ISR_Enable(level); 121 123 } 124 125 #endif /* ARM_MULTILIB_ARCH_V4 */ -
cpukit/score/cpu/arm/arm_exc_handler_low.S
r86c847c1 rc5ed148 33 33 #include <rtems/asm.h> 34 34 #include <rtems/score/cpu_asm.h> 35 36 #ifdef ARM_MULTILIB_ARCH_V4 35 37 36 38 .text … … 163 165 #endif 164 166 /* _AFTER_ the aborted one */ 167 168 #endif /* ARM_MULTILIB_ARCH_V4 */ -
cpukit/score/cpu/arm/arm_exc_interrupt.S
r86c847c1 rc5ed148 32 32 #include <rtems/asm.h> 33 33 #include <rtems/score/percpu.h> 34 35 #ifdef ARM_MULTILIB_ARCH_V4 34 36 35 37 #define EXCHANGE_LR r4 … … 176 178 /* Return from interrupt */ 177 179 subs pc, lr, #4 180 181 #endif /* ARM_MULTILIB_ARCH_V4 */ -
cpukit/score/cpu/arm/cpu.c
r86c847c1 rc5ed148 16 16 * Copyright (c) 2007 Ray xu <rayx.cn@gmail.com> 17 17 * 18 * Copyright (c) 2009 embedded brains GmbH18 * Copyright (c) 2009-2011 embedded brains GmbH 19 19 * 20 20 * The license and distribution terms for this file may be … … 37 37 #include <rtems/score/cpu.h> 38 38 39 #ifdef ARM_MULTILIB_ARCH_V4 40 39 41 /* 40 42 * This variable can be used to change the running mode of the execution … … 45 47 void _CPU_Context_Initialize( 46 48 Context_Control *the_context, 47 uint32_t *stack_base,48 uint32_tsize,49 void *stack_area_begin, 50 size_t stack_area_size, 49 51 uint32_t new_level, 50 void *entry_point,52 void (*entry_point)( void ), 51 53 bool is_fp 52 54 ) 53 55 { 54 the_context->register_sp = (uint32_t) stack_ base + size;56 the_context->register_sp = (uint32_t) stack_area_begin + stack_area_size; 55 57 the_context->register_lr = (uint32_t) entry_point; 56 58 the_context->register_cpsr = new_level | arm_cpu_mode; … … 115 117 } 116 118 117 void _CPU_Install_interrupt_stack( void )118 {119 /* This function is empty since the BSP must set up the interrupt stacks */120 }121 122 119 void _CPU_Initialize( void ) 123 120 { 124 121 /* Do nothing */ 125 122 } 123 124 #endif /* ARM_MULTILIB_ARCH_V4 */ -
cpukit/score/cpu/arm/cpu_asm.S
r86c847c1 rc5ed148 34 34 #include <rtems/asm.h> 35 35 #include <rtems/score/cpu_asm.h> 36 37 #ifdef ARM_MULTILIB_ARCH_V4 36 38 37 39 .text … … 79 81 mov r1, r0 80 82 b _restore 83 84 #endif /* ARM_MULTILIB_ARCH_V4 */ -
cpukit/score/cpu/arm/preinstall.am
r86c847c1 rc5ed148 40 40 PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/arm.h 41 41 42 $(PROJECT_INCLUDE)/rtems/score/armv7m.h: rtems/score/armv7m.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) 43 $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/armv7m.h 44 PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/armv7m.h 45 42 46 $(PROJECT_INCLUDE)/rtems/score/types.h: rtems/score/types.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) 43 47 $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/types.h -
cpukit/score/cpu/arm/rtems/score/arm.h
r86c847c1 rc5ed148 45 45 #if defined(__ARM_ARCH_4__) 46 46 # define CPU_MODEL_NAME "ARMv4" 47 # define ARM_MULTILIB_ARCH_V4 47 48 48 49 #elif defined(__ARM_ARCH_4T__) 49 50 # define CPU_MODEL_NAME "ARMv4T" 51 # define ARM_MULTILIB_ARCH_V4 50 52 51 53 #elif defined(__ARM_ARCH_5__) 52 54 # define CPU_MODEL_NAME "ARMv5" 55 # define ARM_MULTILIB_ARCH_V4 53 56 54 57 #elif defined(__ARM_ARCH_5T__) 55 58 # define CPU_MODEL_NAME "ARMv5T" 59 # define ARM_MULTILIB_ARCH_V4 56 60 57 61 #elif defined(__ARM_ARCH_5E__) 58 62 # define CPU_MODEL_NAME "ARMv5E" 63 # define ARM_MULTILIB_ARCH_V4 59 64 60 65 #elif defined(__ARM_ARCH_5TE__) 61 66 # define CPU_MODEL_NAME "ARMv5TE" 67 # define ARM_MULTILIB_ARCH_V4 62 68 63 69 #elif defined(__ARM_ARCH_5TEJ__) 64 70 # define CPU_MODEL_NAME "ARMv5TEJ" 71 # define ARM_MULTILIB_ARCH_V4 65 72 66 73 #elif defined(__ARM_ARCH_6J__) … … 69 76 #elif defined(__ARM_ARCH_6M__) 70 77 # define CPU_MODEL_NAME "ARMv6M" 78 # define ARM_MULTILIB_ARCH_V7M 71 79 72 80 #elif defined(__ARM_ARCH_7__) 73 81 # define CPU_MODEL_NAME "ARMv7" 74 82 83 #elif defined(__ARM_ARCH_7A__) 84 # define CPU_MODEL_NAME "ARMv7A" 85 86 #elif defined(__ARM_ARCH_7R__) 87 # define CPU_MODEL_NAME "ARMv7R" 88 75 89 #elif defined(__ARM_ARCH_7M__) 76 90 # define CPU_MODEL_NAME "ARMv7M" 77 78 #elif defined(__ARM_ARCH_7A__) 79 # define CPU_MODEL_NAME "ARMv7A" 91 # define ARM_MULTILIB_ARCH_V7M 80 92 81 93 #else -
cpukit/score/cpu/arm/rtems/score/cpu.h
r86c847c1 rc5ed148 13 13 * processor. 14 14 * 15 * Copyright (c) 2009-201 0embedded brains GmbH.15 * Copyright (c) 2009-2011 embedded brains GmbH. 16 16 * 17 17 * Copyright (c) 2007 Ray Xu <Rayx.cn@gmail.com> … … 36 36 #include <rtems/score/types.h> 37 37 #include <rtems/score/arm.h> 38 39 #if defined(ARM_MULTILIB_ARCH_V4) 38 40 39 41 /** … … 94 96 /** @} */ 95 97 98 #endif /* defined(ARM_MULTILIB_ARCH_V4) */ 99 96 100 /** 97 101 * @addtogroup ScoreCPU … … 121 125 #define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE 122 126 123 #define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE127 #define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE 124 128 125 129 #define CPU_ALLOCATE_INTERRUPT_STACK FALSE … … 217 221 218 222 typedef struct { 223 #if defined(ARM_MULTILIB_ARCH_V4) 219 224 uint32_t register_cpsr; 220 225 uint32_t register_r4; … … 229 234 uint32_t register_lr; 230 235 uint32_t register_pc; 236 #elif defined(ARM_MULTILIB_ARCH_V7M) 237 uint32_t register_r4; 238 uint32_t register_r5; 239 uint32_t register_r6; 240 uint32_t register_r7; 241 uint32_t register_r8; 242 uint32_t register_r9; 243 uint32_t register_r10; 244 uint32_t register_r11; 245 void *register_lr; 246 void *register_sp; 247 uint32_t isr_nest_level; 248 #endif 231 249 } Context_Control; 232 250 … … 241 259 static inline uint32_t arm_interrupt_disable( void ) 242 260 { 261 #if defined(ARM_MULTILIB_ARCH_V4) 243 262 uint32_t arm_switch_reg; 244 263 uint32_t level; … … 254 273 255 274 return level; 275 #elif defined(ARM_MULTILIB_ARCH_V7M) 276 uint32_t level; 277 uint32_t basepri = 0x80; 278 279 __asm__ volatile ( 280 "mrs %[level], basepri\n" 281 "msr basepri_max, %[basepri]\n" 282 : [level] "=&r" (level) 283 : [basepri] "r" (basepri) 284 ); 285 286 return level; 287 #endif 256 288 } 257 289 258 290 static inline void arm_interrupt_enable( uint32_t level ) 259 291 { 292 #if defined(ARM_MULTILIB_ARCH_V4) 260 293 ARM_SWITCH_REGISTERS; 261 294 … … 267 300 : [level] "r" (level) 268 301 ); 302 #elif defined(ARM_MULTILIB_ARCH_V7M) 303 __asm__ volatile ( 304 "msr basepri, %[level]\n" 305 : 306 : [level] "r" (level) 307 ); 308 #endif 269 309 } 270 310 271 311 static inline void arm_interrupt_flash( uint32_t level ) 272 312 { 313 #if defined(ARM_MULTILIB_ARCH_V4) 273 314 uint32_t arm_switch_reg; 274 315 … … 282 323 : [level] "r" (level) 283 324 ); 325 #elif defined(ARM_MULTILIB_ARCH_V7M) 326 uint32_t basepri; 327 328 __asm__ volatile ( 329 "mrs %[basepri], basepri\n" 330 "msr basepri, %[level]\n" 331 "msr basepri, %[basepri]\n" 332 : [basepri] "=&r" (basepri) 333 : [level] "r" (level) 334 ); 335 #endif 284 336 } 285 337 … … 301 353 void _CPU_Context_Initialize( 302 354 Context_Control *the_context, 303 uint32_t *stack_base,304 uint32_tsize,355 void *stack_area_begin, 356 size_t stack_area_size, 305 357 uint32_t new_level, 306 void *entry_point,358 void (*entry_point)( void ), 307 359 bool is_fp 308 360 ); … … 344 396 ); 345 397 346 void _CPU_Install_interrupt_stack( void );347 348 398 void _CPU_Context_switch( Context_Control *run, Context_Control *heir ); 349 399 350 400 void _CPU_Context_restore( Context_Control *new_context ) 351 RTEMS_COMPILER_NO_RETURN_ATTRIBUTE; 401 RTEMS_COMPILER_NO_RETURN_ATTRIBUTE; 402 403 #if defined(ARM_MULTILIB_ARCH_V7M) 404 void _ARMV7M_Start_multitasking( Context_Control *bsp, Context_Control *heir ); 405 void _ARMV7M_Stop_multitasking( Context_Control *bsp ) 406 RTEMS_COMPILER_NO_RETURN_ATTRIBUTE; 407 #define _CPU_Start_multitasking _ARMV7M_Start_multitasking 408 #define _CPU_Stop_multitasking _ARMV7M_Stop_multitasking 409 #endif 352 410 353 411 void _CPU_Context_save_fp( Context_Control_fp **fp_context_ptr ); … … 357 415 static inline uint32_t CPU_swap_u32( uint32_t value ) 358 416 { 359 #if defined(__thumb__) 417 #if defined(__thumb2__) 418 __asm__ volatile ( 419 "rev %0, %0" 420 : "=r" (value) 421 : "0" (value) 422 ); 423 return value; 424 #elif defined(__thumb__) 360 425 uint32_t byte1, byte2, byte3, byte4, swapped; 361 426 … … 381 446 static inline uint16_t CPU_swap_u16( uint16_t value ) 382 447 { 448 #if defined(__thumb2__) 449 __asm__ volatile ( 450 "rev16 %0, %0" 451 : "=r" (value) 452 : "0" (value) 453 ); 454 return value; 455 #else 383 456 return (uint16_t) (((value & 0xffU) << 8) | ((value >> 8) & 0xffU)); 457 #endif 384 458 } 385 459 386 460 /** @} */ 461 462 #if defined(ARM_MULTILIB_ARCH_V4) 387 463 388 464 /** … … 488 564 typedef CPU_Exception_frame CPU_Interrupt_frame; 489 565 566 #elif defined(ARM_MULTILIB_ARCH_V7M) 567 568 typedef void CPU_Interrupt_frame; 569 570 #endif /* defined(ARM_MULTILIB_ARCH_V7M) */ 571 490 572 #ifdef __cplusplus 491 573 }
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