Changeset c468f18b in rtems


Ignore:
Timestamp:
Dec 15, 2009, 3:20:47 PM (11 years ago)
Author:
Thomas Doerfler <Thomas.Doerfler@…>
Branches:
4.10, 4.11, 5, master
Children:
85893bc
Parents:
9db18dd
Message:

add support for LPC32xx

Location:
c/src/lib/libbsp/arm
Files:
24 added
26 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/arm/ChangeLog

    r9db18dd rc468f18b  
     12009-12-15      Sebastian Huber <sebastian.huber@embedded-brains.de>
     2
     3        * shared/include/linker-symbols.h: C++ compatibility.
     4        * shared/lpc/include/lpc-timer.h, shared/lpc/clock/lpc-clock-config.c:
     5        New files.
     6
    172009-12-07      Ralf Corsépius <ralf.corsepiu@rtems.org>
    28
  • c/src/lib/libbsp/arm/acinclude.m4

    r9db18dd rc468f18b  
    1919  lpc24xx )
    2020    AC_CONFIG_SUBDIRS([lpc24xx]);;
     21  lpc32xx )
     22    AC_CONFIG_SUBDIRS([lpc32xx]);;
    2123  nds )
    2224    AC_CONFIG_SUBDIRS([nds]);;
  • c/src/lib/libbsp/arm/lpc24xx/ChangeLog

    r9db18dd rc468f18b  
     12009-12-15      Sebastian Huber <sebastian.huber@embedded-brains.de>
     2
     3        * clock/clock-config.c: Removed file.
     4        * include/lpc-clock-config.h, make/custom/lpc2362.cfg,
     5        startup/linkcmds.lpc2362: New files.
     6        * Makefile.am, configure.ac, preinstall.am, console/console-config.c,
     7        i2c/i2c.c, include/bsp.h, include/io.h, include/irq.h,
     8        include/lpc24xx.h, irq/irq.c, make/custom/lpc24xx.inc, misc/dma.c,
     9        misc/io.c, misc/timer.c, network/network.c, rtc/rtc-config.c,
     10        startup/bspreset.c, startup/bspstart.c, startup/bspstarthooks.c,
     11        startup/linkcmds.lpc24xx_ea, startup/linkcmds.lpc24xx_ncs_ram,
     12        startup/linkcmds.lpc24xx_ncs_rom_ext,
     13        startup/linkcmds.lpc24xx_ncs_rom_int: Changes throughout.
     14
    1152009-11-03      Ralf Corsépius <ralf.corsepius@rtems.org>
    216
  • c/src/lib/libbsp/arm/lpc24xx/Makefile.am

    r9db18dd rc468f18b  
    3535include_bsp_HEADERS += ../shared/include/linker-symbols.h
    3636include_bsp_HEADERS += ../shared/include/start.h
     37include_bsp_HEADERS += ../shared/lpc/include/lpc-timer.h
    3738include_bsp_HEADERS += include/irq-config.h
    3839include_bsp_HEADERS += include/irq.h
     
    4344include_bsp_HEADERS += include/i2c.h
    4445include_bsp_HEADERS += include/io.h
     46include_bsp_HEADERS += include/lpc-clock-config.h
    4547
    4648include_HEADERS += ../../shared/include/tm27.h
     
    6264EXTRA_DIST += startup/linkcmds.lpc24xx_ncs_rom_ext
    6365EXTRA_DIST += startup/linkcmds.lpc24xx_ncs_ram
     66EXTRA_DIST += startup/linkcmds.lpc2362
    6467
    6568###############################################################################
     
    101104
    102105# Clock
    103 libbsp_a_SOURCES += clock/clock-config.c \
     106libbsp_a_SOURCES += ../shared/lpc/clock/lpc-clock-config.c \
    104107        ../../../shared/clockdrv_shell.h
    105108
  • c/src/lib/libbsp/arm/lpc24xx/configure.ac

    r9db18dd rc468f18b  
    4646RTEMS_BSPOPTS_HELP([LPC24XX_EMC_TEST],[enable tests for EMC])
    4747
     48RTEMS_BSPOPTS_SET([LPC24XX_SPECIAL_TASK_STACKS_SUPPORT],[lpc2362],[])
     49RTEMS_BSPOPTS_SET([LPC24XX_SPECIAL_TASK_STACKS_SUPPORT],[*],[1])
     50RTEMS_BSPOPTS_HELP([LPC24XX_SPECIAL_TASK_STACKS_SUPPORT],[enable special task stack support for task stacks in internal RAM])
     51
    4852RTEMS_BSPOPTS_SET([LPC24XX_CONFIG_CONSOLE],[*],[0])
    4953RTEMS_BSPOPTS_HELP([LPC24XX_CONFIG_CONSOLE],[configuration for console (UART 0)])
  • c/src/lib/libbsp/arm/lpc24xx/console/console-config.c

    r9db18dd rc468f18b  
    2626#include <bsp/irq.h>
    2727
    28 static uint8_t lpc24xx_uart_register( uint32_t addr, uint8_t i)
     28static uint8_t lpc24xx_uart_register(uint32_t addr, uint8_t i)
    2929{
    3030  volatile uint32_t *reg = (volatile uint32_t *) addr;
     
    3333}
    3434
    35 static void lpc24xx_uart_set_register( uint32_t addr, uint8_t i, uint8_t val)
     35static void lpc24xx_uart_set_register(uint32_t addr, uint8_t i, uint8_t val)
    3636{
    3737  volatile uint32_t *reg = (volatile uint32_t *) addr;
     
    130130
    131131#define LPC24XX_UART_NUMBER \
    132   (sizeof( Console_Port_Tbl) / sizeof( Console_Port_Tbl [0]))
     132  (sizeof(Console_Port_Tbl) / sizeof(Console_Port_Tbl [0]))
    133133
    134134unsigned long Console_Port_Count = LPC24XX_UART_NUMBER;
  • c/src/lib/libbsp/arm/lpc24xx/i2c/i2c.c

    r9db18dd rc468f18b  
    4545} lpc24xx_i2c_bus_entry;
    4646
    47 static void lpc24xx_i2c_handler( void *arg)
     47static void lpc24xx_i2c_handler(void *arg)
    4848{
    4949  lpc24xx_i2c_bus_entry *e = arg;
     
    9898  /* Notify task if necessary */
    9999  if (notify) {
    100     bsp_interrupt_vector_disable( e->vector);
    101 
    102     rtems_semaphore_release( e->state_update);
    103   }
    104 }
    105 
    106 static rtems_status_code lpc24xx_i2c_wait( lpc24xx_i2c_bus_entry *e)
    107 {
    108   bsp_interrupt_vector_enable( e->vector);
    109 
    110   return rtems_semaphore_obtain( e->state_update, RTEMS_WAIT, RTEMS_NO_TIMEOUT);
    111 }
    112 
    113 static rtems_status_code lpc24xx_i2c_init( rtems_libi2c_bus_t *bus)
     100    bsp_interrupt_vector_disable(e->vector);
     101
     102    rtems_semaphore_release(e->state_update);
     103  }
     104}
     105
     106static rtems_status_code lpc24xx_i2c_wait(lpc24xx_i2c_bus_entry *e)
     107{
     108  bsp_interrupt_vector_enable(e->vector);
     109
     110  return rtems_semaphore_obtain(e->state_update, RTEMS_WAIT, RTEMS_NO_TIMEOUT);
     111}
     112
     113static rtems_status_code lpc24xx_i2c_init(rtems_libi2c_bus_t *bus)
    114114{
    115115  rtems_status_code sc = RTEMS_SUCCESSFUL;
     
    120120  /* Create semaphore */
    121121  sc = rtems_semaphore_create (
    122     rtems_build_name ( 'I', '2', 'C', '0' + e->index),
     122    rtems_build_name ('I', '2', 'C', '0' + e->index),
    123123    0,
    124124    RTEMS_SIMPLE_BINARY_SEMAPHORE,
     
    126126    &e->state_update
    127127  );
    128   RTEMS_CHECK_SC( sc, "create status update semaphore");
     128  RTEMS_CHECK_SC(sc, "create status update semaphore");
    129129
    130130  /* Enable module power */
    131   sc = lpc24xx_module_enable( LPC24XX_MODULE_I2C, e->index, LPC24XX_MODULE_CCLK_8);
    132   RTEMS_CHECK_SC( sc, "enable module");
     131  sc = lpc24xx_module_enable(LPC24XX_MODULE_I2C_0 + e->index, LPC24XX_MODULE_CCLK_8);
     132  RTEMS_CHECK_SC(sc, "enable module");
    133133
    134134  /* IO configuration */
    135   sc = lpc24xx_io_config( LPC24XX_MODULE_I2C, e->index, e->config);
    136   RTEMS_CHECK_SC( sc, "IO configuration");
     135  sc = lpc24xx_io_config(LPC24XX_MODULE_I2C_0 + e->index, e->config);
     136  RTEMS_CHECK_SC(sc, "IO configuration");
    137137
    138138  /* Clock high and low duty cycles */
     
    151151    e
    152152  );
    153   RTEMS_CHECK_SC( sc, "install interrupt handler");
    154   bsp_interrupt_vector_disable( e->vector);
     153  RTEMS_CHECK_SC(sc, "install interrupt handler");
     154  bsp_interrupt_vector_disable(e->vector);
    155155
    156156  /* Enable module in master mode */
     
    163163}
    164164
    165 static rtems_status_code lpc24xx_i2c_send_start( rtems_libi2c_bus_t *bus)
     165static rtems_status_code lpc24xx_i2c_send_start(rtems_libi2c_bus_t *bus)
    166166{
    167167  rtems_status_code sc = RTEMS_SUCCESSFUL;
     
    174174
    175175  /* Wait */
    176   sc = lpc24xx_i2c_wait( e);
    177   RTEMS_CHECK_SC( sc, "wait for state update");
     176  sc = lpc24xx_i2c_wait(e);
     177  RTEMS_CHECK_SC(sc, "wait for state update");
    178178
    179179  return RTEMS_SUCCESSFUL;
    180180}
    181181
    182 static rtems_status_code lpc24xx_i2c_send_stop( rtems_libi2c_bus_t *bus)
     182static rtems_status_code lpc24xx_i2c_send_stop(rtems_libi2c_bus_t *bus)
    183183{
    184184  lpc24xx_i2c_bus_entry *e = (lpc24xx_i2c_bus_entry *) bus;
     
    214214
    215215  /* Wait */
    216   sc = lpc24xx_i2c_wait( e);
    217   RTEMS_CHECK_SC_RV( sc, "wait for state update");
     216  sc = lpc24xx_i2c_wait(e);
     217  RTEMS_CHECK_SC_RV(sc, "wait for state update");
    218218
    219219  /* Check state */
     
    226226}
    227227
    228 static int lpc24xx_i2c_read( rtems_libi2c_bus_t *bus, unsigned char *in, int n)
     228static int lpc24xx_i2c_read(rtems_libi2c_bus_t *bus, unsigned char *in, int n)
    229229{
    230230  rtems_status_code sc = RTEMS_SUCCESSFUL;
     
    254254
    255255  /* Wait */
    256   sc = lpc24xx_i2c_wait( e);
    257   RTEMS_CHECK_SC_RV( sc, "wait for state update");
     256  sc = lpc24xx_i2c_wait(e);
     257  RTEMS_CHECK_SC_RV(sc, "wait for state update");
    258258
    259259  /* Check state */
     
    291291
    292292  /* Wait */
    293   sc = lpc24xx_i2c_wait( e);
    294   RTEMS_CHECK_SC_RV( sc, "wait for state update");
     293  sc = lpc24xx_i2c_wait(e);
     294  RTEMS_CHECK_SC_RV(sc, "wait for state update");
    295295
    296296  /* Check state */
     
    311311}
    312312
    313 static int lpc24xx_i2c_ioctl( rtems_libi2c_bus_t *bus, int cmd, void *arg)
     313static int lpc24xx_i2c_ioctl(rtems_libi2c_bus_t *bus, int cmd, void *arg)
    314314{
    315315  int rv = -1;
     
    318318  switch (cmd) {
    319319    case RTEMS_LIBI2C_IOCTL_SET_TFRMODE:
    320       rv = lpc24xx_i2c_set_transfer_mode( bus, tm);
     320      rv = lpc24xx_i2c_set_transfer_mode(bus, tm);
    321321      break;
    322322    default:
     
    342342    .bus = {
    343343      .ops = &lpc24xx_i2c_ops,
    344       .size = sizeof( lpc24xx_i2c_bus_entry)
     344      .size = sizeof(lpc24xx_i2c_bus_entry)
    345345    },
    346346    .regs = (volatile lpc24xx_i2c *) I2C0_BASE_ADDR,
     
    358358    .bus = {
    359359      .ops = &lpc24xx_i2c_ops,
    360       .size = sizeof( lpc24xx_i2c_bus_entry)
     360      .size = sizeof(lpc24xx_i2c_bus_entry)
    361361    },
    362362    .regs = (volatile lpc24xx_i2c *) I2C1_BASE_ADDR,
     
    374374    .bus = {
    375375      .ops = &lpc24xx_i2c_ops,
    376       .size = sizeof( lpc24xx_i2c_bus_entry)
     376      .size = sizeof(lpc24xx_i2c_bus_entry)
    377377    },
    378378    .regs = (volatile lpc24xx_i2c *) I2C2_BASE_ADDR,
  • c/src/lib/libbsp/arm/lpc24xx/include/bsp.h

    r9db18dd rc468f18b  
    8181 * #define CONFIGURE_INIT
    8282 *
    83  * #define CONFIGURE_IDLE_TASK_BODY lpc24xx_idle
     83 * #define CONFIGURE_IDLE_TASK_BODY bsp_idle_thread
    8484 *
    8585 * #include <confdefs.h>
    8686 * @endcode
    8787 */
    88 void *lpc24xx_idle(uintptr_t ignored);
     88void *bsp_idle_thread(uintptr_t ignored);
    8989
    9090/** @} */
  • c/src/lib/libbsp/arm/lpc24xx/include/io.h

    r9db18dd rc468f18b  
    4545#define LPC24XX_IO_INDEX_MAX (LPC24XX_IO_PORT_COUNT * 32U)
    4646
    47 #define LPC24XX_IO_INDEX_BY_PORT( port, bit) (((port) << 5U) + (bit))
     47#define LPC24XX_IO_INDEX_BY_PORT(port, bit) (((port) << 5U) + (bit))
    4848
    49 #define LPC24XX_IO_PORT( index) (index >> 5U)
     49#define LPC24XX_IO_PORT(index) (index >> 5U)
    5050
    51 #define LPC24XX_IO_PORT_BIT( index) (index & 0x1fU)
     51#define LPC24XX_IO_PORT_BIT(index) (index & 0x1fU)
    5252
    5353typedef enum {
    54   LPC24XX_MODULE_ACF,
     54  LPC24XX_MODULE_ACF = 0,
    5555  LPC24XX_MODULE_ADC,
    5656  LPC24XX_MODULE_BAT_RAM,
    57   LPC24XX_MODULE_CAN,
     57  LPC24XX_MODULE_CAN_0,
     58  LPC24XX_MODULE_CAN_1,
    5859  LPC24XX_MODULE_DAC,
    5960  LPC24XX_MODULE_EMC,
     
    6162  LPC24XX_MODULE_GPDMA,
    6263  LPC24XX_MODULE_GPIO,
    63   LPC24XX_MODULE_I2C,
     64  LPC24XX_MODULE_I2C_0,
     65  LPC24XX_MODULE_I2C_1,
     66  LPC24XX_MODULE_I2C_2,
    6467  LPC24XX_MODULE_I2S,
    6568  LPC24XX_MODULE_LCD,
    6669  LPC24XX_MODULE_MCI,
    6770  LPC24XX_MODULE_PCB,
    68   LPC24XX_MODULE_PWM,
     71  LPC24XX_MODULE_PWM_0,
     72  LPC24XX_MODULE_PWM_1,
    6973  LPC24XX_MODULE_RTC,
    7074  LPC24XX_MODULE_SPI,
    71   LPC24XX_MODULE_SSP,
     75  LPC24XX_MODULE_SSP_0,
     76  LPC24XX_MODULE_SSP_1,
    7277  LPC24XX_MODULE_SYSCON,
    73   LPC24XX_MODULE_TIMER,
    74   LPC24XX_MODULE_UART,
     78  LPC24XX_MODULE_TIMER_0,
     79  LPC24XX_MODULE_TIMER_1,
     80  LPC24XX_MODULE_TIMER_2,
     81  LPC24XX_MODULE_TIMER_3,
     82  LPC24XX_MODULE_UART_0,
     83  LPC24XX_MODULE_UART_1,
     84  LPC24XX_MODULE_UART_2,
     85  LPC24XX_MODULE_UART_3,
    7586  LPC24XX_MODULE_USB,
    76   LPC24XX_MODULE_WDT,
    77   LPC24XX_MODULE_COUNT
     87  LPC24XX_MODULE_WDT
    7888} lpc24xx_module;
     89
     90#define LPC24XX_MODULE_FIRST LPC24XX_MODULE_ACF
     91
     92#define LPC24XX_MODULE_COUNT (LPC24XX_MODULE_WDT + 1)
    7993
    8094typedef enum {
     
    103117rtems_status_code lpc24xx_module_enable(
    104118  lpc24xx_module module,
    105   unsigned index,
    106119  lpc24xx_module_clock clock
    107120);
    108121
    109122rtems_status_code lpc24xx_module_disable(
    110   lpc24xx_module module,
    111   unsigned index
     123  lpc24xx_module module
    112124);
    113125
    114126rtems_status_code lpc24xx_io_config(
    115127  lpc24xx_module module,
    116   unsigned index,
    117128  unsigned config
    118129);
     
    120131rtems_status_code lpc24xx_io_release(
    121132  lpc24xx_module module,
    122   unsigned index,
    123133  unsigned config
    124134);
     
    129139);
    130140
    131 static inline void lpc24xx_gpio_set( unsigned index)
     141static inline void lpc24xx_gpio_set(unsigned index)
    132142{
    133143  if (index <= LPC24XX_IO_INDEX_MAX) {
    134     unsigned port = LPC24XX_IO_PORT( index);
    135     unsigned bit = LPC24XX_IO_PORT_BIT( index);
     144    unsigned port = LPC24XX_IO_PORT(index);
     145    unsigned bit = LPC24XX_IO_PORT_BIT(index);
    136146
    137147    LPC24XX_FIO [port].set = 1U << bit;
     
    139149}
    140150
    141 static inline void lpc24xx_gpio_clear( unsigned index)
     151static inline void lpc24xx_gpio_clear(unsigned index)
    142152{
    143153  if (index <= LPC24XX_IO_INDEX_MAX) {
    144     unsigned port = LPC24XX_IO_PORT( index);
    145     unsigned bit = LPC24XX_IO_PORT_BIT( index);
     154    unsigned port = LPC24XX_IO_PORT(index);
     155    unsigned bit = LPC24XX_IO_PORT_BIT(index);
    146156
    147157    LPC24XX_FIO [port].clr = 1U << bit;
     
    149159}
    150160
    151 static inline void lpc24xx_gpio_write( unsigned index, bool value)
     161static inline void lpc24xx_gpio_write(unsigned index, bool value)
    152162{
    153163  if (value) {
    154     lpc24xx_gpio_set( index);
     164    lpc24xx_gpio_set(index);
    155165  } else {
    156     lpc24xx_gpio_clear( index);
     166    lpc24xx_gpio_clear(index);
    157167  }
    158168}
    159169
    160 static inline bool lpc24xx_gpio_get( unsigned index)
     170static inline bool lpc24xx_gpio_get(unsigned index)
    161171{
    162172  if (index <= LPC24XX_IO_INDEX_MAX) {
    163     unsigned port = LPC24XX_IO_PORT( index);
    164     unsigned bit = LPC24XX_IO_PORT_BIT( index);
     173    unsigned port = LPC24XX_IO_PORT(index);
     174    unsigned bit = LPC24XX_IO_PORT_BIT(index);
    165175
    166176    return (LPC24XX_FIO [port].pin & (1U << bit)) != 0;
  • c/src/lib/libbsp/arm/lpc24xx/include/irq.h

    r9db18dd rc468f18b  
    6969#define LPC24XX_IRQ_PRIORITY_VALUE_MIN 0U
    7070#define LPC24XX_IRQ_PRIORITY_VALUE_MAX 15U
     71#define LPC24XX_IRQ_PRIORITY_COUNT (LPC24XX_IRQ_PRIORITY_VALUE_MAX + 1U)
     72#define LPC24XX_IRQ_PRIORITY_HIGHEST LPC24XX_IRQ_PRIORITY_VALUE_MIN
     73#define LPC24XX_IRQ_PRIORITY_LOWEST LPC24XX_IRQ_PRIORITY_VALUE_MAX
    7174
    7275/**
     
    8083#define BSP_INTERRUPT_VECTOR_MAX LPC24XX_IRQ_I2S
    8184
    82 void bsp_interrupt_dispatch( void);
     85void lpc24xx_irq_set_priority(rtems_vector_number vector, unsigned priority);
    8386
    84 void lpc24xx_irq_set_priority( rtems_vector_number vector, unsigned priority);
    85 
    86 unsigned lpc24xx_irq_priority( rtems_vector_number vector);
     87unsigned lpc24xx_irq_get_priority(rtems_vector_number vector);
    8788
    8889/** @} */
  • c/src/lib/libbsp/arm/lpc24xx/include/lpc24xx.h

    r9db18dd rc468f18b  
    11731173#define CLKSRCSEL_CLKSRC_MASK 0x00000003U
    11741174
    1175 #define GET_CLKSRCSEL_CLKSRC( reg) \
    1176   GET_FIELD( reg, CLKSRCSEL_CLKSRC_MASK, 0)
    1177 
    1178 #define SET_CLKSRCSEL_CLKSRC( reg, val) \
    1179   SET_FIELD( reg, val, CLKSRCSEL_CLKSRC_MASK, 0)
     1175#define GET_CLKSRCSEL_CLKSRC(reg) \
     1176  GET_FIELD(reg, CLKSRCSEL_CLKSRC_MASK, 0)
     1177
     1178#define SET_CLKSRCSEL_CLKSRC(reg, val) \
     1179  SET_FIELD(reg, val, CLKSRCSEL_CLKSRC_MASK, 0)
    11801180
    11811181/* PLLCON */
     
    11891189#define PLLCFG_MSEL_MASK 0x00007fffU
    11901190
    1191 #define GET_PLLCFG_MSEL( reg) \
    1192   GET_FIELD( reg, PLLCFG_MSEL_MASK, 0)
    1193 
    1194 #define SET_PLLCFG_MSEL( reg, val) \
    1195   SET_FIELD( reg, val, PLLCFG_MSEL_MASK, 0)
     1191#define GET_PLLCFG_MSEL(reg) \
     1192  GET_FIELD(reg, PLLCFG_MSEL_MASK, 0)
     1193
     1194#define SET_PLLCFG_MSEL(reg, val) \
     1195  SET_FIELD(reg, val, PLLCFG_MSEL_MASK, 0)
    11961196
    11971197#define PLLCFG_NSEL_MASK 0x00ff0000U
    11981198
    1199 #define GET_PLLCFG_NSEL( reg) \
    1200   GET_FIELD( reg, PLLCFG_NSEL_MASK, 16)
    1201 
    1202 #define SET_PLLCFG_NSEL( reg, val) \
    1203   SET_FIELD( reg, val, PLLCFG_NSEL_MASK, 16)
     1199#define GET_PLLCFG_NSEL(reg) \
     1200  GET_FIELD(reg, PLLCFG_NSEL_MASK, 16)
     1201
     1202#define SET_PLLCFG_NSEL(reg, val) \
     1203  SET_FIELD(reg, val, PLLCFG_NSEL_MASK, 16)
    12041204
    12051205/* PLLSTAT */
     
    12071207#define PLLSTAT_MSEL_MASK 0x00007fffU
    12081208
    1209 #define GET_PLLSTAT_MSEL( reg) \
    1210   GET_FIELD( reg, PLLSTAT_MSEL_MASK, 0)
    1211 
    1212 #define SET_PLLSTAT_MSEL( reg, val) \
    1213   SET_FIELD( reg, val, PLLSTAT_MSEL_MASK, 0)
     1209#define GET_PLLSTAT_MSEL(reg) \
     1210  GET_FIELD(reg, PLLSTAT_MSEL_MASK, 0)
     1211
     1212#define SET_PLLSTAT_MSEL(reg, val) \
     1213  SET_FIELD(reg, val, PLLSTAT_MSEL_MASK, 0)
    12141214
    12151215#define PLLSTAT_NSEL_MASK 0x00ff0000U
    12161216
    1217 #define GET_PLLSTAT_NSEL( reg) \
    1218   GET_FIELD( reg, PLLSTAT_NSEL_MASK, 16)
    1219 
    1220 #define SET_PLLSTAT_NSEL( reg, val) \
    1221   SET_FIELD( reg, val, PLLSTAT_NSEL_MASK, 16)
     1217#define GET_PLLSTAT_NSEL(reg) \
     1218  GET_FIELD(reg, PLLSTAT_NSEL_MASK, 16)
     1219
     1220#define SET_PLLSTAT_NSEL(reg, val) \
     1221  SET_FIELD(reg, val, PLLSTAT_NSEL_MASK, 16)
    12221222
    12231223#define PLLSTAT_PLLE 0x01000000U
     
    12311231#define CCLKCFG_CCLKSEL_MASK 0x000000ffU
    12321232
    1233 #define GET_CCLKCFG_CCLKSEL( reg) \
    1234   GET_FIELD( reg, CCLKCFG_CCLKSEL_MASK, 0)
    1235 
    1236 #define SET_CCLKCFG_CCLKSEL( reg, val) \
    1237   SET_FIELD( reg, val, CCLKCFG_CCLKSEL_MASK, 0)
     1233#define GET_CCLKCFG_CCLKSEL(reg) \
     1234  GET_FIELD(reg, CCLKCFG_CCLKSEL_MASK, 0)
     1235
     1236#define SET_CCLKCFG_CCLKSEL(reg, val) \
     1237  SET_FIELD(reg, val, CCLKCFG_CCLKSEL_MASK, 0)
    12381238
    12391239/* MEMMAP */
     
    12411241#define MEMMAP_MAP_MASK 0x00000003U
    12421242
    1243 #define GET_MEMMAP_MAP( reg) \
    1244   GET_FIELD( reg, MEMMAP_MAP_MASK, 0)
    1245 
    1246 #define SET_MEMMAP_MAP( reg, val) \
    1247   SET_FIELD( reg, val, MEMMAP_MAP_MASK, 0)
     1243#define GET_MEMMAP_MAP(reg) \
     1244  GET_FIELD(reg, MEMMAP_MAP_MASK, 0)
     1245
     1246#define SET_MEMMAP_MAP(reg, val) \
     1247  SET_FIELD(reg, val, MEMMAP_MAP_MASK, 0)
    12481248
    12491249/* TIR */
     
    13011301#define PCLKSEL0_PCLK_WDT_MASK 0x00000003U
    13021302
    1303 #define GET_PCLKSEL0_PCLK_WDT( reg) \
    1304   GET_FIELD( reg, PCLKSEL0_PCLK_WDT_MASK, 0)
    1305 
    1306 #define SET_PCLKSEL0_PCLK_WDT( reg, val) \
    1307   SET_FIELD( reg, val, PCLKSEL0_PCLK_WDT_MASK, 0)
     1303#define GET_PCLKSEL0_PCLK_WDT(reg) \
     1304  GET_FIELD(reg, PCLKSEL0_PCLK_WDT_MASK, 0)
     1305
     1306#define SET_PCLKSEL0_PCLK_WDT(reg, val) \
     1307  SET_FIELD(reg, val, PCLKSEL0_PCLK_WDT_MASK, 0)
    13081308
    13091309#define PCLKSEL0_PCLK_TIMER0_MASK 0x0000000cU
    13101310
    1311 #define GET_PCLKSEL0_PCLK_TIMER0( reg) \
    1312   GET_FIELD( reg, PCLKSEL0_PCLK_TIMER0_MASK, 2)
    1313 
    1314 #define SET_PCLKSEL0_PCLK_TIMER0( reg, val) \
    1315   SET_FIELD( reg, val, PCLKSEL0_PCLK_TIMER0_MASK, 2)
     1311#define GET_PCLKSEL0_PCLK_TIMER0(reg) \
     1312  GET_FIELD(reg, PCLKSEL0_PCLK_TIMER0_MASK, 2)
     1313
     1314#define SET_PCLKSEL0_PCLK_TIMER0(reg, val) \
     1315  SET_FIELD(reg, val, PCLKSEL0_PCLK_TIMER0_MASK, 2)
    13161316
    13171317#define PCLKSEL0_PCLK_TIMER1_MASK 0x00000030U
    13181318
    1319 #define GET_PCLKSEL0_PCLK_TIMER1( reg) \
    1320   GET_FIELD( reg, PCLKSEL0_PCLK_TIMER1_MASK, 4)
    1321 
    1322 #define SET_PCLKSEL0_PCLK_TIMER1( reg, val) \
    1323   SET_FIELD( reg, val, PCLKSEL0_PCLK_TIMER1_MASK, 4)
     1319#define GET_PCLKSEL0_PCLK_TIMER1(reg) \
     1320  GET_FIELD(reg, PCLKSEL0_PCLK_TIMER1_MASK, 4)
     1321
     1322#define SET_PCLKSEL0_PCLK_TIMER1(reg, val) \
     1323  SET_FIELD(reg, val, PCLKSEL0_PCLK_TIMER1_MASK, 4)
    13241324
    13251325#define PCLKSEL0_PCLK_UART0_MASK 0x000000c0U
    13261326
    1327 #define GET_PCLKSEL0_PCLK_UART0( reg) \
    1328   GET_FIELD( reg, PCLKSEL0_PCLK_UART0_MASK, 6)
    1329 
    1330 #define SET_PCLKSEL0_PCLK_UART0( reg, val) \
    1331   SET_FIELD( reg, val, PCLKSEL0_PCLK_UART0_MASK, 6)
     1327#define GET_PCLKSEL0_PCLK_UART0(reg) \
     1328  GET_FIELD(reg, PCLKSEL0_PCLK_UART0_MASK, 6)
     1329
     1330#define SET_PCLKSEL0_PCLK_UART0(reg, val) \
     1331  SET_FIELD(reg, val, PCLKSEL0_PCLK_UART0_MASK, 6)
    13321332
    13331333#define PCLKSEL0_PCLK_UART1_MASK 0x00000300U
    13341334
    1335 #define GET_PCLKSEL0_PCLK_UART1( reg) \
    1336   GET_FIELD( reg, PCLKSEL0_PCLK_UART1_MASK, 8)
    1337 
    1338 #define SET_PCLKSEL0_PCLK_UART1( reg, val) \
    1339   SET_FIELD( reg, val, PCLKSEL0_PCLK_UART1_MASK, 8)
     1335#define GET_PCLKSEL0_PCLK_UART1(reg) \
     1336  GET_FIELD(reg, PCLKSEL0_PCLK_UART1_MASK, 8)
     1337
     1338#define SET_PCLKSEL0_PCLK_UART1(reg, val) \
     1339  SET_FIELD(reg, val, PCLKSEL0_PCLK_UART1_MASK, 8)
    13401340
    13411341#define PCLKSEL0_PCLK_PWM0_MASK 0x00000c00U
    13421342
    1343 #define GET_PCLKSEL0_PCLK_PWM0( reg) \
    1344   GET_FIELD( reg, PCLKSEL0_PCLK_PWM0_MASK, 10)
    1345 
    1346 #define SET_PCLKSEL0_PCLK_PWM0( reg, val) \
    1347   SET_FIELD( reg, val, PCLKSEL0_PCLK_PWM0_MASK, 10)
     1343#define GET_PCLKSEL0_PCLK_PWM0(reg) \
     1344  GET_FIELD(reg, PCLKSEL0_PCLK_PWM0_MASK, 10)
     1345
     1346#define SET_PCLKSEL0_PCLK_PWM0(reg, val) \
     1347  SET_FIELD(reg, val, PCLKSEL0_PCLK_PWM0_MASK, 10)
    13481348
    13491349#define PCLKSEL0_PCLK_PWM1_MASK 0x00003000U
    13501350
    1351 #define GET_PCLKSEL0_PCLK_PWM1( reg) \
    1352   GET_FIELD( reg, PCLKSEL0_PCLK_PWM1_MASK, 12)
    1353 
    1354 #define SET_PCLKSEL0_PCLK_PWM1( reg, val) \
    1355   SET_FIELD( reg, val, PCLKSEL0_PCLK_PWM1_MASK, 12)
     1351#define GET_PCLKSEL0_PCLK_PWM1(reg) \
     1352  GET_FIELD(reg, PCLKSEL0_PCLK_PWM1_MASK, 12)
     1353
     1354#define SET_PCLKSEL0_PCLK_PWM1(reg, val) \
     1355  SET_FIELD(reg, val, PCLKSEL0_PCLK_PWM1_MASK, 12)
    13561356
    13571357#define PCLKSEL0_PCLK_I2C0_MASK 0x0000c000U
    13581358
    1359 #define GET_PCLKSEL0_PCLK_I2C0( reg) \
    1360   GET_FIELD( reg, PCLKSEL0_PCLK_I2C0_MASK, 14)
    1361 
    1362 #define SET_PCLKSEL0_PCLK_I2C0( reg, val) \
    1363   SET_FIELD( reg, val, PCLKSEL0_PCLK_I2C0_MASK, 14)
     1359#define GET_PCLKSEL0_PCLK_I2C0(reg) \
     1360  GET_FIELD(reg, PCLKSEL0_PCLK_I2C0_MASK, 14)
     1361
     1362#define SET_PCLKSEL0_PCLK_I2C0(reg, val) \
     1363  SET_FIELD(reg, val, PCLKSEL0_PCLK_I2C0_MASK, 14)
    13641364
    13651365#define PCLKSEL0_PCLK_SPI_MASK 0x00030000U
    13661366
    1367 #define GET_PCLKSEL0_PCLK_SPI( reg) \
    1368   GET_FIELD( reg, PCLKSEL0_PCLK_SPI_MASK, 16)
    1369 
    1370 #define SET_PCLKSEL0_PCLK_SPI( reg, val) \
    1371   SET_FIELD( reg, val, PCLKSEL0_PCLK_SPI_MASK, 16)
     1367#define GET_PCLKSEL0_PCLK_SPI(reg) \
     1368  GET_FIELD(reg, PCLKSEL0_PCLK_SPI_MASK, 16)
     1369
     1370#define SET_PCLKSEL0_PCLK_SPI(reg, val) \
     1371  SET_FIELD(reg, val, PCLKSEL0_PCLK_SPI_MASK, 16)
    13721372
    13731373#define PCLKSEL0_PCLK_RTC_MASK 0x000c0000U
    13741374
    1375 #define GET_PCLKSEL0_PCLK_RTC( reg) \
    1376   GET_FIELD( reg, PCLKSEL0_PCLK_RTC_MASK, 18)
    1377 
    1378 #define SET_PCLKSEL0_PCLK_RTC( reg, val) \
    1379   SET_FIELD( reg, val, PCLKSEL0_PCLK_RTC_MASK, 18)
     1375#define GET_PCLKSEL0_PCLK_RTC(reg) \
     1376  GET_FIELD(reg, PCLKSEL0_PCLK_RTC_MASK, 18)
     1377
     1378#define SET_PCLKSEL0_PCLK_RTC(reg, val) \
     1379  SET_FIELD(reg, val, PCLKSEL0_PCLK_RTC_MASK, 18)
    13801380
    13811381#define PCLKSEL0_PCLK_SSP1_MASK 0x00300000U
    13821382
    1383 #define GET_PCLKSEL0_PCLK_SSP1( reg) \
    1384   GET_FIELD( reg, PCLKSEL0_PCLK_SSP1_MASK, 20)
    1385 
    1386 #define SET_PCLKSEL0_PCLK_SSP1( reg, val) \
    1387   SET_FIELD( reg, val, PCLKSEL0_PCLK_SSP1_MASK, 20)
     1383#define GET_PCLKSEL0_PCLK_SSP1(reg) \
     1384  GET_FIELD(reg, PCLKSEL0_PCLK_SSP1_MASK, 20)
     1385
     1386#define SET_PCLKSEL0_PCLK_SSP1(reg, val) \
     1387  SET_FIELD(reg, val, PCLKSEL0_PCLK_SSP1_MASK, 20)
    13881388
    13891389#define PCLKSEL0_PCLK_DAC_MASK 0x00c00000U
    13901390
    1391 #define GET_PCLKSEL0_PCLK_DAC( reg) \
    1392   GET_FIELD( reg, PCLKSEL0_PCLK_DAC_MASK, 22)
    1393 
    1394 #define SET_PCLKSEL0_PCLK_DAC( reg, val) \
    1395   SET_FIELD( reg, val, PCLKSEL0_PCLK_DAC_MASK, 22)
     1391#define GET_PCLKSEL0_PCLK_DAC(reg) \
     1392  GET_FIELD(reg, PCLKSEL0_PCLK_DAC_MASK, 22)
     1393
     1394#define SET_PCLKSEL0_PCLK_DAC(reg, val) \
     1395  SET_FIELD(reg, val, PCLKSEL0_PCLK_DAC_MASK, 22)
    13961396
    13971397#define PCLKSEL0_PCLK_ADC_MASK 0x03000000U
    13981398
    1399 #define GET_PCLKSEL0_PCLK_ADC( reg) \
    1400   GET_FIELD( reg, PCLKSEL0_PCLK_ADC_MASK, 24)
    1401 
    1402 #define SET_PCLKSEL0_PCLK_ADC( reg, val) \
    1403   SET_FIELD( reg, val, PCLKSEL0_PCLK_ADC_MASK, 24)
     1399#define GET_PCLKSEL0_PCLK_ADC(reg) \
     1400  GET_FIELD(reg, PCLKSEL0_PCLK_ADC_MASK, 24)
     1401
     1402#define SET_PCLKSEL0_PCLK_ADC(reg, val) \
     1403  SET_FIELD(reg, val, PCLKSEL0_PCLK_ADC_MASK, 24)
    14041404
    14051405#define PCLKSEL0_PCLK_CAN1_MASK 0x0c000000U
    14061406
    1407 #define GET_PCLKSEL0_PCLK_CAN1( reg) \
    1408   GET_FIELD( reg, PCLKSEL0_PCLK_CAN1_MASK, 26)
    1409 
    1410 #define SET_PCLKSEL0_PCLK_CAN1( reg, val) \
    1411   SET_FIELD( reg, val, PCLKSEL0_PCLK_CAN1_MASK, 26)
     1407#define GET_PCLKSEL0_PCLK_CAN1(reg) \
     1408  GET_FIELD(reg, PCLKSEL0_PCLK_CAN1_MASK, 26)
     1409
     1410#define SET_PCLKSEL0_PCLK_CAN1(reg, val) \
     1411  SET_FIELD(reg, val, PCLKSEL0_PCLK_CAN1_MASK, 26)
    14121412
    14131413#define PCLKSEL0_PCLK_CAN2_MASK 0x30000000U
    14141414
    1415 #define GET_PCLKSEL0_PCLK_CAN2( reg) \
    1416   GET_FIELD( reg, PCLKSEL0_PCLK_CAN2_MASK, 28)
    1417 
    1418 #define SET_PCLKSEL0_PCLK_CAN2( reg, val) \
    1419   SET_FIELD( reg, val, PCLKSEL0_PCLK_CAN2_MASK, 28)
     1415#define GET_PCLKSEL0_PCLK_CAN2(reg) \
     1416  GET_FIELD(reg, PCLKSEL0_PCLK_CAN2_MASK, 28)
     1417
     1418#define SET_PCLKSEL0_PCLK_CAN2(reg, val) \
     1419  SET_FIELD(reg, val, PCLKSEL0_PCLK_CAN2_MASK, 28)
    14201420
    14211421/* PCLKSEL1 */
     
    14231423#define PCLKSEL1_PCLK_BAT_RAM_MASK 0x00000003U
    14241424
    1425 #define GET_PCLKSEL1_PCLK_BAT_RAM( reg) \
    1426   GET_FIELD( reg, PCLKSEL1_PCLK_BAT_RAM_MASK, 0)
    1427 
    1428 #define SET_PCLKSEL1_PCLK_BAT_RAM( reg, val) \
    1429   SET_FIELD( reg, val, PCLKSEL1_PCLK_BAT_RAM_MASK, 0)
     1425#define GET_PCLKSEL1_PCLK_BAT_RAM(reg) \
     1426  GET_FIELD(reg, PCLKSEL1_PCLK_BAT_RAM_MASK, 0)
     1427
     1428#define SET_PCLKSEL1_PCLK_BAT_RAM(reg, val) \
     1429  SET_FIELD(reg, val, PCLKSEL1_PCLK_BAT_RAM_MASK, 0)
    14301430
    14311431#define PCLKSEL1_PCLK_GPIO_MASK 0x0000000cU
    14321432
    1433 #define GET_PCLKSEL1_PCLK_GPIO( reg) \
    1434   GET_FIELD( reg, PCLKSEL1_PCLK_GPIO_MASK, 2)
    1435 
    1436 #define SET_PCLKSEL1_PCLK_GPIO( reg, val) \
    1437   SET_FIELD( reg, val, PCLKSEL1_PCLK_GPIO_MASK, 2)
     1433#define GET_PCLKSEL1_PCLK_GPIO(reg) \
     1434  GET_FIELD(reg, PCLKSEL1_PCLK_GPIO_MASK, 2)
     1435
     1436#define SET_PCLKSEL1_PCLK_GPIO(reg, val) \
     1437  SET_FIELD(reg, val, PCLKSEL1_PCLK_GPIO_MASK, 2)
    14381438
    14391439#define PCLKSEL1_PCLK_PCB_MASK 0x00000030U
    14401440
    1441 #define GET_PCLKSEL1_PCLK_PCB( reg) \
    1442   GET_FIELD( reg, PCLKSEL1_PCLK_PCB_MASK, 4)
    1443 
    1444 #define SET_PCLKSEL1_PCLK_PCB( reg, val) \
    1445   SET_FIELD( reg, val, PCLKSEL1_PCLK_PCB_MASK, 4)
     1441#define GET_PCLKSEL1_PCLK_PCB(reg) \
     1442  GET_FIELD(reg, PCLKSEL1_PCLK_PCB_MASK, 4)
     1443
     1444#define SET_PCLKSEL1_PCLK_PCB(reg, val) \
     1445  SET_FIELD(reg, val, PCLKSEL1_PCLK_PCB_MASK, 4)
    14461446
    14471447#define PCLKSEL1_PCLK_I2C1_MASK 0x000000c0U
    14481448
    1449 #define GET_PCLKSEL1_PCLK_I2C1( reg) \
    1450   GET_FIELD( reg, PCLKSEL1_PCLK_I2C1_MASK, 6)
    1451 
    1452 #define SET_PCLKSEL1_PCLK_I2C1( reg, val) \
    1453   SET_FIELD( reg, val, PCLKSEL1_PCLK_I2C1_MASK, 6)
     1449#define GET_PCLKSEL1_PCLK_I2C1(reg) \
     1450  GET_FIELD(reg, PCLKSEL1_PCLK_I2C1_MASK, 6)
     1451
     1452#define SET_PCLKSEL1_PCLK_I2C1(reg, val) \
     1453  SET_FIELD(reg, val, PCLKSEL1_PCLK_I2C1_MASK, 6)
    14541454
    14551455#define PCLKSEL1_PCLK_SSP0_MASK 0x00000c00U
    14561456
    1457 #define GET_PCLKSEL1_PCLK_SSP0( reg) \
    1458   GET_FIELD( reg, PCLKSEL1_PCLK_SSP0_MASK, 10)
    1459 
    1460 #define SET_PCLKSEL1_PCLK_SSP0( reg, val) \
    1461   SET_FIELD( reg, val, PCLKSEL1_PCLK_SSP0_MASK, 10)
     1457#define GET_PCLKSEL1_PCLK_SSP0(reg) \
     1458  GET_FIELD(reg, PCLKSEL1_PCLK_SSP0_MASK, 10)
     1459
     1460#define SET_PCLKSEL1_PCLK_SSP0(reg, val) \
     1461  SET_FIELD(reg, val, PCLKSEL1_PCLK_SSP0_MASK, 10)
    14621462
    14631463#define PCLKSEL1_PCLK_TIMER2_MASK 0x00003000U
    14641464
    1465 #define GET_PCLKSEL1_PCLK_TIMER2( reg) \
    1466   GET_FIELD( reg, PCLKSEL1_PCLK_TIMER2_MASK, 12)
    1467 
    1468 #define SET_PCLKSEL1_PCLK_TIMER2( reg, val) \
    1469   SET_FIELD( reg, val, PCLKSEL1_PCLK_TIMER2_MASK, 12)
     1465#define GET_PCLKSEL1_PCLK_TIMER2(reg) \
     1466  GET_FIELD(reg, PCLKSEL1_PCLK_TIMER2_MASK, 12)
     1467
     1468#define SET_PCLKSEL1_PCLK_TIMER2(reg, val) \
     1469  SET_FIELD(reg, val, PCLKSEL1_PCLK_TIMER2_MASK, 12)
    14701470
    14711471#define PCLKSEL1_PCLK_TIMER3_MASK 0x0000c000U
    14721472
    1473 #define GET_PCLKSEL1_PCLK_TIMER3( reg) \
    1474   GET_FIELD( reg, PCLKSEL1_PCLK_TIMER3_MASK, 14)
    1475 
    1476 #define SET_PCLKSEL1_PCLK_TIMER3( reg, val) \
    1477   SET_FIELD( reg, val, PCLKSEL1_PCLK_TIMER3_MASK, 14)
     1473#define GET_PCLKSEL1_PCLK_TIMER3(reg) \
     1474  GET_FIELD(reg, PCLKSEL1_PCLK_TIMER3_MASK, 14)
     1475
     1476#define SET_PCLKSEL1_PCLK_TIMER3(reg, val) \
     1477  SET_FIELD(reg, val, PCLKSEL1_PCLK_TIMER3_MASK, 14)
    14781478
    14791479#define PCLKSEL1_PCLK_UART2_MASK 0x00030000U
    14801480
    1481 #define GET_PCLKSEL1_PCLK_UART2( reg) \
    1482   GET_FIELD( reg, PCLKSEL1_PCLK_UART2_MASK, 16)
    1483 
    1484 #define SET_PCLKSEL1_PCLK_UART2( reg, val) \
    1485   SET_FIELD( reg, val, PCLKSEL1_PCLK_UART2_MASK, 16)
     1481#define GET_PCLKSEL1_PCLK_UART2(reg) \
     1482  GET_FIELD(reg, PCLKSEL1_PCLK_UART2_MASK, 16)
     1483
     1484#define SET_PCLKSEL1_PCLK_UART2(reg, val) \
     1485  SET_FIELD(reg, val, PCLKSEL1_PCLK_UART2_MASK, 16)
    14861486
    14871487#define PCLKSEL1_PCLK_UART3_MASK 0x000c0000U
    14881488
    1489 #define GET_PCLKSEL1_PCLK_UART3( reg) \
    1490   GET_FIELD( reg, PCLKSEL1_PCLK_UART3_MASK, 18)
    1491 
    1492 #define SET_PCLKSEL1_PCLK_UART3( reg, val) \
    1493   SET_FIELD( reg, val, PCLKSEL1_PCLK_UART3_MASK, 18)
     1489#define GET_PCLKSEL1_PCLK_UART3(reg) \
     1490  GET_FIELD(reg, PCLKSEL1_PCLK_UART3_MASK, 18)
     1491
     1492#define SET_PCLKSEL1_PCLK_UART3(reg, val) \
     1493  SET_FIELD(reg, val, PCLKSEL1_PCLK_UART3_MASK, 18)
    14941494
    14951495#define PCLKSEL1_PCLK_I2C2_MASK 0x00300000U
    14961496
    1497 #define GET_PCLKSEL1_PCLK_I2C2( reg) \
    1498   GET_FIELD( reg, PCLKSEL1_PCLK_I2C2_MASK, 20)
    1499 
    1500 #define SET_PCLKSEL1_PCLK_I2C2( reg, val) \
    1501   SET_FIELD( reg, val, PCLKSEL1_PCLK_I2C2_MASK, 20)
     1497#define GET_PCLKSEL1_PCLK_I2C2(reg) \
     1498  GET_FIELD(reg, PCLKSEL1_PCLK_I2C2_MASK, 20)
     1499
     1500#define SET_PCLKSEL1_PCLK_I2C2(reg, val) \
     1501  SET_FIELD(reg, val, PCLKSEL1_PCLK_I2C2_MASK, 20)
    15021502
    15031503#define PCLKSEL1_PCLK_I2S_MASK 0x00c00000U
    15041504
    1505 #define GET_PCLKSEL1_PCLK_I2S( reg) \
    1506   GET_FIELD( reg, PCLKSEL1_PCLK_I2S_MASK, 22)
    1507 
    1508 #define SET_PCLKSEL1_PCLK_I2S( reg, val) \
    1509   SET_FIELD( reg, val, PCLKSEL1_PCLK_I2S_MASK, 22)
     1505#define GET_PCLKSEL1_PCLK_I2S(reg) \
     1506  GET_FIELD(reg, PCLKSEL1_PCLK_I2S_MASK, 22)
     1507
     1508#define SET_PCLKSEL1_PCLK_I2S(reg, val) \
     1509  SET_FIELD(reg, val, PCLKSEL1_PCLK_I2S_MASK, 22)
    15101510
    15111511#define PCLKSEL1_PCLK_MCI_MASK 0x03000000U
    15121512
    1513 #define GET_PCLKSEL1_PCLK_MCI( reg) \
    1514   GET_FIELD( reg, PCLKSEL1_PCLK_MCI_MASK, 24)
    1515 
    1516 #define SET_PCLKSEL1_PCLK_MCI( reg, val) \
    1517   SET_FIELD( reg, val, PCLKSEL1_PCLK_MCI_MASK, 24)
     1513#define GET_PCLKSEL1_PCLK_MCI(reg) \
     1514  GET_FIELD(reg, PCLKSEL1_PCLK_MCI_MASK, 24)
     1515
     1516#define SET_PCLKSEL1_PCLK_MCI(reg, val) \
     1517  SET_FIELD(reg, val, PCLKSEL1_PCLK_MCI_MASK, 24)
    15181518
    15191519#define PCLKSEL1_PCLK_SYSCON_MASK 0x30000000U
    15201520
    1521 #define GET_PCLKSEL1_PCLK_SYSCON( reg) \
    1522   GET_FIELD( reg, PCLKSEL1_PCLK_SYSCON_MASK, 28)
    1523 
    1524 #define SET_PCLKSEL1_PCLK_SYSCON( reg, val) \
    1525   SET_FIELD( reg, val, PCLKSEL1_PCLK_SYSCON_MASK, 28)
     1521#define GET_PCLKSEL1_PCLK_SYSCON(reg) \
     1522  GET_FIELD(reg, PCLKSEL1_PCLK_SYSCON_MASK, 28)
     1523
     1524#define SET_PCLKSEL1_PCLK_SYSCON(reg, val) \
     1525  SET_FIELD(reg, val, PCLKSEL1_PCLK_SYSCON_MASK, 28)
    15261526
    15271527/* RTC_ILR */
     
    15601560#define SSP_CR0_DSS_MASK 0x0000000fU
    15611561
    1562 #define GET_SSP_CR0_DSS( reg) \
    1563   GET_FIELD( reg, SSP_CR0_DSS_MASK, 0)
    1564 
    1565 #define SET_SSP_CR0_DSS( reg, val) \
    1566   SET_FIELD( reg, val, SSP_CR0_DSS_MASK, 0)
     1562#define GET_SSP_CR0_DSS(reg) \
     1563  GET_FIELD(reg, SSP_CR0_DSS_MASK, 0)
     1564
     1565#define SET_SSP_CR0_DSS(reg, val) \
     1566  SET_FIELD(reg, val, SSP_CR0_DSS_MASK, 0)
    15671567
    15681568#define SSP_CR0_FRF_MASK 0x00000030U
    15691569
    1570 #define GET_SSP_CR0_FRF( reg) \
    1571   GET_FIELD( reg, SSP_CR0_FRF_MASK, 4)
    1572 
    1573 #define SET_SSP_CR0_FRF( reg, val) \
    1574   SET_FIELD( reg, val, SSP_CR0_FRF_MASK, 4)
     1570#define GET_SSP_CR0_FRF(reg) \
     1571  GET_FIELD(reg, SSP_CR0_FRF_MASK, 4)
     1572
     1573#define SET_SSP_CR0_FRF(reg, val) \
     1574  SET_FIELD(reg, val, SSP_CR0_FRF_MASK, 4)
    15751575
    15761576#define SSP_CR0_CPOL 0x00000040U
     
    15801580#define SSP_CR0_SCR_MASK 0x0000ff00U
    15811581
    1582 #define GET_SSP_CR0_SCR( reg) \
    1583   GET_FIELD( reg, SSP_CR0_SCR_MASK, 8)
    1584 
    1585 #define SET_SSP_CR0_SCR( reg, val) \
    1586   SET_FIELD( reg, val, SSP_CR0_SCR_MASK, 8)
     1582#define GET_SSP_CR0_SCR(reg) \
     1583  GET_FIELD(reg, SSP_CR0_SCR_MASK, 8)
     1584
     1585#define SET_SSP_CR0_SCR(reg, val) \
     1586  SET_FIELD(reg, val, SSP_CR0_SCR_MASK, 8)
    15871587
    15881588/* SSP_CR1 */
     
    16741674#define GPDMA_STATUS_CH_1 0x00000002U
    16751675
    1676 #define GPDMA_CH_BASE_ADDR( i) \
     1676#define GPDMA_CH_BASE_ADDR(i) \
    16771677  ((volatile lpc24xx_dma_channel *) \
    16781678    ((i) ? GPDMA_CH1_BASE_ADDR : GPDMA_CH0_BASE_ADDR))
     
    16941694#define GPDMA_CH_CTRL_TSZ_MASK 0x00000fffU
    16951695
    1696 #define GET_GPDMA_CH_CTRL_TSZ( reg) \
    1697   GET_FIELD( reg, GPDMA_CH_CTRL_TSZ_MASK, 0)
    1698 
    1699 #define SET_GPDMA_CH_CTRL_TSZ( reg, val) \
    1700   SET_FIELD( reg, val, GPDMA_CH_CTRL_TSZ_MASK, 0)
     1696#define GET_GPDMA_CH_CTRL_TSZ(reg) \
     1697  GET_FIELD(reg, GPDMA_CH_CTRL_TSZ_MASK, 0)
     1698
     1699#define SET_GPDMA_CH_CTRL_TSZ(reg, val) \
     1700  SET_FIELD(reg, val, GPDMA_CH_CTRL_TSZ_MASK, 0)
    17011701
    17021702#define GPDMA_CH_CTRL_TSZ_MAX 0x00000fffU
     
    17041704#define GPDMA_CH_CTRL_SBSZ_MASK 0x00007000U
    17051705
    1706 #define GET_GPDMA_CH_CTRL_SBSZ( reg) \
    1707   GET_FIELD( reg, GPDMA_CH_CTRL_SBSZ_MASK, 12)
    1708 
    1709 #define SET_GPDMA_CH_CTRL_SBSZ( reg, val) \
    1710   SET_FIELD( reg, val, GPDMA_CH_CTRL_SBSZ_MASK, 12)
     1706#define GET_GPDMA_CH_CTRL_SBSZ(reg) \
     1707  GET_FIELD(reg, GPDMA_CH_CTRL_SBSZ_MASK, 12)
     1708
     1709#define SET_GPDMA_CH_CTRL_SBSZ(reg, val) \
     1710  SET_FIELD(reg, val, GPDMA_CH_CTRL_SBSZ_MASK, 12)
    17111711
    17121712#define GPDMA_CH_CTRL_DBSZ_MASK 0x00038000U
    17131713
    1714 #define GET_GPDMA_CH_CTRL_DBSZ( reg) \
    1715   GET_FIELD( reg, GPDMA_CH_CTRL_DBSZ_MASK, 15)
    1716 
    1717 #define SET_GPDMA_CH_CTRL_DBSZ( reg, val) \
    1718   SET_FIELD( reg, val, GPDMA_CH_CTRL_DBSZ_MASK, 15)
     1714#define GET_GPDMA_CH_CTRL_DBSZ(reg) \
     1715  GET_FIELD(reg, GPDMA_CH_CTRL_DBSZ_MASK, 15)
     1716
     1717#define SET_GPDMA_CH_CTRL_DBSZ(reg, val) \
     1718  SET_FIELD(reg, val, GPDMA_CH_CTRL_DBSZ_MASK, 15)
    17191719
    17201720#define GPDMA_CH_CTRL_BSZ_1 0x00000000U
     
    17361736#define GPDMA_CH_CTRL_SW_MASK 0x001c0000U
    17371737
    1738 #define GET_GPDMA_CH_CTRL_SW( reg) \
    1739   GET_FIELD( reg, GPDMA_CH_CTRL_SW_MASK, 18)
    1740 
    1741 #define SET_GPDMA_CH_CTRL_SW( reg, val) \
    1742   SET_FIELD( reg, val, GPDMA_CH_CTRL_SW_MASK, 18)
     1738#define GET_GPDMA_CH_CTRL_SW(reg) \
     1739  GET_FIELD(reg, GPDMA_CH_CTRL_SW_MASK, 18)
     1740
     1741#define SET_GPDMA_CH_CTRL_SW(reg, val) \
     1742  SET_FIELD(reg, val, GPDMA_CH_CTRL_SW_MASK, 18)
    17431743
    17441744#define GPDMA_CH_CTRL_DW_MASK 0x00e00000U
    17451745
    1746 #define GET_GPDMA_CH_CTRL_DW( reg) \
    1747   GET_FIELD( reg, GPDMA_CH_CTRL_DW_MASK, 21)
    1748 
    1749 #define SET_GPDMA_CH_CTRL_DW( reg, val) \
    1750   SET_FIELD( reg, val, GPDMA_CH_CTRL_DW_MASK, 21)
     1746#define GET_GPDMA_CH_CTRL_DW(reg) \
     1747  GET_FIELD(reg, GPDMA_CH_CTRL_DW_MASK, 21)
     1748
     1749#define SET_GPDMA_CH_CTRL_DW(reg, val) \
     1750  SET_FIELD(reg, val, GPDMA_CH_CTRL_DW_MASK, 21)
    17511751
    17521752#define GPDMA_CH_CTRL_W_8 0x00000000U
     
    17621762#define GPDMA_CH_CTRL_PROT_MASK 0x70000000U
    17631763
    1764 #define GET_GPDMA_CH_CTRL_PROT( reg) \
    1765   GET_FIELD( reg, GPDMA_CH_CTRL_PROT_MASK, 28)
    1766 
    1767 #define SET_GPDMA_CH_CTRL_PROT( reg, val) \
    1768   SET_FIELD( reg, val, GPDMA_CH_CTRL_PROT_MASK, 28)
     1764#define GET_GPDMA_CH_CTRL_PROT(reg) \
     1765  GET_FIELD(reg, GPDMA_CH_CTRL_PROT_MASK, 28)
     1766
     1767#define SET_GPDMA_CH_CTRL_PROT(reg, val) \
     1768  SET_FIELD(reg, val, GPDMA_CH_CTRL_PROT_MASK, 28)
    17691769
    17701770#define GPDMA_CH_CTRL_ITC 0x80000000U
     
    17761776#define GPDMA_CH_CFG_SRCPER_MASK 0x0000001eU
    17771777
    1778 #define GET_GPDMA_CH_CFG_SRCPER( reg) \
    1779   GET_FIELD( reg, GPDMA_CH_CFG_SRCPER_MASK, 1)
    1780 
    1781 #define SET_GPDMA_CH_CFG_SRCPER( reg, val) \
    1782   SET_FIELD( reg, val, GPDMA_CH_CFG_SRCPER_MASK, 1)
     1778#define GET_GPDMA_CH_CFG_SRCPER(reg) \
     1779  GET_FIELD(reg, GPDMA_CH_CFG_SRCPER_MASK, 1)
     1780
     1781#define SET_GPDMA_CH_CFG_SRCPER(reg, val) \
     1782  SET_FIELD(reg, val, GPDMA_CH_CFG_SRCPER_MASK, 1)
    17831783
    17841784#define GPDMA_CH_CFG_DESTPER_MASK 0x000003c0U
    17851785
    1786 #define GET_GPDMA_CH_CFG_DESTPER( reg) \
    1787   GET_FIELD( reg, GPDMA_CH_CFG_DESTPER_MASK, 6)
    1788 
    1789 #define SET_GPDMA_CH_CFG_DESTPER( reg, val) \
    1790   SET_FIELD( reg, val, GPDMA_CH_CFG_DESTPER_MASK, 6)
     1786#define GET_GPDMA_CH_CFG_DESTPER(reg) \
     1787  GET_FIELD(reg, GPDMA_CH_CFG_DESTPER_MASK, 6)
     1788
     1789#define SET_GPDMA_CH_CFG_DESTPER(reg, val) \
     1790  SET_FIELD(reg, val, GPDMA_CH_CFG_DESTPER_MASK, 6)
    17911791
    17921792#define GPDMA_CH_CFG_PER_SSP0_TX 0x00000000U
     
    18061806#define GPDMA_CH_CFG_FLOW_MASK 0x00003800U
    18071807
    1808 #define GET_GPDMA_CH_CFG_FLOW( reg) \
    1809   GET_FIELD( reg, GPDMA_CH_CFG_FLOW_MASK, 11)
    1810 
    1811 #define SET_GPDMA_CH_CFG_FLOW( reg, val) \
    1812   SET_FIELD( reg, val, GPDMA_CH_CFG_FLOW_MASK, 11)
     1808#define GET_GPDMA_CH_CFG_FLOW(reg) \
     1809  GET_FIELD(reg, GPDMA_CH_CFG_FLOW_MASK, 11)
     1810
     1811#define SET_GPDMA_CH_CFG_FLOW(reg, val) \
     1812  SET_FIELD(reg, val, GPDMA_CH_CFG_FLOW_MASK, 11)
    18131813
    18141814#define GPDMA_CH_CFG_FLOW_MEM_TO_MEM_DMA 0x00000000U
     
    18601860#define ETH_RX_CTRL_SIZE_MASK 0x000007ffU
    18611861
    1862 #define GET_ETH_RX_CTRL_SIZE( reg) \
    1863   GET_FIELD( reg, ETH_RX_CTRL_SIZE_MASK, 0)
    1864 
    1865 #define SET_ETH_RX_CTRL_SIZE( reg, val) \
    1866   SET_FIELD( reg, val, ETH_RX_CTRL_SIZE_MASK, 0)
     1862#define GET_ETH_RX_CTRL_SIZE(reg) \
     1863  GET_FIELD(reg, ETH_RX_CTRL_SIZE_MASK, 0)
     1864
     1865#define SET_ETH_RX_CTRL_SIZE(reg, val) \
     1866  SET_FIELD(reg, val, ETH_RX_CTRL_SIZE_MASK, 0)
    18671867
    18681868#define ETH_RX_CTRL_INTERRUPT 0x80000000U
     
    18721872#define ETH_RX_STAT_RXSIZE_MASK 0x000007ffU
    18731873
    1874 #define GET_ETH_RX_STAT_RXSIZE( reg) \
    1875   GET_FIELD( reg, ETH_RX_STAT_RXSIZE_MASK, 0)
    1876 
    1877 #define SET_ETH_RX_STAT_RXSIZE( reg, val) \
    1878   SET_FIELD( reg, val, ETH_RX_STAT_RXSIZE_MASK, 0)
     1874#define GET_ETH_RX_STAT_RXSIZE(reg) \
     1875  GET_FIELD(reg, ETH_RX_STAT_RXSIZE_MASK, 0)
     1876
     1877#define SET_ETH_RX_STAT_RXSIZE(reg, val) \
     1878  SET_FIELD(reg, val, ETH_RX_STAT_RXSIZE_MASK, 0)
    18791879
    18801880#define ETH_RX_STAT_BYTES 0x00000100U
     
    19121912#define ETH_TX_CTRL_SIZE_MASK 0x000007ffU
    19131913
    1914 #define GET_ETH_TX_CTRL_SIZE( reg) \
    1915   GET_FIELD( reg, ETH_TX_CTRL_SIZE_MASK, 0)
    1916 
    1917 #define SET_ETH_TX_CTRL_SIZE( reg, val) \
    1918   SET_FIELD( reg, val, ETH_TX_CTRL_SIZE_MASK, 0)
     1914#define GET_ETH_TX_CTRL_SIZE(reg) \
     1915  GET_FIELD(reg, ETH_TX_CTRL_SIZE_MASK, 0)
     1916
     1917#define SET_ETH_TX_CTRL_SIZE(reg, val) \
     1918  SET_FIELD(reg, val, ETH_TX_CTRL_SIZE_MASK, 0)
    19191919
    19201920#define ETH_TX_CTRL_OVERRIDE 0x04000000U
     
    19341934#define ETH_TX_STAT_COLLISION_COUNT_MASK 0x01e00000U
    19351935
    1936 #define GET_ETH_TX_STAT_COLLISION_COUNT( reg) \
    1937   GET_FIELD( reg, ETH_TX_STAT_COLLISION_COUNT_MASK, 21)
    1938 
    1939 #define SET_ETH_TX_STAT_COLLISION_COUNT( reg, val) \
    1940   SET_FIELD( reg, val, ETH_TX_STAT_COLLISION_COUNT_MASK, 21)
     1936#define GET_ETH_TX_STAT_COLLISION_COUNT(reg) \
     1937  GET_FIELD(reg, ETH_TX_STAT_COLLISION_COUNT_MASK, 21)
     1938
     1939#define SET_ETH_TX_STAT_COLLISION_COUNT(reg, val) \
     1940  SET_FIELD(reg, val, ETH_TX_STAT_COLLISION_COUNT_MASK, 21)
    19411941
    19421942#define ETH_TX_STAT_DEFER 0x02000000U
     
    20282028#define AHBCFG_BREAK_BURST_MASK 0x00000006U
    20292029
    2030 #define GET_AHBCFG_BREAK_BURST( reg) \
    2031   GET_FIELD( reg, AHBCFG_BREAK_BURST_MASK, 1)
    2032 
    2033 #define SET_AHBCFG_BREAK_BURST( reg, val) \
    2034   SET_FIELD( reg, val, AHBCFG_BREAK_BURST_MASK, 1)
     2030#define GET_AHBCFG_BREAK_BURST(reg) \
     2031  GET_FIELD(reg, AHBCFG_BREAK_BURST_MASK, 1)
     2032
     2033#define SET_AHBCFG_BREAK_BURST(reg, val) \
     2034  SET_FIELD(reg, val, AHBCFG_BREAK_BURST_MASK, 1)
    20352035
    20362036#define AHBCFG_QUANTUM_BUS_CYCLE 0x00000008U
     
    20382038#define AHBCFG_QUANTUM_SIZE_MASK 0x000000f0U
    20392039
    2040 #define GET_AHBCFG_QUANTUM_SIZE( reg) \
    2041   GET_FIELD( reg, AHBCFG_QUANTUM_SIZE_MASK, 4)
    2042 
    2043 #define SET_AHBCFG_QUANTUM_SIZE( reg, val) \
    2044   SET_FIELD( reg, val, AHBCFG_QUANTUM_SIZE_MASK, 4)
     2040#define GET_AHBCFG_QUANTUM_SIZE(reg) \
     2041  GET_FIELD(reg, AHBCFG_QUANTUM_SIZE_MASK, 4)
     2042
     2043#define SET_AHBCFG_QUANTUM_SIZE(reg, val) \
     2044  SET_FIELD(reg, val, AHBCFG_QUANTUM_SIZE_MASK, 4)
    20452045
    20462046#define AHBCFG_DEFAULT_MASTER_MASK 0x00000700U
    20472047
    2048 #define GET_AHBCFG_DEFAULT_MASTER( reg) \
    2049   GET_FIELD( reg, AHBCFG_DEFAULT_MASTER_MASK, 8)
    2050 
    2051 #define SET_AHBCFG_DEFAULT_MASTER( reg, val) \
    2052   SET_FIELD( reg, val, AHBCFG_DEFAULT_MASTER_MASK, 8)
     2048#define GET_AHBCFG_DEFAULT_MASTER(reg) \
     2049  GET_FIELD(reg, AHBCFG_DEFAULT_MASTER_MASK, 8)
     2050
     2051#define SET_AHBCFG_DEFAULT_MASTER(reg, val) \
     2052  SET_FIELD(reg, val, AHBCFG_DEFAULT_MASTER_MASK, 8)
    20532053
    20542054#define AHBCFG_EP1_MASK 0x00007000U
    20552055
    2056 #define GET_AHBCFG_EP1( reg) \
    2057   GET_FIELD( reg, AHBCFG_EP1_MASK, 12)
    2058 
    2059 #define SET_AHBCFG_EP1( reg, val) \
    2060   SET_FIELD( reg, val, AHBCFG_EP1_MASK, 12)
     2056#define GET_AHBCFG_EP1(reg) \
     2057  GET_FIELD(reg, AHBCFG_EP1_MASK, 12)
     2058
     2059#define SET_AHBCFG_EP1(reg, val) \
     2060  SET_FIELD(reg, val, AHBCFG_EP1_MASK, 12)
    20612061
    20622062#define AHBCFG_EP2_MASK 0x00070000U
    20632063
    2064 #define GET_AHBCFG_EP2( reg) \
    2065   GET_FIELD( reg, AHBCFG_EP2_MASK, 16)
    2066 
    2067 #define SET_AHBCFG_EP2( reg, val) \
    2068   SET_FIELD( reg, val, AHBCFG_EP2_MASK, 16)
     2064#define GET_AHBCFG_EP2(reg) \
     2065  GET_FIELD(reg, AHBCFG_EP2_MASK, 16)
     2066
     2067#define SET_AHBCFG_EP2(reg, val) \
     2068  SET_FIELD(reg, val, AHBCFG_EP2_MASK, 16)
    20692069
    20702070#define AHBCFG_EP3_MASK 0x00700000U
    20712071
    2072 #define GET_AHBCFG_EP3( reg) \
    2073   GET_FIELD( reg, AHBCFG_EP3_MASK, 20)
    2074 
    2075 #define SET_AHBCFG_EP3( reg, val) \
    2076   SET_FIELD( reg, val, AHBCFG_EP3_MASK, 20)
     2072#define GET_AHBCFG_EP3(reg) \
     2073  GET_FIELD(reg, AHBCFG_EP3_MASK, 20)
     2074
     2075#define SET_AHBCFG_EP3(reg, val) \
     2076  SET_FIELD(reg, val, AHBCFG_EP3_MASK, 20)
    20772077
    20782078#define AHBCFG_EP4_MASK 0x07000000U
    20792079
    2080 #define GET_AHBCFG_EP4( reg) \
    2081   GET_FIELD( reg, AHBCFG_EP4_MASK, 24)
    2082 
    2083 #define SET_AHBCFG_EP4( reg, val) \
    2084   SET_FIELD( reg, val, AHBCFG_EP4_MASK, 24)
     2080#define GET_AHBCFG_EP4(reg) \
     2081  GET_FIELD(reg, AHBCFG_EP4_MASK, 24)
     2082
     2083#define SET_AHBCFG_EP4(reg, val) \
     2084  SET_FIELD(reg, val, AHBCFG_EP4_MASK, 24)
    20852085
    20862086#define AHBCFG_EP5_MASK 0x70000000U
    20872087
    2088 #define GET_AHBCFG_EP5( reg) \
    2089   GET_FIELD( reg, AHBCFG_EP5_MASK, 28)
    2090 
    2091 #define SET_AHBCFG_EP5( reg, val) \
    2092   SET_FIELD( reg, val, AHBCFG_EP5_MASK, 28)
     2088#define GET_AHBCFG_EP5(reg) \
     2089  GET_FIELD(reg, AHBCFG_EP5_MASK, 28)
     2090
     2091#define SET_AHBCFG_EP5(reg, val) \
     2092  SET_FIELD(reg, val, AHBCFG_EP5_MASK, 28)
    20932093
    20942094/* EMC */
  • c/src/lib/libbsp/arm/lpc24xx/irq/irq.c

    r9db18dd rc468f18b  
    2424#include <bsp/lpc24xx.h>
    2525
    26 static inline bool lpc24xx_irq_is_valid( rtems_vector_number vector)
     26static inline bool lpc24xx_irq_is_valid(rtems_vector_number vector)
    2727{
    2828  return vector <= BSP_INTERRUPT_VECTOR_MAX;
    2929}
    3030
    31 void lpc24xx_irq_set_priority( rtems_vector_number vector, unsigned priority)
     31void lpc24xx_irq_set_priority(rtems_vector_number vector, unsigned priority)
    3232{
    33   if (lpc24xx_irq_is_valid( vector)) {
     33  if (lpc24xx_irq_is_valid(vector)) {
    3434    if (priority > LPC24XX_IRQ_PRIORITY_VALUE_MAX) {
    3535      priority = LPC24XX_IRQ_PRIORITY_VALUE_MAX;
     
    4040}
    4141
    42 unsigned lpc24xx_irq_priority( rtems_vector_number vector)
     42unsigned lpc24xx_irq_get_priority(rtems_vector_number vector)
    4343{
    44   if (lpc24xx_irq_is_valid( vector)) {
     44  if (lpc24xx_irq_is_valid(vector)) {
    4545    return VICVectPriorityBase [vector];
    4646  } else {
     
    4949}
    5050
    51 void bsp_interrupt_dispatch( void)
     51void bsp_interrupt_dispatch(void)
    5252{
    5353  /* Read current vector number */
     
    5858
    5959  /* Dispatch interrupt handlers */
    60   bsp_interrupt_handler_dispatch( vector);
     60  bsp_interrupt_handler_dispatch(vector);
    6161
    6262  /* Restore program status register */
    63   arm_status_restore( psr);
     63  arm_status_restore(psr);
    6464
    6565  /* Acknowledge interrupt */
     
    6767}
    6868
    69 rtems_status_code bsp_interrupt_vector_enable( rtems_vector_number vector)
     69rtems_status_code bsp_interrupt_vector_enable(rtems_vector_number vector)
    7070{
    71   if (lpc24xx_irq_is_valid( vector)) {
     71  if (lpc24xx_irq_is_valid(vector)) {
    7272    VICIntEnable = 1U << vector;
    7373  }
     
    7676}
    7777
    78 rtems_status_code bsp_interrupt_vector_disable( rtems_vector_number vector)
     78rtems_status_code bsp_interrupt_vector_disable(rtems_vector_number vector)
    7979{
    80   if (lpc24xx_irq_is_valid( vector)) {
     80  if (lpc24xx_irq_is_valid(vector)) {
    8181    VICIntEnClear = 1U << vector;
    8282  }
     
    8585}
    8686
    87 /* FIXME */
    88 void arm_exc_interrupt( void);
    89 
    90 rtems_status_code bsp_interrupt_facility_initialize( void)
     87rtems_status_code bsp_interrupt_facility_initialize(void)
    9188{
    9289  volatile uint32_t *addr = VICVectAddrBase;
     
    118115
    119116  /* Install the IRQ exception handler */
    120   _CPU_ISR_install_vector( ARM_EXCEPTION_IRQ, arm_exc_interrupt, NULL);
     117  _CPU_ISR_install_vector(ARM_EXCEPTION_IRQ, arm_exc_interrupt, NULL);
    121118
    122119  return RTEMS_SUCCESSFUL;
    123120}
    124121
    125 void bsp_interrupt_handler_default( rtems_vector_number vector)
     122void bsp_interrupt_handler_default(rtems_vector_number vector)
    126123{
    127   printk( "spurious interrupt: %u\n", vector);
     124  printk("spurious interrupt: %u\n", vector);
    128125}
  • c/src/lib/libbsp/arm/lpc24xx/misc/dma.c

    r9db18dd rc468f18b  
    3434{
    3535  /* Enable module power */
    36   lpc24xx_module_enable(LPC24XX_MODULE_GPDMA, 0, LPC24XX_MODULE_PCLK_DEFAULT);
     36  lpc24xx_module_enable(LPC24XX_MODULE_GPDMA, LPC24XX_MODULE_PCLK_DEFAULT);
    3737
    3838  /* Disable module */
  • c/src/lib/libbsp/arm/lpc24xx/misc/io.c

    r9db18dd rc468f18b  
    3737#define LPC24XX_IO_ALTERNATE_2 0x3U
    3838
    39 #define LPC24XX_IO_ENTRY(mod, idx, cfg, begin_port, begin_index, last_port, last_index, function) \
     39#define LPC24XX_IO_ENTRY(mod, cfg, begin_port, begin_index, last_port, last_index, function) \
    4040  { \
    4141    .module = mod, \
    42     .index = idx, \
    4342    .config = cfg, \
    4443    .pin_begin = LPC24XX_IO_INDEX_BY_PORT(begin_port, begin_index), \
     
    4847
    4948typedef struct {
    50   unsigned module : 5;
    51   unsigned index : 4;
     49  unsigned module : 6;
    5250  unsigned config : 4;
    5351  unsigned pin_begin : 8;
     
    6058static const lpc24xx_io_entry lpc24xx_io_config_table [] = {
    6159  /* UART */
    62   LPC24XX_IO_ENTRY(LPC24XX_MODULE_UART, 0, 0, 0, 2, 0, 3, LPC24XX_IO_ALTERNATE_0),
    63   LPC24XX_IO_ENTRY(LPC24XX_MODULE_UART, 1, 0, 0, 15, 0, 16, LPC24XX_IO_ALTERNATE_0),
    64   LPC24XX_IO_ENTRY(LPC24XX_MODULE_UART, 1, 1, 2, 0, 2, 1, LPC24XX_IO_ALTERNATE_1),
    65   LPC24XX_IO_ENTRY(LPC24XX_MODULE_UART, 1, 2, 3, 16, 3, 17, LPC24XX_IO_ALTERNATE_2),
    66   LPC24XX_IO_ENTRY(LPC24XX_MODULE_UART, 2, 0, 0, 10, 0, 11, LPC24XX_IO_ALTERNATE_0),
    67   LPC24XX_IO_ENTRY(LPC24XX_MODULE_UART, 2, 1, 2, 8, 2, 9, LPC24XX_IO_ALTERNATE_1),
    68   LPC24XX_IO_ENTRY(LPC24XX_MODULE_UART, 2, 2, 4, 22, 4, 23, LPC24XX_IO_ALTERNATE_1),
    69   LPC24XX_IO_ENTRY(LPC24XX_MODULE_UART, 3, 0, 0, 0, 0, 1, LPC24XX_IO_ALTERNATE_1),
    70   LPC24XX_IO_ENTRY(LPC24XX_MODULE_UART, 3, 1, 0, 25, 0, 26, LPC24XX_IO_ALTERNATE_2),
    71   LPC24XX_IO_ENTRY(LPC24XX_MODULE_UART, 3, 2, 4, 28, 4, 29, LPC24XX_IO_ALTERNATE_2),
     60  LPC24XX_IO_ENTRY(LPC24XX_MODULE_UART_0, 0, 0, 2, 0, 3, LPC24XX_IO_ALTERNATE_0),
     61  LPC24XX_IO_ENTRY(LPC24XX_MODULE_UART_1, 0, 0, 15, 0, 16, LPC24XX_IO_ALTERNATE_0),
     62  LPC24XX_IO_ENTRY(LPC24XX_MODULE_UART_1, 1, 2, 0, 2, 1, LPC24XX_IO_ALTERNATE_1),
     63  LPC24XX_IO_ENTRY(LPC24XX_MODULE_UART_1, 2, 3, 16, 3, 17, LPC24XX_IO_ALTERNATE_2),
     64  LPC24XX_IO_ENTRY(LPC24XX_MODULE_UART_2, 0, 0, 10, 0, 11, LPC24XX_IO_ALTERNATE_0),
     65  LPC24XX_IO_ENTRY(LPC24XX_MODULE_UART_2, 1, 2, 8, 2, 9, LPC24XX_IO_ALTERNATE_1),
     66  LPC24XX_IO_ENTRY(LPC24XX_MODULE_UART_2, 2, 4, 22, 4, 23, LPC24XX_IO_ALTERNATE_1),
     67  LPC24XX_IO_ENTRY(LPC24XX_MODULE_UART_3, 0, 0, 0, 0, 1, LPC24XX_IO_ALTERNATE_1),
     68  LPC24XX_IO_ENTRY(LPC24XX_MODULE_UART_3, 1, 0, 25, 0, 26, LPC24XX_IO_ALTERNATE_2),
     69  LPC24XX_IO_ENTRY(LPC24XX_MODULE_UART_3, 2, 4, 28, 4, 29, LPC24XX_IO_ALTERNATE_2),
    7270
    7371  /* Ethernet */
    74   LPC24XX_IO_ENTRY(LPC24XX_MODULE_ETHERNET, 0, 0, 1, 0, 1, 17, LPC24XX_IO_ALTERNATE_0),
    75   LPC24XX_IO_ENTRY(LPC24XX_MODULE_ETHERNET, 0, 1, 1, 0, 1, 1, LPC24XX_IO_ALTERNATE_0),
    76   LPC24XX_IO_ENTRY(LPC24XX_MODULE_ETHERNET, 0, 1, 1, 4, 1, 4, LPC24XX_IO_ALTERNATE_0),
    77   LPC24XX_IO_ENTRY(LPC24XX_MODULE_ETHERNET, 0, 1, 1, 8, 1, 10, LPC24XX_IO_ALTERNATE_0),
    78   LPC24XX_IO_ENTRY(LPC24XX_MODULE_ETHERNET, 0, 1, 1, 14, 1, 17, LPC24XX_IO_ALTERNATE_0),
     72  LPC24XX_IO_ENTRY(LPC24XX_MODULE_ETHERNET, 0, 1, 0, 1, 17, LPC24XX_IO_ALTERNATE_0),
     73  LPC24XX_IO_ENTRY(LPC24XX_MODULE_ETHERNET, 1, 1, 0, 1, 1, LPC24XX_IO_ALTERNATE_0),
     74  LPC24XX_IO_ENTRY(LPC24XX_MODULE_ETHERNET, 1, 1, 4, 1, 4, LPC24XX_IO_ALTERNATE_0),
     75  LPC24XX_IO_ENTRY(LPC24XX_MODULE_ETHERNET, 1, 1, 8, 1, 10, LPC24XX_IO_ALTERNATE_0),
     76  LPC24XX_IO_ENTRY(LPC24XX_MODULE_ETHERNET, 1, 1, 14, 1, 17, LPC24XX_IO_ALTERNATE_0),
    7977
    8078  /* ADC */
    81   LPC24XX_IO_ENTRY(LPC24XX_MODULE_ADC, 0, 0, 0, 12, 0, 13, LPC24XX_IO_ALTERNATE_2),
     79  LPC24XX_IO_ENTRY(LPC24XX_MODULE_ADC, 0, 0, 12, 0, 13, LPC24XX_IO_ALTERNATE_2),
    8280
    8381  /* I2C */
    84   LPC24XX_IO_ENTRY(LPC24XX_MODULE_I2C, 0, 0, 0, 27, 0, 28, LPC24XX_IO_ALTERNATE_0),
    85   LPC24XX_IO_ENTRY(LPC24XX_MODULE_I2C, 1, 0, 0, 0, 0, 1, LPC24XX_IO_ALTERNATE_2),
    86   LPC24XX_IO_ENTRY(LPC24XX_MODULE_I2C, 1, 1, 0, 19, 0, 20, LPC24XX_IO_ALTERNATE_2),
    87   LPC24XX_IO_ENTRY(LPC24XX_MODULE_I2C, 1, 2, 2, 14, 2, 15, LPC24XX_IO_ALTERNATE_2),
    88   LPC24XX_IO_ENTRY(LPC24XX_MODULE_I2C, 2, 0, 0, 10, 0, 11, LPC24XX_IO_ALTERNATE_1),
    89   LPC24XX_IO_ENTRY(LPC24XX_MODULE_I2C, 2, 1, 2, 30, 2, 31, LPC24XX_IO_ALTERNATE_2),
    90   LPC24XX_IO_ENTRY(LPC24XX_MODULE_I2C, 2, 2, 4, 20, 4, 21, LPC24XX_IO_ALTERNATE_1),
     82  LPC24XX_IO_ENTRY(LPC24XX_MODULE_I2C_0, 0, 0, 27, 0, 28, LPC24XX_IO_ALTERNATE_0),
     83  LPC24XX_IO_ENTRY(LPC24XX_MODULE_I2C_1, 0, 0, 0, 0, 1, LPC24XX_IO_ALTERNATE_2),
     84  LPC24XX_IO_ENTRY(LPC24XX_MODULE_I2C_1, 1, 0, 19, 0, 20, LPC24XX_IO_ALTERNATE_2),
     85  LPC24XX_IO_ENTRY(LPC24XX_MODULE_I2C_1, 2, 2, 14, 2, 15, LPC24XX_IO_ALTERNATE_2),
     86  LPC24XX_IO_ENTRY(LPC24XX_MODULE_I2C_2, 0, 0, 10, 0, 11, LPC24XX_IO_ALTERNATE_1),
     87  LPC24XX_IO_ENTRY(LPC24XX_MODULE_I2C_2, 1, 2, 30, 2, 31, LPC24XX_IO_ALTERNATE_2),
     88  LPC24XX_IO_ENTRY(LPC24XX_MODULE_I2C_2, 2, 4, 20, 4, 21, LPC24XX_IO_ALTERNATE_1),
    9189
    9290  /* SSP */
    93   LPC24XX_IO_ENTRY(LPC24XX_MODULE_SSP, 0, 0, 0, 15, 0, 18, LPC24XX_IO_ALTERNATE_1),
    94   LPC24XX_IO_ENTRY(LPC24XX_MODULE_SSP, 0, 1, 1, 20, 0, 21, LPC24XX_IO_ALTERNATE_2),
    95   LPC24XX_IO_ENTRY(LPC24XX_MODULE_SSP, 0, 1, 1, 23, 0, 24, LPC24XX_IO_ALTERNATE_2),
    96   LPC24XX_IO_ENTRY(LPC24XX_MODULE_SSP, 0, 2, 2, 22, 2, 23, LPC24XX_IO_ALTERNATE_2),
    97   LPC24XX_IO_ENTRY(LPC24XX_MODULE_SSP, 0, 2, 2, 26, 2, 27, LPC24XX_IO_ALTERNATE_2),
    98   LPC24XX_IO_ENTRY(LPC24XX_MODULE_SSP, 1, 0, 0, 6, 0, 9, LPC24XX_IO_ALTERNATE_1),
    99   LPC24XX_IO_ENTRY(LPC24XX_MODULE_SSP, 1, 1, 0, 12, 0, 13, LPC24XX_IO_ALTERNATE_1),
    100   LPC24XX_IO_ENTRY(LPC24XX_MODULE_SSP, 1, 1, 0, 14, 0, 14, LPC24XX_IO_ALTERNATE_2),
    101   LPC24XX_IO_ENTRY(LPC24XX_MODULE_SSP, 1, 1, 1, 31, 1, 31, LPC24XX_IO_ALTERNATE_1),
    102   LPC24XX_IO_ENTRY(LPC24XX_MODULE_SSP, 1, 2, 4, 20, 4, 23, LPC24XX_IO_ALTERNATE_2),
     91  LPC24XX_IO_ENTRY(LPC24XX_MODULE_SSP_0, 0, 0, 15, 0, 18, LPC24XX_IO_ALTERNATE_1),
     92  LPC24XX_IO_ENTRY(LPC24XX_MODULE_SSP_0, 1, 1, 20, 0, 21, LPC24XX_IO_ALTERNATE_2),
     93  LPC24XX_IO_ENTRY(LPC24XX_MODULE_SSP_0, 1, 1, 23, 0, 24, LPC24XX_IO_ALTERNATE_2),
     94  LPC24XX_IO_ENTRY(LPC24XX_MODULE_SSP_0, 2, 2, 22, 2, 23, LPC24XX_IO_ALTERNATE_2),
     95  LPC24XX_IO_ENTRY(LPC24XX_MODULE_SSP_0, 2, 2, 26, 2, 27, LPC24XX_IO_ALTERNATE_2),
     96  LPC24XX_IO_ENTRY(LPC24XX_MODULE_SSP_1, 0, 0, 6, 0, 9, LPC24XX_IO_ALTERNATE_1),
     97  LPC24XX_IO_ENTRY(LPC24XX_MODULE_SSP_1, 1, 0, 12, 0, 13, LPC24XX_IO_ALTERNATE_1),
     98  LPC24XX_IO_ENTRY(LPC24XX_MODULE_SSP_1, 1, 0, 14, 0, 14, LPC24XX_IO_ALTERNATE_2),
     99  LPC24XX_IO_ENTRY(LPC24XX_MODULE_SSP_1, 1, 1, 31, 1, 31, LPC24XX_IO_ALTERNATE_1),
     100  LPC24XX_IO_ENTRY(LPC24XX_MODULE_SSP_1, 2, 4, 20, 4, 23, LPC24XX_IO_ALTERNATE_2),
    103101
    104102  /* USB */
    105   LPC24XX_IO_ENTRY(LPC24XX_MODULE_USB, 0, 0, 0, 29, 0, 30, LPC24XX_IO_ALTERNATE_0),
    106   LPC24XX_IO_ENTRY(LPC24XX_MODULE_USB, 0, 0, 1, 19, 1, 19, LPC24XX_IO_ALTERNATE_1),
     103  LPC24XX_IO_ENTRY(LPC24XX_MODULE_USB, 0, 0, 29, 0, 30, LPC24XX_IO_ALTERNATE_0),
     104  LPC24XX_IO_ENTRY(LPC24XX_MODULE_USB, 0, 1, 19, 1, 19, LPC24XX_IO_ALTERNATE_1),
    107105
    108106  /* Terminate */
    109   LPC24XX_IO_ENTRY(LPC24XX_MODULE_COUNT, 0, 0, 0, 0, 0, 0, 0),
     107  LPC24XX_IO_ENTRY(LPC24XX_MODULE_COUNT, 0, 0, 0, 0, 0, 0),
    110108};
    111109
    112110static rtems_status_code lpc24xx_io_iterate(
    113111  lpc24xx_module module,
    114   unsigned index,
    115112  unsigned config,
    116113  lpc24xx_io_iterate_routine routine
     
    121118
    122119  while (e->module != LPC24XX_MODULE_COUNT) {
    123     if (e->module == module && e->index == index && e->config == config) {
     120    if (e->module == module && e->config == config) {
    124121      unsigned pin = e->pin_begin;
    125122      unsigned last = e->pin_last;
     
    173170rtems_status_code lpc24xx_io_config(
    174171  lpc24xx_module module,
    175   unsigned index,
    176172  unsigned config
    177173)
    178174{
    179   return lpc24xx_io_iterate(module, index, config, lpc24xx_io_do_config);
     175  return lpc24xx_io_iterate(module, config, lpc24xx_io_do_config);
    180176}
    181177
    182178rtems_status_code lpc24xx_io_release(
    183179  lpc24xx_module module,
    184   unsigned index,
    185180  unsigned config
    186181)
    187182{
    188   return lpc24xx_io_iterate(module, index, config, lpc24xx_io_do_release);
     183  return lpc24xx_io_iterate(module, config, lpc24xx_io_do_release);
    189184}
    190185
     
    240235}
    241236
     237#define LPC24XX_MODULE_ENTRY(mod, pwr, clk, idx) \
     238  [mod] = { \
     239    .power = pwr, \
     240    .clock = clk, \
     241    .index = idx \
     242  }
     243
     244typedef struct {
     245  unsigned char power : 1;
     246  unsigned char clock : 1;
     247  unsigned char index : 6;
     248} lpc24xx_module_entry;
     249
     250static const lpc24xx_module_entry lpc24xx_module_table [] = {
     251  LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_ACF, 0, 1, 15),
     252  LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_ADC, 1, 1, 12),
     253  LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_BAT_RAM, 0, 1, 16),
     254  LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_CAN_0, 1, 1, 13),
     255  LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_CAN_1, 1, 1, 14),
     256  LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_DAC, 0, 1, 11),
     257  LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_EMC, 1, 0, 11),
     258  LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_ETHERNET, 1, 0, 30),
     259  LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_GPDMA, 1, 1, 29),
     260  LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_GPIO, 0, 1, 17),
     261  LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_I2C_0, 1, 1, 7),
     262  LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_I2C_1, 1, 1, 19),
     263  LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_I2C_2, 1, 1, 26),
     264  LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_I2S, 1, 1, 27),
     265  LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_LCD, 1, 1, 20),
     266  LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_MCI, 1, 1, 28),
     267  LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_PCB, 0, 1, 18),
     268  LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_PWM_0, 1, 1, 5),
     269  LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_PWM_1, 1, 1, 6),
     270  LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_RTC, 1, 1, 9),
     271  LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_SPI, 1, 1, 8),
     272  LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_SSP_0, 1, 1, 21),
     273  LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_SSP_1, 1, 1, 10),
     274  LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_SYSCON, 0, 1, 30),
     275  LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_TIMER_0, 1, 1, 1),
     276  LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_TIMER_1, 1, 1, 2),
     277  LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_TIMER_2, 1, 1, 22),
     278  LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_TIMER_3, 1, 1, 23),
     279  LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_UART_0, 1, 1, 3),
     280  LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_UART_1, 1, 1, 4),
     281  LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_UART_2, 1, 1, 24),
     282  LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_UART_3, 1, 1, 25),
     283  LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_USB, 1, 0, 31),
     284  LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_WDT, 0, 1, 0)
     285};
     286
    242287static rtems_status_code lpc24xx_module_do_enable(
    243288  lpc24xx_module module,
    244   unsigned index,
    245289  lpc24xx_module_clock clock,
    246290  bool enable
    247291)
    248292{
    249   const unsigned NO_POWER = 32U;
    250   const unsigned INVALID = 33U;
    251   unsigned power_bit = INVALID;
    252   unsigned clock_shift = INVALID;
    253 
    254   /* Check clock value */
     293  rtems_interrupt_level level;
     294  bool has_power = false;
     295  bool has_clock = false;
     296  unsigned index = 0;
     297
     298  if ((unsigned) module >= LPC24XX_MODULE_COUNT) {
     299      return RTEMS_INVALID_ID;
     300  }
     301
    255302  if ((clock & ~LPC24XX_MODULE_CLOCK_MASK) != 0U) {
    256303    return RTEMS_INVALID_NUMBER;
    257304  }
    258305
    259   /* Get power bit */
    260   switch (module) {
    261     case LPC24XX_MODULE_ACF:
    262       if (index == 0) {
    263         power_bit = NO_POWER;
    264         clock_shift = 30U;
    265       }
    266       break;
    267     case LPC24XX_MODULE_ADC:
    268       if (index == 0) {
    269         power_bit = 12U;
    270       }
    271       break;
    272     case LPC24XX_MODULE_BAT_RAM:
    273       if (index == 0) {
    274         power_bit = NO_POWER;
    275         clock_shift = 32U;
    276       }
    277       break;
    278     case LPC24XX_MODULE_CAN:
    279       if (index < 2) {
    280         power_bit = 13U + index;
    281       }
    282       break;
    283     case LPC24XX_MODULE_DAC:
    284       if (index == 0) {
    285         power_bit = NO_POWER;
    286         clock_shift = 22U;
    287       }
    288       break;
    289     case LPC24XX_MODULE_EMC:
    290       if (index == 0) {
    291         power_bit = 11U;
    292       }
    293       break;
    294     case LPC24XX_MODULE_ETHERNET:
    295       if (index == 0) {
    296         power_bit = 30U;
    297       }
    298       break;
    299     case LPC24XX_MODULE_GPDMA:
    300       if (index == 0) {
    301         power_bit = 29U;
    302       }
    303       break;
    304     case LPC24XX_MODULE_GPIO:
    305       if (index == 0) {
    306         power_bit = NO_POWER;
    307         clock_shift = 34U;
    308       }
    309       break;
    310     case LPC24XX_MODULE_I2C:
    311       switch (index) {
    312         case 0U:
    313           power_bit = 7U;
    314           break;
    315         case 1U:
    316           power_bit = 19U;
    317           break;
    318         case 2U:
    319           power_bit = 26U;
    320           break;
    321       }
    322       break;
    323     case LPC24XX_MODULE_I2S:
    324       if (index == 0) {
    325         power_bit = 27U;
    326       }
    327       break;
    328     case LPC24XX_MODULE_LCD:
    329       if (index == 0) {
    330         power_bit = 20U;
    331       }
    332       break;
    333     case LPC24XX_MODULE_MCI:
    334       if (index == 0) {
    335         power_bit = 28U;
    336       }
    337       break;
    338     case LPC24XX_MODULE_PCB:
    339       if (index == 0) {
    340         power_bit = NO_POWER;
    341         clock_shift = 36U;
    342       }
    343       break;
    344     case LPC24XX_MODULE_PWM:
    345       if (index < 2) {
    346         power_bit = 5U + index;
    347       }
    348       break;
    349     case LPC24XX_MODULE_RTC:
    350       if (index == 0) {
    351         power_bit = 9U;
    352       }
    353       break;
    354     case LPC24XX_MODULE_SPI:
    355       if (index == 0) {
    356         power_bit = 8U;
    357       }
    358       break;
    359     case LPC24XX_MODULE_SSP:
    360       switch (index) {
    361         case 0U:
    362           power_bit = 21U;
    363           break;
    364         case 1U:
    365           power_bit = 10U;
    366           break;
    367       }
    368       break;
    369     case LPC24XX_MODULE_SYSCON:
    370       if (index == 0) {
    371         power_bit = NO_POWER;
    372         clock_shift = 60U;
    373       }
    374       break;
    375     case LPC24XX_MODULE_TIMER:
    376       if (index < 2) {
    377         power_bit = 1U + index;
    378       } else if (index < 4) {
    379         power_bit = 20U + index;
    380       }
    381       break;
    382     case LPC24XX_MODULE_UART:
    383       if (index < 2) {
    384         power_bit = 3U + index;
    385       } else if (index < 4) {
    386         power_bit = 22U + index;
    387       }
    388       break;
    389     case LPC24XX_MODULE_USB:
    390       if (index == 0) {
    391         power_bit = 31U;
    392       }
    393       break;
    394     case LPC24XX_MODULE_WDT:
    395       if (index == 0) {
    396         power_bit = NO_POWER;
    397         clock_shift = 0U;
    398       }
    399       break;
    400     default:
    401       return RTEMS_INVALID_ID;
    402   }
    403 
    404   /* Check power bit */
    405   if (power_bit == INVALID) {
    406     return RTEMS_INVALID_ID;
    407   }
    408 
    409   /* Get clock shift */
    410   if (clock_shift == INVALID) {
    411     clock_shift = power_bit << 1U;
    412   }
     306  has_power = lpc24xx_module_table [module].power;
     307  has_clock = lpc24xx_module_table [module].clock;
     308  index = lpc24xx_module_table [module].index;
    413309
    414310  /* Enable or disable module */
    415311  if (enable) {
    416     rtems_interrupt_level level;
    417 
    418     rtems_interrupt_disable(level);
    419     PCONP |= 1U << power_bit;
    420     rtems_interrupt_enable(level);
     312    if (has_power) {
     313      rtems_interrupt_disable(level);
     314      PCONP |= 1U << index;
     315      rtems_interrupt_enable(level);
     316    }
    421317
    422318    if (module != LPC24XX_MODULE_USB) {
    423       rtems_interrupt_disable(level);
    424       if (clock_shift < 32U) {
    425         PCLKSEL0 = (PCLKSEL0 & ~(LPC24XX_MODULE_CLOCK_MASK << clock_shift))
    426             | (clock << clock_shift);
    427       } else {
    428         clock_shift -= 32U;
    429         PCLKSEL1 = (PCLKSEL1 & ~(LPC24XX_MODULE_CLOCK_MASK << clock_shift))
    430             | (clock << clock_shift);
     319      if (has_clock) {
     320        unsigned clock_shift = 2U * index;
     321
     322        rtems_interrupt_disable(level);
     323        if (clock_shift < 32U) {
     324          PCLKSEL0 = (PCLKSEL0 & ~(LPC24XX_MODULE_CLOCK_MASK << clock_shift))
     325              | (clock << clock_shift);
     326        } else {
     327          clock_shift -= 32U;
     328          PCLKSEL1 = (PCLKSEL1 & ~(LPC24XX_MODULE_CLOCK_MASK << clock_shift))
     329              | (clock << clock_shift);
     330        }
     331        rtems_interrupt_enable(level);
    431332      }
    432       rtems_interrupt_enable(level);
    433333    } else {
    434334      unsigned pllclk = lpc24xx_pllclk();
     
    442342    }
    443343  } else {
    444     rtems_interrupt_level level;
    445 
    446     rtems_interrupt_disable(level);
    447     PCONP &= ~(1U << power_bit);
    448     rtems_interrupt_enable(level);
     344    if (has_power) {
     345      rtems_interrupt_disable(level);
     346      PCONP &= ~(1U << index);
     347      rtems_interrupt_enable(level);
     348    }
    449349  }
    450350
     
    454354rtems_status_code lpc24xx_module_enable(
    455355  lpc24xx_module module,
    456   unsigned index,
    457356  lpc24xx_module_clock clock
    458357)
    459358{
    460   return lpc24xx_module_do_enable(module, index, clock, true);
     359  return lpc24xx_module_do_enable(module, clock, true);
    461360}
    462361
    463362rtems_status_code lpc24xx_module_disable(
    464   lpc24xx_module module,
    465   unsigned index
    466 )
    467 {
    468   return lpc24xx_module_do_enable(module, index, 0U, false);
    469 }
     363  lpc24xx_module module
     364)
     365{
     366  return lpc24xx_module_do_enable(module, 0U, false);
     367}
  • c/src/lib/libbsp/arm/lpc24xx/misc/timer.c

    r9db18dd rc468f18b  
    5050}
    5151
    52 void benchmark_timer_disable_subtracting_average_overhead( bool find_average_overhead )
     52void benchmark_timer_disable_subtracting_average_overhead(bool find_average_overhead )
    5353{
    5454  benchmark_timer_find_average_overhead = find_average_overhead;
  • c/src/lib/libbsp/arm/lpc24xx/network/network.c

    r9db18dd rc468f18b  
    900900    lpc24xx_module_enable(
    901901      LPC24XX_MODULE_ETHERNET,
    902       0,
    903902      LPC24XX_MODULE_PCLK_DEFAULT
    904903    );
     
    906905    /* Module IO configuration */
    907906    #ifdef LPC24XX_ETHERNET_RMII
    908         lpc24xx_io_config(LPC24XX_MODULE_ETHERNET, 0, 0);
     907        lpc24xx_io_config(LPC24XX_MODULE_ETHERNET, 0);
    909908    #else
    910         lpc24xx_io_config(LPC24XX_MODULE_ETHERNET, 0, 1);
     909        lpc24xx_io_config(LPC24XX_MODULE_ETHERNET, 1);
    911910    #endif
    912911
  • c/src/lib/libbsp/arm/lpc24xx/preinstall.am

    r9db18dd rc468f18b  
    8282PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/start.h
    8383
     84$(PROJECT_INCLUDE)/bsp/lpc-timer.h: ../shared/lpc/include/lpc-timer.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     85        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/lpc-timer.h
     86PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/lpc-timer.h
     87
    8488$(PROJECT_INCLUDE)/bsp/irq-config.h: include/irq-config.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    8589        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-config.h
     
    114118PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/io.h
    115119
     120$(PROJECT_INCLUDE)/bsp/lpc-clock-config.h: include/lpc-clock-config.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     121        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/lpc-clock-config.h
     122PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/lpc-clock-config.h
     123
    116124$(PROJECT_INCLUDE)/tm27.h: ../../shared/include/tm27.h $(PROJECT_INCLUDE)/$(dirstamp)
    117125        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/tm27.h
  • c/src/lib/libbsp/arm/lpc24xx/rtc/rtc-config.c

    r9db18dd rc468f18b  
    2626#define LPC24XX_RTC_NUMBER 1
    2727
    28 static void lpc24xx_rtc_initialize( int minor)
     28static void lpc24xx_rtc_initialize(int minor)
    2929{
    3030  /* Enable module power */
    31   lpc24xx_module_enable( LPC24XX_MODULE_RTC, 0, LPC24XX_MODULE_PCLK_DEFAULT);
     31  lpc24xx_module_enable(LPC24XX_MODULE_RTC, LPC24XX_MODULE_PCLK_DEFAULT);
    3232
    3333  /* Enable the RTC and use external clock */
     
    4343}
    4444
    45 static int lpc24xx_rtc_get_time( int minor, rtems_time_of_day *tod)
     45static int lpc24xx_rtc_get_time(int minor, rtems_time_of_day *tod)
    4646{
    4747  tod->ticks = 0;
     
    5656}
    5757
    58 static int lpc24xx_rtc_set_time( int minor, const rtems_time_of_day *tod)
     58static int lpc24xx_rtc_set_time(int minor, const rtems_time_of_day *tod)
    5959{
    6060  RTC_SEC = tod->second;
     
    6868}
    6969
    70 static bool lpc24xx_rtc_probe( int minor)
     70static bool lpc24xx_rtc_probe(int minor)
    7171{
    7272  return true;
  • c/src/lib/libbsp/arm/lpc24xx/startup/bspreset.c

    r9db18dd rc468f18b  
    2424#include <bsp/lpc24xx.h>
    2525
    26 void bsp_reset( void)
     26void bsp_reset(void)
    2727{
    2828  rtems_interrupt_level level;
    2929
    30   rtems_interrupt_disable( level);
     30  rtems_interrupt_disable(level);
    3131
    3232  /* Trigger watchdog reset */
  • c/src/lib/libbsp/arm/lpc24xx/startup/bspstart.c

    r9db18dd rc468f18b  
    3434{
    3535  /* Initialize Timer 1 */
    36   lpc24xx_module_enable(LPC24XX_MODULE_TIMER, 1, LPC24XX_MODULE_CCLK);
     36  lpc24xx_module_enable(LPC24XX_MODULE_TIMER_1, LPC24XX_MODULE_CCLK);
    3737
    3838  /* Initialize standard timer */
     
    4141  /* Initialize console */
    4242  #ifdef LPC24XX_CONFIG_CONSOLE
    43     lpc24xx_module_enable(LPC24XX_MODULE_UART, 0, LPC24XX_MODULE_CCLK);
    44     lpc24xx_io_config(LPC24XX_MODULE_UART, 0, LPC24XX_CONFIG_CONSOLE);
     43    lpc24xx_module_enable(LPC24XX_MODULE_UART_0, LPC24XX_MODULE_CCLK);
     44    lpc24xx_io_config(LPC24XX_MODULE_UART_0, LPC24XX_CONFIG_CONSOLE);
    4545    U0LCR = 0;
    4646    U0IER = 0;
     
    6161
    6262  /* Task stacks */
    63   bsp_stack_initialize(
    64     bsp_section_stack_begin,
    65     (uintptr_t) bsp_section_stack_size
    66   );
     63  #ifdef LPC24XX_SPECIAL_TASK_STACKS_SUPPORT
     64    bsp_stack_initialize(
     65      bsp_section_stack_begin,
     66      (uintptr_t) bsp_section_stack_size
     67    );
     68  #endif
    6769
    6870  /* UART configurations */
    6971  #ifdef LPC24XX_CONFIG_UART_1
    70     lpc24xx_module_enable(LPC24XX_MODULE_UART, 1, LPC24XX_MODULE_CCLK);
    71     lpc24xx_io_config(LPC24XX_MODULE_UART, 1, LPC24XX_CONFIG_UART_1);
     72    lpc24xx_module_enable(LPC24XX_MODULE_UART_1, LPC24XX_MODULE_CCLK);
     73    lpc24xx_io_config(LPC24XX_MODULE_UART_1, LPC24XX_CONFIG_UART_1);
    7274  #endif
    7375  #ifdef LPC24XX_CONFIG_UART_2
    74     lpc24xx_module_enable(LPC24XX_MODULE_UART, 2, LPC24XX_MODULE_CCLK);
    75     lpc24xx_io_config(LPC24XX_MODULE_UART, 2, LPC24XX_CONFIG_UART_2);
     76    lpc24xx_module_enable(LPC24XX_MODULE_UART_2, LPC24XX_MODULE_CCLK);
     77    lpc24xx_io_config(LPC24XX_MODULE_UART_2, LPC24XX_CONFIG_UART_2);
    7678  #endif
    7779  #ifdef LPC24XX_CONFIG_UART_3
    78     lpc24xx_module_enable(LPC24XX_MODULE_UART, 3, LPC24XX_MODULE_CCLK);
    79     lpc24xx_io_config(LPC24XX_MODULE_UART, 3, LPC24XX_CONFIG_UART_3);
     80    lpc24xx_module_enable(LPC24XX_MODULE_UART_3, LPC24XX_MODULE_CCLK);
     81    lpc24xx_io_config(LPC24XX_MODULE_UART_3, LPC24XX_CONFIG_UART_3);
    8082  #endif
    8183}
  • c/src/lib/libbsp/arm/lpc24xx/startup/bspstarthooks.c

    r9db18dd rc468f18b  
    2727#include <bsp/linker-symbols.h>
    2828
     29#define BSP_START_SECTION __attribute__((section(".bsp_start")))
     30
    2931#ifdef LPC24XX_EMC_MICRON
    30   static void __attribute__((section(".bsp_start"))) lpc24xx_ram_test_32(void)
     32  static void BSP_START_SECTION lpc24xx_ram_test_32(void)
    3133  {
    3234    #ifdef LPC24XX_EMC_TEST
     
    5254  }
    5355
    54   static void __attribute__((section(".bsp_start"))) lpc24xx_cpu_delay(
     56  static void BSP_START_SECTION lpc24xx_cpu_delay(
    5557    unsigned ticks
    5658  )
     
    7072 * @brief EMC initialization hook 0.
    7173 */
    72 static void __attribute__((section(".bsp_start"))) lpc24xx_init_emc_0(void)
     74static void BSP_START_SECTION lpc24xx_init_emc_0(void)
    7375{
    7476  #ifdef LPC24XX_EMC_NUMONYX
     
    132134 * @brief EMC initialization hook 1.
    133135 */
    134 static void __attribute__((section(".bsp_start"))) lpc24xx_init_emc_1(void)
     136static void BSP_START_SECTION lpc24xx_init_emc_1(void)
    135137{
    136138  /* Use normal memory map */
     
    235237}
    236238
    237 static void __attribute__((section(".bsp_start"))) lpc24xx_pll_config(
     239static void BSP_START_SECTION lpc24xx_pll_config(
    238240  uint32_t val
    239241)
     
    258260 * from the PLL output.
    259261 */
    260 static void __attribute__((section(".bsp_start"))) lpc24xx_set_pll(
     262static void BSP_START_SECTION lpc24xx_set_pll(
    261263  unsigned clksrc,
    262264  unsigned nsel,
     
    314316}
    315317
    316 static void __attribute__((section(".bsp_start"))) lpc24xx_init_pll(void)
     318static void BSP_START_SECTION lpc24xx_init_pll(void)
    317319{
    318320  /* Enable main oscillator */
     
    328330}
    329331
    330 static void __attribute__((section(".bsp_start"))) lpc24xx_clear_bss(void)
     332static void BSP_START_SECTION lpc24xx_clear_bss(void)
    331333{
    332334  const int *end = (const int *) bsp_section_bss_end;
     
    340342}
    341343
    342 void __attribute__((section(".bsp_start"))) bsp_start_hook_0(void)
     344void BSP_START_SECTION bsp_start_hook_0(void)
    343345{
    344346  /* Initialize PLL */
     
    349351}
    350352
    351 void __attribute__((section(".bsp_start"))) bsp_start_hook_1(void)
     353void BSP_START_SECTION bsp_start_hook_1(void)
    352354{
    353355  /* Re-map interrupt vectors to internal RAM */
  • c/src/lib/libbsp/arm/lpc24xx/startup/linkcmds.lpc24xx_ea

    r9db18dd rc468f18b  
    2222 * <table>
    2323 *   <tr><th>Section Name</th><th>Section Runtime Region</th><th>Section Load Region</th></tr>
    24  *   <tr><td>.start</td><td>RAM_EXT</td><td>RAM_EXT</td></tr>
     24 *   <tr><td>.start</td><td>RAM_EXT</td><td></td></tr>
    2525 *   <tr><td>.vector</td><td>RAM_INT</td><td></td></tr>
    2626 *   <tr><td>.text</td><td>RAM_EXT</td><td>RAM_EXT</td></tr>
  • c/src/lib/libbsp/arm/lpc24xx/startup/linkcmds.lpc24xx_ncs_ram

    r9db18dd rc468f18b  
    2222 * <table>
    2323 *   <tr><th>Section Name</th><th>Section Runtime Region</th><th>Section Load Region</th></tr>
    24  *   <tr><td>.start</td><td>RAM_EXT</td><td>RAM_EXT</td></tr>
     24 *   <tr><td>.start</td><td>RAM_EXT</td><td></td></tr>
    2525 *   <tr><td>.vector</td><td>RAM_INT</td><td></td></tr>
    2626 *   <tr><td>.text</td><td>RAM_EXT</td><td>RAM_EXT</td></tr>
  • c/src/lib/libbsp/arm/lpc24xx/startup/linkcmds.lpc24xx_ncs_rom_ext

    r9db18dd rc468f18b  
    2424 * <table>
    2525 *   <tr><th>Section Name</th><th>Section Runtime Region</th><th>Section Load Region</th></tr>
    26  *   <tr><td>.start</td><td>ROM_BOOT</td><td>ROM_BOOT</td></tr>
     26 *   <tr><td>.start</td><td>ROM_BOOT</td><td></td></tr>
    2727 *   <tr><td>.vector</td><td>RAM_INT</td><td></td></tr>
    2828 *   <tr><td>.text</td><td>RAM_EXT</td><td>ROM_EXT</td></tr>
  • c/src/lib/libbsp/arm/lpc24xx/startup/linkcmds.lpc24xx_ncs_rom_int

    r9db18dd rc468f18b  
    2424 * <table>
    2525 *   <tr><th>Section Name</th><th>Section Runtime Region</th><th>Section Load Region</th></tr>
    26  *   <tr><td>.start</td><td>ROM_INT</td><td>ROM_INT</td></tr>
     26 *   <tr><td>.start</td><td>ROM_INT</td><td></td></tr>
    2727 *   <tr><td>.vector</td><td>RAM_VEC</td><td></td></tr>
    2828 *   <tr><td>.text</td><td>ROM_INT</td><td>ROM_INT</td></tr>
  • c/src/lib/libbsp/arm/shared/include/linker-symbols.h

    r9db18dd rc468f18b  
    2222#ifndef LIBBSP_ARM_SHARED_LINKER_SYMBOLS_H
    2323#define LIBBSP_ARM_SHARED_LINKER_SYMBOLS_H
     24
     25#ifdef __cplusplus
     26extern "C" {
     27#endif /* __cplusplus */
    2428
    2529/**
     
    101105/** @} */
    102106
     107#ifdef __cplusplus
     108}
     109#endif /* __cplusplus */
     110
    103111#endif /* LIBBSP_ARM_SHARED_LINKER_SYMBOLS_H */
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