Changeset c37807e9 in rtems


Ignore:
Timestamp:
Dec 21, 2018, 10:57:26 AM (6 months ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
master
Children:
8b59916
Parents:
41a557bc
git-author:
Sebastian Huber <sebastian.huber@…> (12/21/18 10:57:26)
git-committer:
Sebastian Huber <sebastian.huber@…> (12/21/18 10:57:49)
Message:

bsps/arm: Add cache size support for CP15

File:
1 edited

Legend:

Unmodified
Added
Removed
  • bsps/arm/shared/cache/cache-cp15.c

    r41a557bc rc37807e9  
    2929
    3030#define CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS
     31
     32#define CPU_CACHE_SUPPORT_PROVIDES_CACHE_SIZE_FUNCTIONS
    3133
    3234#if __ARM_ARCH >= 7 && (__ARM_ARCH_PROFILE == 65 || __ARM_ARCH_PROFILE == 82)
     
    181183}
    182184
     185static inline size_t arm_cp15_get_cache_size(
     186  uint32_t level,
     187  uint32_t which
     188)
     189{
     190  uint32_t clidr;
     191  uint32_t loc;
     192  uint32_t ccsidr;
     193
     194  clidr = arm_cp15_get_cache_level_id();
     195  loc = arm_clidr_get_level_of_coherency(clidr);
     196
     197  if (level >= loc) {
     198    return 0;
     199  }
     200
     201  if (level == 0) {
     202    level = loc - 1;
     203  }
     204
     205  ccsidr = arm_cp15_get_cache_size_id_for_level(
     206    ARM_CP15_CACHE_CSS_LEVEL(level) | which
     207  );
     208
     209  return (1U << arm_ccsidr_get_line_power(ccsidr))
     210    * arm_ccsidr_get_associativity(ccsidr)
     211    * arm_ccsidr_get_num_sets(ccsidr);
     212}
     213
     214static inline size_t _CPU_cache_get_data_cache_size(uint32_t level)
     215{
     216  return arm_cp15_get_cache_size(level, ARM_CP15_CACHE_CSS_ID_DATA);
     217}
     218
     219static inline size_t _CPU_cache_get_instruction_cache_size(uint32_t level)
     220{
     221  return arm_cp15_get_cache_size(level, ARM_CP15_CACHE_CSS_ID_INSTRUCTION);
     222}
     223
    183224#include "../../shared/cache/cacheimpl.h"
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