Index: cpukit/score/cpu/arm/ChangeLog
===================================================================
--- cpukit/score/cpu/arm/ChangeLog	(revision e6aeabd8dcc7c34a66bd2b688f836be2eb847111)
+++ cpukit/score/cpu/arm/ChangeLog	(revision c346f33d6df5aba8e1ce76d61a2357529ab6e353)
@@ -1,2 +1,6 @@
+2004-03-30	Ralf Corsepius <ralf_corsepius@rtems.org>
+
+	* cpu.c, rtems/score/cpu.h: Convert to using c99 fixed size types.
+
 2004-03-29	Ralf Corsepius <ralf_corsepius@rtems.org>
 
Index: cpukit/score/cpu/arm/cpu.c
===================================================================
--- cpukit/score/cpu/arm/cpu.c	(revision e6aeabd8dcc7c34a66bd2b688f836be2eb847111)
+++ cpukit/score/cpu/arm/cpu.c	(revision c346f33d6df5aba8e1ce76d61a2357529ab6e353)
@@ -33,6 +33,6 @@
  */
 
-unsigned32 g_data_abort_cnt = 0;
-unsigned32 g_data_abort_insn_list[1024];
+uint32_t   g_data_abort_cnt = 0;
+uint32_t   g_data_abort_insn_list[1024];
 
 void _CPU_Initialize(
@@ -49,7 +49,7 @@
  */
  
-unsigned32 _CPU_ISR_Get_level( void )
-{
-    unsigned32 reg = 0; /* to avoid warning */
+uint32_t   _CPU_ISR_Get_level( void )
+{
+    uint32_t   reg = 0; /* to avoid warning */
     
     asm volatile ("mrs  %0, cpsr \n"           \
@@ -81,5 +81,5 @@
  */
 void _CPU_ISR_install_vector(
-  unsigned32  vector,
+  uint32_t    vector,
   proc_ptr    new_handler,
   proc_ptr   *old_handler
@@ -99,13 +99,13 @@
 void _CPU_Context_Initialize(
   Context_Control  *the_context,
-  unsigned32       *stack_base,
-  unsigned32        size,
-  unsigned32        new_level,
+  uint32_t         *stack_base,
+  uint32_t          size,
+  uint32_t          new_level,
   void             *entry_point,
   boolean           is_fp
 )
 {
-    the_context->register_sp = (unsigned32)stack_base + size ;
-    the_context->register_lr = (unsigned32)entry_point;
+    the_context->register_sp = (uint32_t  )stack_base + size ;
+    the_context->register_lr = (uint32_t  )entry_point;
     the_context->register_cpsr = new_level | 0x13;
 }
@@ -218,6 +218,6 @@
 #define GET_I(x)              ((x & 0x02000000) >> 25)
 
-#define GET_REG(r, ctx)      (((unsigned32 *)ctx)[r])
-#define SET_REG(r, ctx, v)   (((unsigned32 *)ctx)[r] = v)
+#define GET_REG(r, ctx)      (((uint32_t   *)ctx)[r])
+#define SET_REG(r, ctx, v)   (((uint32_t   *)ctx)[r] = v)
 #define GET_OFFSET(insn)     (insn & 0xfff)
 
@@ -229,15 +229,15 @@
  */
 
-void do_data_abort(unsigned32 insn, unsigned32 spsr, 
+void do_data_abort(uint32_t   insn, uint32_t   spsr, 
                    CPU_Exception_frame *ctx)
 {
-    unsigned8  decode;
-    unsigned8  insn_type;
-
-    unsigned32 rn;
-    unsigned32 rd;
-
-    unsigned8  *src_addr;
-    unsigned32  tmp;
+    uint8_t    decode;
+    uint8_t    insn_type;
+
+    uint32_t   rn;
+    uint32_t   rd;
+
+    uint8_t    *src_addr;
+    uint32_t    tmp;
 
     g_data_abort_insn_list[g_data_abort_cnt & 0x3ff] = ctx->register_lr - 8;
@@ -282,5 +282,5 @@
                 break;
             case 0x10:  /* P=1, W=0 -> base not updated */
-                src_addr = (unsigned8 *)GET_REG(rn, ctx);
+                src_addr = (uint8_t   *)GET_REG(rn, ctx);
                 if (GET_U(insn) == 0) {
                     src_addr -= GET_OFFSET(insn);
Index: cpukit/score/cpu/arm/rtems/score/cpu.h
===================================================================
--- cpukit/score/cpu/arm/rtems/score/cpu.h	(revision e6aeabd8dcc7c34a66bd2b688f836be2eb847111)
+++ cpukit/score/cpu/arm/rtems/score/cpu.h	(revision c346f33d6df5aba8e1ce76d61a2357529ab6e353)
@@ -335,16 +335,16 @@
  */
 typedef struct {
-    unsigned32 register_cpsr;
-    unsigned32 register_r4;
-    unsigned32 register_r5;
-    unsigned32 register_r6;
-    unsigned32 register_r7;
-    unsigned32 register_r8;
-    unsigned32 register_r9;
-    unsigned32 register_r10;
-    unsigned32 register_fp;
-    unsigned32 register_sp;
-    unsigned32 register_lr;
-    unsigned32 register_pc;
+    uint32_t   register_cpsr;
+    uint32_t   register_r4;
+    uint32_t   register_r5;
+    uint32_t   register_r6;
+    uint32_t   register_r7;
+    uint32_t   register_r8;
+    uint32_t   register_r9;
+    uint32_t   register_r10;
+    uint32_t   register_fp;
+    uint32_t   register_sp;
+    uint32_t   register_lr;
+    uint32_t   register_pc;
 } Context_Control;
 
@@ -354,10 +354,10 @@
 
 typedef struct {
-    unsigned32 register_r0;
-    unsigned32 register_r1;
-    unsigned32 register_r2;
-    unsigned32 register_r3;
-    unsigned32 register_ip;
-    unsigned32 register_lr;
+    uint32_t   register_r0;
+    uint32_t   register_r1;
+    uint32_t   register_r2;
+    uint32_t   register_r3;
+    uint32_t   register_ip;
+    uint32_t   register_lr;
 } CPU_Exception_frame;
 
@@ -385,8 +385,8 @@
   void       (*idle_task)( void );
   boolean      do_zero_of_workspace;
-  unsigned32   idle_task_stack_size;
-  unsigned32   interrupt_stack_size;
-  unsigned32   extra_mpci_receive_server_stack;
-  void *     (*stack_allocate_hook)( unsigned32 );
+  uint32_t     idle_task_stack_size;
+  uint32_t     interrupt_stack_size;
+  uint32_t     extra_mpci_receive_server_stack;
+  void *     (*stack_allocate_hook)( uint32_t   );
   void       (*stack_free_hook)( void* );
   /* end of fields required on all CPUs */
@@ -577,5 +577,5 @@
 
 
-unsigned32 _CPU_ISR_Get_level( void );
+uint32_t   _CPU_ISR_Get_level( void );
 
 /* end of ISR handler macros */
@@ -606,7 +606,7 @@
 void _CPU_Context_Initialize(
   Context_Control  *the_context,
-  unsigned32       *stack_base,
-  unsigned32        size,
-  unsigned32        new_level,
+  uint32_t         *stack_base,
+  uint32_t          size,
+  uint32_t          new_level,
   void             *entry_point,
   boolean           is_fp
@@ -813,5 +813,5 @@
 
 void _CPU_ISR_install_vector(
-  unsigned32  vector,
+  uint32_t    vector,
   proc_ptr    new_handler,
   proc_ptr   *old_handler
@@ -899,5 +899,5 @@
 )
 {
-    unsigned32 tmp = value; /* make compiler warnings go away */
+    uint32_t   tmp = value; /* make compiler warnings go away */
     asm volatile ("EOR   %1, %0, %0, ROR #16\n" 
                   "BIC   %1, %1, #0xff0000\n"   
@@ -910,10 +910,10 @@
 }
 
-static inline unsigned16 CPU_swap_u16(unsigned16 value)
+static inline uint16_t   CPU_swap_u16(uint16_t   value)
 {
-    unsigned16 lower;
-    unsigned16 upper;
-
-    value = value & (unsigned16) 0xffff;
+    uint16_t   lower;
+    uint16_t   upper;
+
+    value = value & (uint16_t  ) 0xffff;
     lower = (value >> 8) ;
     upper = (value << 8) ;
Index: cpukit/score/cpu/h8300/ChangeLog
===================================================================
--- cpukit/score/cpu/h8300/ChangeLog	(revision e6aeabd8dcc7c34a66bd2b688f836be2eb847111)
+++ cpukit/score/cpu/h8300/ChangeLog	(revision c346f33d6df5aba8e1ce76d61a2357529ab6e353)
@@ -1,2 +1,6 @@
+2004-03-30	Ralf Corsepius <ralf_corsepius@rtems.org>
+
+	* cpu.c, rtems/score/cpu.h: Convert to using c99 fixed size types.
+
 2004-03-29	Ralf Corsepius <ralf_corsepius@rtems.org>
 
Index: cpukit/score/cpu/h8300/cpu.c
===================================================================
--- cpukit/score/cpu/h8300/cpu.c	(revision e6aeabd8dcc7c34a66bd2b688f836be2eb847111)
+++ cpukit/score/cpu/h8300/cpu.c	(revision c346f33d6df5aba8e1ce76d61a2357529ab6e353)
@@ -63,5 +63,5 @@
  */
  
-unsigned32 _CPU_ISR_Get_level( void )
+uint32_t   _CPU_ISR_Get_level( void )
 {
   unsigned int _ccr;
@@ -84,5 +84,5 @@
  
 void _CPU_ISR_install_raw_handler(
-  unsigned32  vector,
+  uint32_t    vector,
   proc_ptr    new_handler,
   proc_ptr   *old_handler
@@ -114,5 +114,5 @@
 
 void _CPU_ISR_install_vector(
-  unsigned32  vector,
+  uint32_t    vector,
   proc_ptr    new_handler,
   proc_ptr   *old_handler
Index: cpukit/score/cpu/h8300/rtems/score/cpu.h
===================================================================
--- cpukit/score/cpu/h8300/rtems/score/cpu.h	(revision e6aeabd8dcc7c34a66bd2b688f836be2eb847111)
+++ cpukit/score/cpu/h8300/rtems/score/cpu.h	(revision c346f33d6df5aba8e1ce76d61a2357529ab6e353)
@@ -379,14 +379,14 @@
 
 typedef struct {
-    unsigned16  ccr nogap;
+    uint16_t    ccr nogap;
     void	*er7 nogap;
     void 	*er6 nogap;
-    unsigned32  er5 nogap;
-    unsigned32	er4 nogap;
-    unsigned32  er3 nogap;
-    unsigned32	er2 nogap;
-    unsigned32  er1 nogap;
-    unsigned32	er0 nogap;
-    unsigned32  xxx nogap;
+    uint32_t    er5 nogap;
+    uint32_t  	er4 nogap;
+    uint32_t    er3 nogap;
+    uint32_t  	er2 nogap;
+    uint32_t    er1 nogap;
+    uint32_t  	er0 nogap;
+    uint32_t    xxx nogap;
 } Context_Control;
 
@@ -396,5 +396,5 @@
 
 typedef struct {
-    unsigned32 special_interrupt_register;
+    uint32_t   special_interrupt_register;
 } CPU_Interrupt_frame;
 
@@ -421,8 +421,8 @@
   void       (*idle_task)( void );
   boolean      do_zero_of_workspace;
-  unsigned32   idle_task_stack_size;
-  unsigned32   interrupt_stack_size;
-  unsigned32   extra_mpci_receive_server_stack;
-  void *     (*stack_allocate_hook)( unsigned32 );
+  uint32_t     idle_task_stack_size;
+  uint32_t     interrupt_stack_size;
+  uint32_t     extra_mpci_receive_server_stack;
+  void *     (*stack_allocate_hook)( uint32_t   );
   void       (*stack_free_hook)( void* );
 }   rtems_cpu_table;
@@ -615,5 +615,5 @@
 
 /* COPE With Brain dead version of GCC distributed with Hitachi HIView Tools.
-   Note requires ISR_Level be unsigned16 or assembler croaks.
+   Note requires ISR_Level be uint16_t   or assembler croaks.
 */
 
@@ -749,5 +749,5 @@
   }
 
-unsigned32 _CPU_ISR_Get_level( void );
+uint32_t   _CPU_ISR_Get_level( void );
 
 /* end of ISR handler macros */
@@ -788,10 +788,10 @@
   /* Locate Me */ \
   do { \
-    unsigned32 _stack; \
+    uint32_t   _stack; \
     \
     if ( (_isr) ) (_the_context)->ccr = CPU_CCR_INTERRUPTS_OFF; \
     else          (_the_context)->ccr = CPU_CCR_INTERRUPTS_ON; \
     \
-    _stack = ((unsigned32)(_stack_base)) + (_size) - 4; \
+    _stack = ((uint32_t  )(_stack_base)) + (_size) - 4; \
     *((proc_ptr *)(_stack)) = (_entry_point); \
      (_the_context)->er7     = (void *) _stack; \
@@ -1024,5 +1024,5 @@
  
 void _CPU_ISR_install_raw_handler(
-  unsigned32  vector,
+  uint32_t    vector,
   proc_ptr    new_handler,
   proc_ptr   *old_handler
@@ -1040,5 +1040,5 @@
 
 void _CPU_ISR_install_vector(
-  unsigned32  vector,
+  uint32_t    vector,
   proc_ptr    new_handler,
   proc_ptr   *old_handler
@@ -1159,9 +1159,9 @@
  */
  
-static inline unsigned32 CPU_swap_u32(
-  unsigned32 value
+static inline uint32_t   CPU_swap_u32(
+  uint32_t   value
 )
 {
-  unsigned32 byte1, byte2, byte3, byte4, swapped;
+  uint32_t   byte1, byte2, byte3, byte4, swapped;
  
   byte4 = (value >> 24) & 0xff;
@@ -1179,5 +1179,5 @@
 /* to be provided by the BSP */
 extern void H8BD_Install_IRQ(
-  unsigned32	vector,
+  uint32_t  	vector,
   proc_ptr	new_handler,
   proc_ptr	*old_handler );
Index: cpukit/score/cpu/i960/ChangeLog
===================================================================
--- cpukit/score/cpu/i960/ChangeLog	(revision e6aeabd8dcc7c34a66bd2b688f836be2eb847111)
+++ cpukit/score/cpu/i960/ChangeLog	(revision c346f33d6df5aba8e1ce76d61a2357529ab6e353)
@@ -1,2 +1,6 @@
+2004-03-30	Ralf Corsepius <ralf_corsepius@rtems.org>
+
+	* cpu.c, rtems/score/cpu.h: Convert to using c99 fixed size types.
+
 2004-03-29	Ralf Corsepius <ralf_corsepius@rtems.org>
 
Index: cpukit/score/cpu/i960/cpu.c
===================================================================
--- cpukit/score/cpu/i960/cpu.c	(revision e6aeabd8dcc7c34a66bd2b688f836be2eb847111)
+++ cpukit/score/cpu/i960/cpu.c	(revision c346f33d6df5aba8e1ce76d61a2357529ab6e353)
@@ -42,7 +42,7 @@
  */
  
-unsigned32 _CPU_ISR_Get_level( void )
+uint32_t   _CPU_ISR_Get_level( void )
 {
-  unsigned32 level;
+  uint32_t   level;
  
   i960_get_interrupt_level( level );
@@ -67,5 +67,5 @@
 
 void _CPU_ISR_install_vector(
-  unsigned32  vector,
+  uint32_t    vector,
   proc_ptr    new_handler,
   proc_ptr   *old_handler
Index: cpukit/score/cpu/i960/rtems/score/cpu.h
===================================================================
--- cpukit/score/cpu/i960/rtems/score/cpu.h	(revision e6aeabd8dcc7c34a66bd2b688f836be2eb847111)
+++ cpukit/score/cpu/i960/rtems/score/cpu.h	(revision c346f33d6df5aba8e1ce76d61a2357529ab6e353)
@@ -88,5 +88,5 @@
   void       *r0_pfp;                 /* (r0)  Previous Frame Pointer */
   void       *r1_sp;                  /* (r1)  Stack Pointer */
-  unsigned32  pc;                     /* (pc)  Processor Control */
+  uint32_t    pc;                     /* (pc)  Processor Control */
   void       *g8;                     /* (g8)  Global Register 8 */
   void       *g9;                     /* (g9)  Global Register 9 */
@@ -95,5 +95,5 @@
   void       *g12;                    /* (g12) Global Register 12 */
   void       *g13;                    /* (g13) Global Register 13 */
-  unsigned32  g14;                    /* (g14) Global Register 14 */
+  uint32_t    g14;                    /* (g14) Global Register 14 */
   void       *g15_fp;                 /* (g15) Frame Pointer */
 }   Context_Control;
@@ -104,16 +104,16 @@
 
 typedef struct {
-   unsigned32  fp0_1;                 /* (fp0) first word  */
-   unsigned32  fp0_2;                 /* (fp0) second word */
-   unsigned32  fp0_3;                 /* (fp0) third word  */
-   unsigned32  fp1_1;                 /* (fp1) first word  */
-   unsigned32  fp1_2;                 /* (fp1) second word */
-   unsigned32  fp1_3;                 /* (fp1) third word  */
-   unsigned32  fp2_1;                 /* (fp2) first word  */
-   unsigned32  fp2_2;                 /* (fp2) second word */
-   unsigned32  fp2_3;                 /* (fp2) third word  */
-   unsigned32  fp3_1;                 /* (fp3) first word  */
-   unsigned32  fp3_2;                 /* (fp3) second word */
-   unsigned32  fp3_3;                 /* (fp3) third word  */
+   uint32_t    fp0_1;                 /* (fp0) first word  */
+   uint32_t    fp0_2;                 /* (fp0) second word */
+   uint32_t    fp0_3;                 /* (fp0) third word  */
+   uint32_t    fp1_1;                 /* (fp1) first word  */
+   uint32_t    fp1_2;                 /* (fp1) second word */
+   uint32_t    fp1_3;                 /* (fp1) third word  */
+   uint32_t    fp2_1;                 /* (fp2) first word  */
+   uint32_t    fp2_2;                 /* (fp2) second word */
+   uint32_t    fp2_3;                 /* (fp2) third word  */
+   uint32_t    fp3_1;                 /* (fp3) first word  */
+   uint32_t    fp3_2;                 /* (fp3) second word */
+   uint32_t    fp3_3;                 /* (fp3) third word  */
 } Context_Control_fp;
 
@@ -124,5 +124,5 @@
 
 typedef struct {
-  unsigned32   TBD;   /* XXX Fix for this CPU */
+  uint32_t     TBD;   /* XXX Fix for this CPU */
 } CPU_Interrupt_frame;
 
@@ -162,8 +162,8 @@
   void       (*idle_task)( void );
   boolean      do_zero_of_workspace;
-  unsigned32   idle_task_stack_size;
-  unsigned32   interrupt_stack_size;
-  unsigned32   extra_mpci_receive_server_stack;
-  void *     (*stack_allocate_hook)( unsigned32 );
+  uint32_t     idle_task_stack_size;
+  uint32_t     interrupt_stack_size;
+  uint32_t     extra_mpci_receive_server_stack;
+  void *     (*stack_allocate_hook)( uint32_t   );
   void       (*stack_free_hook)( void* );
   /* end of fields required on all CPUs */
@@ -268,6 +268,6 @@
 #define _CPU_ISR_Set_level( newlevel ) \
   { \
-    unsigned32 _mask = 0; \
-    unsigned32 _level = (newlevel); \
+    uint32_t   _mask = 0; \
+    uint32_t   _level = (newlevel); \
     \
     __asm__ volatile ( "ldconst 0x1f0000,%0; \
@@ -277,5 +277,5 @@
   }
 
-unsigned32 _CPU_ISR_Get_level( void );
+uint32_t   _CPU_ISR_Get_level( void );
 
 /* ISR handler section macros */
@@ -294,10 +294,10 @@
                                   _isr, _entry, _is_fp ) \
  { CPU_Call_frame *_texit_frame; \
-   unsigned32 _mask; \
-   unsigned32 _base_pc; \
-   unsigned32  _stack_tmp; \
+   uint32_t   _mask; \
+   uint32_t   _base_pc; \
+   uint32_t    _stack_tmp; \
    void       *_stack; \
    \
-  _stack_tmp = (unsigned32)(_stack_base) + CPU_STACK_ALIGNMENT; \
+  _stack_tmp = (uint32_t  )(_stack_base) + CPU_STACK_ALIGNMENT; \
   _stack_tmp &= ~(CPU_STACK_ALIGNMENT - 1); \
   _stack = (void *) _stack_tmp; \
@@ -338,6 +338,6 @@
 
 #define _CPU_Fatal_halt( _errorcode ) \
-  { unsigned32 _mask, _level; \
-    unsigned32 _error = (_errorcode); \
+  { uint32_t   _mask, _level; \
+    uint32_t   _error = (_errorcode); \
     \
     __asm__ volatile ( "ldconst 0x1f0000,%0 ; \
@@ -362,5 +362,5 @@
 
 #define _CPU_Bitfield_Find_first_bit( _value, _output ) \
-  { unsigned32 _search = (_value); \
+  { uint32_t   _search = (_value); \
     \
     (_output) = 0; /* to prevent warnings */ \
@@ -411,5 +411,5 @@
  
 void _CPU_ISR_install_raw_handler(
-  unsigned32  vector,
+  uint32_t    vector,
   proc_ptr    new_handler,
   proc_ptr   *old_handler
@@ -423,5 +423,5 @@
 
 void _CPU_ISR_install_vector(
-  unsigned32  vector,
+  uint32_t    vector,
   proc_ptr    new_handler,
   proc_ptr   *old_handler
Index: cpukit/score/cpu/mips/ChangeLog
===================================================================
--- cpukit/score/cpu/mips/ChangeLog	(revision e6aeabd8dcc7c34a66bd2b688f836be2eb847111)
+++ cpukit/score/cpu/mips/ChangeLog	(revision c346f33d6df5aba8e1ce76d61a2357529ab6e353)
@@ -1,2 +1,6 @@
+2004-03-30	Ralf Corsepius <ralf_corsepius@rtems.org>
+
+	* cpu.c, rtems/score/cpu.h: Convert to using c99 fixed size types.
+
 2004-03-29	Ralf Corsepius <ralf_corsepius@rtems.org>
 
Index: cpukit/score/cpu/mips/cpu.c
===================================================================
--- cpukit/score/cpu/mips/cpu.c	(revision e6aeabd8dcc7c34a66bd2b688f836be2eb847111)
+++ cpukit/score/cpu/mips/cpu.c	(revision c346f33d6df5aba8e1ce76d61a2357529ab6e353)
@@ -94,5 +94,5 @@
  */
 
-unsigned32 _CPU_ISR_Get_level( void )
+uint32_t   _CPU_ISR_Get_level( void )
 {
   unsigned int sr;
@@ -118,5 +118,5 @@
 
 
-void _CPU_ISR_Set_level( unsigned32 new_level )
+void _CPU_ISR_Set_level( uint32_t   new_level )
 {
   unsigned int sr, srbits;
@@ -186,5 +186,5 @@
  
 void _CPU_ISR_install_raw_handler(
-  unsigned32  vector,
+  uint32_t    vector,
   proc_ptr    new_handler,
   proc_ptr   *old_handler
@@ -217,5 +217,5 @@
 
 void _CPU_ISR_install_vector(
-  unsigned32  vector,
+  uint32_t    vector,
   proc_ptr    new_handler,
   proc_ptr   *old_handler
Index: cpukit/score/cpu/mips/rtems/score/cpu.h
===================================================================
--- cpukit/score/cpu/mips/rtems/score/cpu.h	(revision e6aeabd8dcc7c34a66bd2b688f836be2eb847111)
+++ cpukit/score/cpu/mips/rtems/score/cpu.h	(revision c346f33d6df5aba8e1ce76d61a2357529ab6e353)
@@ -358,9 +358,9 @@
 /* WARNING: If this structure is modified, the constants in cpu.h must be updated. */
 #if __mips == 1
-#define __MIPS_REGISTER_TYPE     unsigned32
-#define __MIPS_FPU_REGISTER_TYPE unsigned32
+#define __MIPS_REGISTER_TYPE     uint32_t  
+#define __MIPS_FPU_REGISTER_TYPE uint32_t  
 #elif __mips == 3
-#define __MIPS_REGISTER_TYPE     unsigned64
-#define __MIPS_FPU_REGISTER_TYPE unsigned64
+#define __MIPS_REGISTER_TYPE     uint64_t  
+#define __MIPS_FPU_REGISTER_TYPE uint64_t  
 #else
 #error "mips register size: unknown architecture level!!"
@@ -582,12 +582,12 @@
   void       (*idle_task)( void );
   boolean      do_zero_of_workspace;
-  unsigned32   idle_task_stack_size;
-  unsigned32   interrupt_stack_size;
-  unsigned32   extra_mpci_receive_server_stack;
-  void *     (*stack_allocate_hook)( unsigned32 );
+  uint32_t     idle_task_stack_size;
+  uint32_t     interrupt_stack_size;
+  uint32_t     extra_mpci_receive_server_stack;
+  void *     (*stack_allocate_hook)( uint32_t   );
   void       (*stack_free_hook)( void* );
   /* end of fields required on all CPUs */
 
-  unsigned32   clicks_per_microsecond;
+  uint32_t     clicks_per_microsecond;
 }   rtems_cpu_table;
 
@@ -684,5 +684,5 @@
  */
 
-#define CPU_STACK_MINIMUM_SIZE          (2048*sizeof(unsigned32))
+#define CPU_STACK_MINIMUM_SIZE          (2048*sizeof(uint32_t  ))
 
 
@@ -798,7 +798,7 @@
  */
 
-unsigned32 _CPU_ISR_Get_level( void );  /* in cpu.c */
-
-void _CPU_ISR_Set_level( unsigned32 );  /* in cpu.c */
+uint32_t   _CPU_ISR_Get_level( void );  /* in cpu.c */
+
+void _CPU_ISR_Set_level( uint32_t   );  /* in cpu.c */
 
 /* end of ISR handler macros */
@@ -858,11 +858,11 @@
 #define _CPU_Context_Initialize( _the_context, _stack_base, _size, _isr, _entry_point, _is_fp ) \
   { \
- 	unsigned32 _stack_tmp = \
-           (unsigned32)(_stack_base) + (_size) - CPU_STACK_ALIGNMENT; \
-        unsigned32 _intlvl = _isr & 0xff; \
+ 	uint32_t   _stack_tmp = \
+           (uint32_t  )(_stack_base) + (_size) - CPU_STACK_ALIGNMENT; \
+        uint32_t   _intlvl = _isr & 0xff; \
   	_stack_tmp &= ~(CPU_STACK_ALIGNMENT - 1); \
   	(_the_context)->sp = _stack_tmp; \
   	(_the_context)->fp = _stack_tmp; \
-	(_the_context)->ra = (unsigned64)_entry_point; \
+	(_the_context)->ra = (uint64_t  )_entry_point; \
 	(_the_context)->c0_sr = ((_intlvl==0)?(0xFF00 | _INTON):( ((_intlvl<<9) & 0xfc00) | \
 						       0x300 | \
@@ -1063,5 +1063,5 @@
 
 void _CPU_ISR_install_raw_handler(
-  unsigned32  vector,
+  uint32_t    vector,
   proc_ptr    new_handler,
   proc_ptr   *old_handler
@@ -1075,5 +1075,5 @@
 
 void _CPU_ISR_install_vector(
-  unsigned32  vector,
+  uint32_t    vector,
   proc_ptr    new_handler,
   proc_ptr   *old_handler
@@ -1170,5 +1170,5 @@
 )
 {
-  unsigned32 byte1, byte2, byte3, byte4, swapped;
+  uint32_t   byte1, byte2, byte3, byte4, swapped;
 
   byte4 = (value >> 24) & 0xff;
Index: cpukit/score/cpu/no_cpu/ChangeLog
===================================================================
--- cpukit/score/cpu/no_cpu/ChangeLog	(revision e6aeabd8dcc7c34a66bd2b688f836be2eb847111)
+++ cpukit/score/cpu/no_cpu/ChangeLog	(revision c346f33d6df5aba8e1ce76d61a2357529ab6e353)
@@ -1,2 +1,6 @@
+2004-03-30	Ralf Corsepius <ralf_corsepius@rtems.org>
+
+	* cpu.c, rtems/score/cpu.h: Convert to using c99 fixed size types.
+
 2004-03-29	Ralf Corsepius <ralf_corsepius@rtems.org>
 
Index: cpukit/score/cpu/no_cpu/cpu.c
===================================================================
--- cpukit/score/cpu/no_cpu/cpu.c	(revision e6aeabd8dcc7c34a66bd2b688f836be2eb847111)
+++ cpukit/score/cpu/no_cpu/cpu.c	(revision c346f33d6df5aba8e1ce76d61a2357529ab6e353)
@@ -70,5 +70,5 @@
  */
  
-unsigned32 _CPU_ISR_Get_level( void )
+uint32_t   _CPU_ISR_Get_level( void )
 {
   /*
@@ -89,5 +89,5 @@
  
 void _CPU_ISR_install_raw_handler(
-  unsigned32  vector,
+  uint32_t    vector,
   proc_ptr    new_handler,
   proc_ptr   *old_handler
@@ -121,5 +121,5 @@
 
 void _CPU_ISR_install_vector(
-  unsigned32  vector,
+  uint32_t    vector,
   proc_ptr    new_handler,
   proc_ptr   *old_handler
Index: cpukit/score/cpu/no_cpu/rtems/score/cpu.h
===================================================================
--- cpukit/score/cpu/no_cpu/rtems/score/cpu.h	(revision e6aeabd8dcc7c34a66bd2b688f836be2eb847111)
+++ cpukit/score/cpu/no_cpu/rtems/score/cpu.h	(revision c346f33d6df5aba8e1ce76d61a2357529ab6e353)
@@ -409,6 +409,6 @@
 
 typedef struct {
-    unsigned32 some_integer_register;
-    unsigned32 some_system_register;
+    uint32_t   some_integer_register;
+    uint32_t   some_system_register;
 } Context_Control;
 
@@ -418,5 +418,5 @@
 
 typedef struct {
-    unsigned32 special_interrupt_register;
+    uint32_t   special_interrupt_register;
 } CPU_Interrupt_frame;
 
@@ -437,8 +437,8 @@
   void       (*idle_task)( void );
   boolean      do_zero_of_workspace;
-  unsigned32   idle_task_stack_size;
-  unsigned32   interrupt_stack_size;
-  unsigned32   extra_mpci_receive_server_stack;
-  void *     (*stack_allocate_hook)( unsigned32 );
+  uint32_t     idle_task_stack_size;
+  uint32_t     interrupt_stack_size;
+  uint32_t     extra_mpci_receive_server_stack;
+  void *     (*stack_allocate_hook)( uint32_t   );
   void       (*stack_free_hook)( void* );
   /* end of fields required on all CPUs */
@@ -727,5 +727,5 @@
   }
 
-unsigned32 _CPU_ISR_Get_level( void );
+uint32_t   _CPU_ISR_Get_level( void );
 
 /* end of ISR handler macros */
@@ -983,5 +983,5 @@
  
 void _CPU_ISR_install_raw_handler(
-  unsigned32  vector,
+  uint32_t    vector,
   proc_ptr    new_handler,
   proc_ptr   *old_handler
@@ -999,5 +999,5 @@
 
 void _CPU_ISR_install_vector(
-  unsigned32  vector,
+  uint32_t    vector,
   proc_ptr    new_handler,
   proc_ptr   *old_handler
@@ -1122,5 +1122,5 @@
 )
 {
-  unsigned32 byte1, byte2, byte3, byte4, swapped;
+  uint32_t   byte1, byte2, byte3, byte4, swapped;
  
   byte4 = (value >> 24) & 0xff;
Index: cpukit/score/cpu/unix/ChangeLog
===================================================================
--- cpukit/score/cpu/unix/ChangeLog	(revision e6aeabd8dcc7c34a66bd2b688f836be2eb847111)
+++ cpukit/score/cpu/unix/ChangeLog	(revision c346f33d6df5aba8e1ce76d61a2357529ab6e353)
@@ -1,2 +1,6 @@
+2004-03-30	Ralf Corsepius <ralf_corsepius@rtems.org>
+
+	* cpu.c, rtems/score/cpu.h: Convert to using c99 fixed size types.
+
 2004-03-29	Ralf Corsepius <ralf_corsepius@rtems.org>
 
Index: cpukit/score/cpu/unix/cpu.c
===================================================================
--- cpukit/score/cpu/unix/cpu.c	(revision e6aeabd8dcc7c34a66bd2b688f836be2eb847111)
+++ cpukit/score/cpu/unix/cpu.c	(revision c346f33d6df5aba8e1ce76d61a2357529ab6e353)
@@ -87,5 +87,5 @@
 void _CPU_Initialize_vectors(void)
 {
-  unsigned32        i;
+  uint32_t          i;
   proc_ptr          old_handler;
 
@@ -195,5 +195,5 @@
 
     {
-      extern unsigned32 _SYSTEM_ID;
+      extern uint32_t   _SYSTEM_ID;
 
       _SYSTEM_ID = 0x20c;
@@ -255,5 +255,5 @@
  */
 
-unsigned32 _CPU_ISR_Get_level( void )
+uint32_t   _CPU_ISR_Get_level( void )
 {
   sigset_t old_mask;
@@ -328,5 +328,5 @@
 
 void _CPU_ISR_install_raw_handler(
-  unsigned32  vector,
+  uint32_t    vector,
   proc_ptr    new_handler,
   proc_ptr   *old_handler
@@ -354,5 +354,5 @@
 
 void _CPU_ISR_install_vector(
-  unsigned32  vector,
+  uint32_t    vector,
   proc_ptr    new_handler,
   proc_ptr   *old_handler
@@ -461,18 +461,18 @@
 void _CPU_Context_Initialize(
   Context_Control  *_the_context,
-  unsigned32       *_stack_base,
-  unsigned32        _size,
-  unsigned32        _new_level,
+  uint32_t         *_stack_base,
+  uint32_t          _size,
+  uint32_t          _new_level,
   void             *_entry_point,
   boolean           _is_fp
 )
 {
-  unsigned32  *addr;
-  unsigned32   jmp_addr;
-  unsigned32   _stack_low;   /* lowest "stack aligned" address */
-  unsigned32   _stack_high;  /* highest "stack aligned" address */
-  unsigned32   _the_size;
-
-  jmp_addr = (unsigned32) _entry_point;
+  uint32_t    *addr;
+  uint32_t     jmp_addr;
+  uint32_t     _stack_low;   /* lowest "stack aligned" address */
+  uint32_t     _stack_high;  /* highest "stack aligned" address */
+  uint32_t     _the_size;
+
+  jmp_addr = (uint32_t  ) _entry_point;
 
   /*
@@ -482,8 +482,8 @@
    */
 
-  _stack_low = (unsigned32)(_stack_base) + CPU_STACK_ALIGNMENT - 1;
+  _stack_low = (uint32_t  )(_stack_base) + CPU_STACK_ALIGNMENT - 1;
   _stack_low &= ~(CPU_STACK_ALIGNMENT - 1);
 
-  _stack_high = (unsigned32)(_stack_base) + _size;
+  _stack_high = (uint32_t  )(_stack_base) + _size;
   _stack_high &= ~(CPU_STACK_ALIGNMENT - 1);
 
@@ -504,9 +504,9 @@
                          _CPU_Context_Default_with_ISRs_disabled;
 
-  addr = (unsigned32 *)_the_context;
+  addr = (uint32_t   *)_the_context;
 
 #if defined(__hppa__)
   *(addr + RP_OFF) = jmp_addr;
-  *(addr + SP_OFF) = (unsigned32)(_stack_low + CPU_FRAME_SIZE);
+  *(addr + SP_OFF) = (uint32_t  )(_stack_low + CPU_FRAME_SIZE);
 
   /*
@@ -519,5 +519,5 @@
   if (jmp_addr & 0x40000000) {
     jmp_addr &= 0xfffffffc;
-     *(addr + RP_OFF) = *(unsigned32 *)jmp_addr;
+     *(addr + RP_OFF) = *(uint32_t   *)jmp_addr;
   }
 #elif defined(__sparc__)
@@ -531,6 +531,6 @@
 
   *(addr + RP_OFF) = jmp_addr + ADDR_ADJ_OFFSET;
-  *(addr + SP_OFF) = (unsigned32)(_stack_high - CPU_FRAME_SIZE);
-  *(addr + FP_OFF) = (unsigned32)(_stack_high);
+  *(addr + SP_OFF) = (uint32_t  )(_stack_high - CPU_FRAME_SIZE);
+  *(addr + FP_OFF) = (uint32_t  )(_stack_high);
 
 #elif defined(__i386__)
@@ -541,5 +541,5 @@
 
     {
-      unsigned32 stack_ptr;
+      uint32_t   stack_ptr;
 
       stack_ptr = _stack_high - CPU_FRAME_SIZE;
@@ -552,9 +552,9 @@
       *(addr + RET_OFF) = jmp_addr;
 
-      addr = (unsigned32 *) stack_ptr;
+      addr = (uint32_t   *) stack_ptr;
 
       addr[ 0 ] = jmp_addr;
-      addr[ 1 ] = (unsigned32) stack_ptr;
-      addr[ 2 ] = (unsigned32) stack_ptr;
+      addr[ 1 ] = (uint32_t  ) stack_ptr;
+      addr[ 2 ] = (uint32_t  ) stack_ptr;
     }
 
@@ -668,5 +668,5 @@
  */
 
-unsigned32 _CPU_ISR_Disable_support(void)
+uint32_t   _CPU_ISR_Disable_support(void)
 {
   int status;
@@ -694,5 +694,5 @@
 
 void _CPU_ISR_Enable(
-  unsigned32 level
+  uint32_t   level
 )
 {
@@ -724,5 +724,5 @@
 {
   extern void        _Thread_Dispatch(void);
-  extern unsigned32  _Thread_Dispatch_disable_level;
+  extern uint32_t    _Thread_Dispatch_disable_level;
   extern boolean     _Context_Switch_necessary;
 
@@ -834,5 +834,5 @@
  */
 
-void _CPU_Fatal_error(unsigned32 error)
+void _CPU_Fatal_error(uint32_t   error)
 {
   setitimer(ITIMER_REAL, 0, 0);
@@ -951,8 +951,8 @@
 
 void _CPU_SHM_Init(
-  unsigned32   maximum_nodes,
+  uint32_t     maximum_nodes,
   boolean      is_master_node,
   void       **shm_address,
-  unsigned32  *shm_length
+  uint32_t    *shm_length
 )
 {
Index: cpukit/score/cpu/unix/rtems/score/cpu.h
===================================================================
--- cpukit/score/cpu/unix/rtems/score/cpu.h	(revision e6aeabd8dcc7c34a66bd2b688f836be2eb847111)
+++ cpukit/score/cpu/unix/rtems/score/cpu.h	(revision c346f33d6df5aba8e1ce76d61a2357529ab6e353)
@@ -467,5 +467,5 @@
  *
  *    jmp_buf    regs;
- *    unsigned32 isr_level;
+ *    uint32_t   isr_level;
  *
  *  Doing it this way avoids conflicts between the native stuff and the
@@ -507,8 +507,8 @@
   void       (*idle_task)( void );
   boolean      do_zero_of_workspace;
-  unsigned32   idle_task_stack_size;
-  unsigned32   interrupt_stack_size;
-  unsigned32   extra_mpci_receive_server_stack;
-  void *     (*stack_allocate_hook)( unsigned32 );
+  uint32_t     idle_task_stack_size;
+  uint32_t     interrupt_stack_size;
+  uint32_t     extra_mpci_receive_server_stack;
+  void *     (*stack_allocate_hook)( uint32_t   );
   void       (*stack_free_hook)( void* );
   /* end of required fields */
@@ -683,5 +683,5 @@
  */
 
-extern unsigned32 _CPU_ISR_Disable_support(void);
+extern uint32_t   _CPU_ISR_Disable_support(void);
 
 #define _CPU_ISR_Disable( _level ) \
@@ -696,5 +696,5 @@
  */
 
-void _CPU_ISR_Enable(unsigned32 level);
+void _CPU_ISR_Enable(uint32_t   level);
 
 /*
@@ -707,5 +707,5 @@
 #define _CPU_ISR_Flash( _level ) \
   do { \
-      register unsigned32 _ignored = 0; \
+      register uint32_t   _ignored = 0; \
       _CPU_ISR_Enable( (_level) ); \
       _CPU_ISR_Disable( _ignored ); \
@@ -729,5 +729,5 @@
   }
 
-unsigned32 _CPU_ISR_Get_level( void );
+uint32_t   _CPU_ISR_Get_level( void );
 
 /* end of ISR handler macros */
@@ -790,7 +790,7 @@
 extern void _CPU_Context_Initialize(
   Context_Control  *_the_context,
-  unsigned32       *_stack_base,
-  unsigned32        _size,
-  unsigned32        _new_level,
+  uint32_t         *_stack_base,
+  uint32_t          _size,
+  uint32_t          _new_level,
   void             *_entry_point,
   boolean           _is_fp
@@ -911,5 +911,5 @@
  
 void _CPU_ISR_install_raw_handler(
-  unsigned32  vector,
+  uint32_t    vector,
   proc_ptr    new_handler,
   proc_ptr   *old_handler
@@ -923,5 +923,5 @@
 
 void _CPU_ISR_install_vector(
-  unsigned32  vector,
+  uint32_t    vector,
   proc_ptr    new_handler,
   proc_ptr   *old_handler
@@ -996,9 +996,9 @@
 
 void _CPU_ISR_Set_signal_level(
-  unsigned32 level
+  uint32_t   level
 );
 
 void _CPU_Fatal_error(
-  unsigned32 _error
+  uint32_t   _error
 );
 
@@ -1027,5 +1027,5 @@
 )
 {
-  unsigned32 byte1, byte2, byte3, byte4, swapped;
+  uint32_t   byte1, byte2, byte3, byte4, swapped;
  
   byte4 = (value >> 24) & 0xff;
@@ -1082,8 +1082,8 @@
 
 void _CPU_SHM_Init( 
-  unsigned32   maximum_nodes,
+  uint32_t     maximum_nodes,
   boolean      is_master_node,
   void       **shm_address,
-  unsigned32  *shm_length
+  uint32_t    *shm_length
 );
 
