Changeset c346f33d in rtems for cpukit/score/cpu/arm/rtems/score/cpu.h
- Timestamp:
- 03/30/04 11:49:14 (20 years ago)
- Branches:
- 4.10, 4.11, 4.8, 4.9, 5, master
- Children:
- 30b1016
- Parents:
- e6aeabd
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
cpukit/score/cpu/arm/rtems/score/cpu.h
re6aeabd rc346f33d 335 335 */ 336 336 typedef struct { 337 u nsigned32register_cpsr;338 u nsigned32register_r4;339 u nsigned32register_r5;340 u nsigned32register_r6;341 u nsigned32register_r7;342 u nsigned32register_r8;343 u nsigned32register_r9;344 u nsigned32register_r10;345 u nsigned32register_fp;346 u nsigned32register_sp;347 u nsigned32register_lr;348 u nsigned32register_pc;337 uint32_t register_cpsr; 338 uint32_t register_r4; 339 uint32_t register_r5; 340 uint32_t register_r6; 341 uint32_t register_r7; 342 uint32_t register_r8; 343 uint32_t register_r9; 344 uint32_t register_r10; 345 uint32_t register_fp; 346 uint32_t register_sp; 347 uint32_t register_lr; 348 uint32_t register_pc; 349 349 } Context_Control; 350 350 … … 354 354 355 355 typedef struct { 356 u nsigned32register_r0;357 u nsigned32register_r1;358 u nsigned32register_r2;359 u nsigned32register_r3;360 u nsigned32register_ip;361 u nsigned32register_lr;356 uint32_t register_r0; 357 uint32_t register_r1; 358 uint32_t register_r2; 359 uint32_t register_r3; 360 uint32_t register_ip; 361 uint32_t register_lr; 362 362 } CPU_Exception_frame; 363 363 … … 385 385 void (*idle_task)( void ); 386 386 boolean do_zero_of_workspace; 387 u nsigned32idle_task_stack_size;388 u nsigned32interrupt_stack_size;389 u nsigned32extra_mpci_receive_server_stack;390 void * (*stack_allocate_hook)( u nsigned32);387 uint32_t idle_task_stack_size; 388 uint32_t interrupt_stack_size; 389 uint32_t extra_mpci_receive_server_stack; 390 void * (*stack_allocate_hook)( uint32_t ); 391 391 void (*stack_free_hook)( void* ); 392 392 /* end of fields required on all CPUs */ … … 577 577 578 578 579 u nsigned32_CPU_ISR_Get_level( void );579 uint32_t _CPU_ISR_Get_level( void ); 580 580 581 581 /* end of ISR handler macros */ … … 606 606 void _CPU_Context_Initialize( 607 607 Context_Control *the_context, 608 u nsigned32*stack_base,609 u nsigned32size,610 u nsigned32new_level,608 uint32_t *stack_base, 609 uint32_t size, 610 uint32_t new_level, 611 611 void *entry_point, 612 612 boolean is_fp … … 813 813 814 814 void _CPU_ISR_install_vector( 815 u nsigned32vector,815 uint32_t vector, 816 816 proc_ptr new_handler, 817 817 proc_ptr *old_handler … … 899 899 ) 900 900 { 901 u nsigned32tmp = value; /* make compiler warnings go away */901 uint32_t tmp = value; /* make compiler warnings go away */ 902 902 asm volatile ("EOR %1, %0, %0, ROR #16\n" 903 903 "BIC %1, %1, #0xff0000\n" … … 910 910 } 911 911 912 static inline u nsigned16 CPU_swap_u16(unsigned16value)912 static inline uint16_t CPU_swap_u16(uint16_t value) 913 913 { 914 u nsigned16lower;915 u nsigned16upper;916 917 value = value & (u nsigned16) 0xffff;914 uint16_t lower; 915 uint16_t upper; 916 917 value = value & (uint16_t ) 0xffff; 918 918 lower = (value >> 8) ; 919 919 upper = (value << 8) ;
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