Changeset c346f33d in rtems
- Timestamp:
- 03/30/04 11:49:14 (19 years ago)
- Branches:
- 4.10, 4.11, 4.8, 4.9, 5, master
- Children:
- 30b1016
- Parents:
- e6aeabd
- Location:
- cpukit/score/cpu
- Files:
-
- 18 edited
Legend:
- Unmodified
- Added
- Removed
-
cpukit/score/cpu/arm/ChangeLog
re6aeabd rc346f33d 1 2004-03-30 Ralf Corsepius <ralf_corsepius@rtems.org> 2 3 * cpu.c, rtems/score/cpu.h: Convert to using c99 fixed size types. 4 1 5 2004-03-29 Ralf Corsepius <ralf_corsepius@rtems.org> 2 6 -
cpukit/score/cpu/arm/cpu.c
re6aeabd rc346f33d 33 33 */ 34 34 35 u nsigned32g_data_abort_cnt = 0;36 u nsigned32g_data_abort_insn_list[1024];35 uint32_t g_data_abort_cnt = 0; 36 uint32_t g_data_abort_insn_list[1024]; 37 37 38 38 void _CPU_Initialize( … … 49 49 */ 50 50 51 u nsigned32_CPU_ISR_Get_level( void )52 { 53 u nsigned32reg = 0; /* to avoid warning */51 uint32_t _CPU_ISR_Get_level( void ) 52 { 53 uint32_t reg = 0; /* to avoid warning */ 54 54 55 55 asm volatile ("mrs %0, cpsr \n" \ … … 81 81 */ 82 82 void _CPU_ISR_install_vector( 83 u nsigned32vector,83 uint32_t vector, 84 84 proc_ptr new_handler, 85 85 proc_ptr *old_handler … … 99 99 void _CPU_Context_Initialize( 100 100 Context_Control *the_context, 101 u nsigned32*stack_base,102 u nsigned32size,103 u nsigned32new_level,101 uint32_t *stack_base, 102 uint32_t size, 103 uint32_t new_level, 104 104 void *entry_point, 105 105 boolean is_fp 106 106 ) 107 107 { 108 the_context->register_sp = (u nsigned32)stack_base + size ;109 the_context->register_lr = (u nsigned32)entry_point;108 the_context->register_sp = (uint32_t )stack_base + size ; 109 the_context->register_lr = (uint32_t )entry_point; 110 110 the_context->register_cpsr = new_level | 0x13; 111 111 } … … 218 218 #define GET_I(x) ((x & 0x02000000) >> 25) 219 219 220 #define GET_REG(r, ctx) (((u nsigned32*)ctx)[r])221 #define SET_REG(r, ctx, v) (((u nsigned32*)ctx)[r] = v)220 #define GET_REG(r, ctx) (((uint32_t *)ctx)[r]) 221 #define SET_REG(r, ctx, v) (((uint32_t *)ctx)[r] = v) 222 222 #define GET_OFFSET(insn) (insn & 0xfff) 223 223 … … 229 229 */ 230 230 231 void do_data_abort(u nsigned32 insn, unsigned32spsr,231 void do_data_abort(uint32_t insn, uint32_t spsr, 232 232 CPU_Exception_frame *ctx) 233 233 { 234 u nsigned8decode;235 u nsigned8insn_type;236 237 u nsigned32rn;238 u nsigned32rd;239 240 u nsigned8*src_addr;241 u nsigned32tmp;234 uint8_t decode; 235 uint8_t insn_type; 236 237 uint32_t rn; 238 uint32_t rd; 239 240 uint8_t *src_addr; 241 uint32_t tmp; 242 242 243 243 g_data_abort_insn_list[g_data_abort_cnt & 0x3ff] = ctx->register_lr - 8; … … 282 282 break; 283 283 case 0x10: /* P=1, W=0 -> base not updated */ 284 src_addr = (u nsigned8*)GET_REG(rn, ctx);284 src_addr = (uint8_t *)GET_REG(rn, ctx); 285 285 if (GET_U(insn) == 0) { 286 286 src_addr -= GET_OFFSET(insn); -
cpukit/score/cpu/arm/rtems/score/cpu.h
re6aeabd rc346f33d 335 335 */ 336 336 typedef struct { 337 u nsigned32register_cpsr;338 u nsigned32register_r4;339 u nsigned32register_r5;340 u nsigned32register_r6;341 u nsigned32register_r7;342 u nsigned32register_r8;343 u nsigned32register_r9;344 u nsigned32register_r10;345 u nsigned32register_fp;346 u nsigned32register_sp;347 u nsigned32register_lr;348 u nsigned32register_pc;337 uint32_t register_cpsr; 338 uint32_t register_r4; 339 uint32_t register_r5; 340 uint32_t register_r6; 341 uint32_t register_r7; 342 uint32_t register_r8; 343 uint32_t register_r9; 344 uint32_t register_r10; 345 uint32_t register_fp; 346 uint32_t register_sp; 347 uint32_t register_lr; 348 uint32_t register_pc; 349 349 } Context_Control; 350 350 … … 354 354 355 355 typedef struct { 356 u nsigned32register_r0;357 u nsigned32register_r1;358 u nsigned32register_r2;359 u nsigned32register_r3;360 u nsigned32register_ip;361 u nsigned32register_lr;356 uint32_t register_r0; 357 uint32_t register_r1; 358 uint32_t register_r2; 359 uint32_t register_r3; 360 uint32_t register_ip; 361 uint32_t register_lr; 362 362 } CPU_Exception_frame; 363 363 … … 385 385 void (*idle_task)( void ); 386 386 boolean do_zero_of_workspace; 387 u nsigned32idle_task_stack_size;388 u nsigned32interrupt_stack_size;389 u nsigned32extra_mpci_receive_server_stack;390 void * (*stack_allocate_hook)( u nsigned32);387 uint32_t idle_task_stack_size; 388 uint32_t interrupt_stack_size; 389 uint32_t extra_mpci_receive_server_stack; 390 void * (*stack_allocate_hook)( uint32_t ); 391 391 void (*stack_free_hook)( void* ); 392 392 /* end of fields required on all CPUs */ … … 577 577 578 578 579 u nsigned32_CPU_ISR_Get_level( void );579 uint32_t _CPU_ISR_Get_level( void ); 580 580 581 581 /* end of ISR handler macros */ … … 606 606 void _CPU_Context_Initialize( 607 607 Context_Control *the_context, 608 u nsigned32*stack_base,609 u nsigned32size,610 u nsigned32new_level,608 uint32_t *stack_base, 609 uint32_t size, 610 uint32_t new_level, 611 611 void *entry_point, 612 612 boolean is_fp … … 813 813 814 814 void _CPU_ISR_install_vector( 815 u nsigned32vector,815 uint32_t vector, 816 816 proc_ptr new_handler, 817 817 proc_ptr *old_handler … … 899 899 ) 900 900 { 901 u nsigned32tmp = value; /* make compiler warnings go away */901 uint32_t tmp = value; /* make compiler warnings go away */ 902 902 asm volatile ("EOR %1, %0, %0, ROR #16\n" 903 903 "BIC %1, %1, #0xff0000\n" … … 910 910 } 911 911 912 static inline u nsigned16 CPU_swap_u16(unsigned16value)912 static inline uint16_t CPU_swap_u16(uint16_t value) 913 913 { 914 u nsigned16lower;915 u nsigned16upper;916 917 value = value & (u nsigned16) 0xffff;914 uint16_t lower; 915 uint16_t upper; 916 917 value = value & (uint16_t ) 0xffff; 918 918 lower = (value >> 8) ; 919 919 upper = (value << 8) ; -
cpukit/score/cpu/h8300/ChangeLog
re6aeabd rc346f33d 1 2004-03-30 Ralf Corsepius <ralf_corsepius@rtems.org> 2 3 * cpu.c, rtems/score/cpu.h: Convert to using c99 fixed size types. 4 1 5 2004-03-29 Ralf Corsepius <ralf_corsepius@rtems.org> 2 6 -
cpukit/score/cpu/h8300/cpu.c
re6aeabd rc346f33d 63 63 */ 64 64 65 u nsigned32_CPU_ISR_Get_level( void )65 uint32_t _CPU_ISR_Get_level( void ) 66 66 { 67 67 unsigned int _ccr; … … 84 84 85 85 void _CPU_ISR_install_raw_handler( 86 u nsigned32vector,86 uint32_t vector, 87 87 proc_ptr new_handler, 88 88 proc_ptr *old_handler … … 114 114 115 115 void _CPU_ISR_install_vector( 116 u nsigned32vector,116 uint32_t vector, 117 117 proc_ptr new_handler, 118 118 proc_ptr *old_handler -
cpukit/score/cpu/h8300/rtems/score/cpu.h
re6aeabd rc346f33d 379 379 380 380 typedef struct { 381 u nsigned16ccr nogap;381 uint16_t ccr nogap; 382 382 void *er7 nogap; 383 383 void *er6 nogap; 384 u nsigned32er5 nogap;385 u nsigned32er4 nogap;386 u nsigned32er3 nogap;387 u nsigned32er2 nogap;388 u nsigned32er1 nogap;389 u nsigned32er0 nogap;390 u nsigned32xxx nogap;384 uint32_t er5 nogap; 385 uint32_t er4 nogap; 386 uint32_t er3 nogap; 387 uint32_t er2 nogap; 388 uint32_t er1 nogap; 389 uint32_t er0 nogap; 390 uint32_t xxx nogap; 391 391 } Context_Control; 392 392 … … 396 396 397 397 typedef struct { 398 u nsigned32special_interrupt_register;398 uint32_t special_interrupt_register; 399 399 } CPU_Interrupt_frame; 400 400 … … 421 421 void (*idle_task)( void ); 422 422 boolean do_zero_of_workspace; 423 u nsigned32idle_task_stack_size;424 u nsigned32interrupt_stack_size;425 u nsigned32extra_mpci_receive_server_stack;426 void * (*stack_allocate_hook)( u nsigned32);423 uint32_t idle_task_stack_size; 424 uint32_t interrupt_stack_size; 425 uint32_t extra_mpci_receive_server_stack; 426 void * (*stack_allocate_hook)( uint32_t ); 427 427 void (*stack_free_hook)( void* ); 428 428 } rtems_cpu_table; … … 615 615 616 616 /* COPE With Brain dead version of GCC distributed with Hitachi HIView Tools. 617 Note requires ISR_Level be u nsigned16or assembler croaks.617 Note requires ISR_Level be uint16_t or assembler croaks. 618 618 */ 619 619 … … 749 749 } 750 750 751 u nsigned32_CPU_ISR_Get_level( void );751 uint32_t _CPU_ISR_Get_level( void ); 752 752 753 753 /* end of ISR handler macros */ … … 788 788 /* Locate Me */ \ 789 789 do { \ 790 u nsigned32_stack; \790 uint32_t _stack; \ 791 791 \ 792 792 if ( (_isr) ) (_the_context)->ccr = CPU_CCR_INTERRUPTS_OFF; \ 793 793 else (_the_context)->ccr = CPU_CCR_INTERRUPTS_ON; \ 794 794 \ 795 _stack = ((u nsigned32)(_stack_base)) + (_size) - 4; \795 _stack = ((uint32_t )(_stack_base)) + (_size) - 4; \ 796 796 *((proc_ptr *)(_stack)) = (_entry_point); \ 797 797 (_the_context)->er7 = (void *) _stack; \ … … 1024 1024 1025 1025 void _CPU_ISR_install_raw_handler( 1026 u nsigned32vector,1026 uint32_t vector, 1027 1027 proc_ptr new_handler, 1028 1028 proc_ptr *old_handler … … 1040 1040 1041 1041 void _CPU_ISR_install_vector( 1042 u nsigned32vector,1042 uint32_t vector, 1043 1043 proc_ptr new_handler, 1044 1044 proc_ptr *old_handler … … 1159 1159 */ 1160 1160 1161 static inline u nsigned32CPU_swap_u32(1162 u nsigned32value1161 static inline uint32_t CPU_swap_u32( 1162 uint32_t value 1163 1163 ) 1164 1164 { 1165 u nsigned32byte1, byte2, byte3, byte4, swapped;1165 uint32_t byte1, byte2, byte3, byte4, swapped; 1166 1166 1167 1167 byte4 = (value >> 24) & 0xff; … … 1179 1179 /* to be provided by the BSP */ 1180 1180 extern void H8BD_Install_IRQ( 1181 u nsigned32vector,1181 uint32_t vector, 1182 1182 proc_ptr new_handler, 1183 1183 proc_ptr *old_handler ); -
cpukit/score/cpu/i960/ChangeLog
re6aeabd rc346f33d 1 2004-03-30 Ralf Corsepius <ralf_corsepius@rtems.org> 2 3 * cpu.c, rtems/score/cpu.h: Convert to using c99 fixed size types. 4 1 5 2004-03-29 Ralf Corsepius <ralf_corsepius@rtems.org> 2 6 -
cpukit/score/cpu/i960/cpu.c
re6aeabd rc346f33d 42 42 */ 43 43 44 u nsigned32_CPU_ISR_Get_level( void )44 uint32_t _CPU_ISR_Get_level( void ) 45 45 { 46 u nsigned32level;46 uint32_t level; 47 47 48 48 i960_get_interrupt_level( level ); … … 67 67 68 68 void _CPU_ISR_install_vector( 69 u nsigned32vector,69 uint32_t vector, 70 70 proc_ptr new_handler, 71 71 proc_ptr *old_handler -
cpukit/score/cpu/i960/rtems/score/cpu.h
re6aeabd rc346f33d 88 88 void *r0_pfp; /* (r0) Previous Frame Pointer */ 89 89 void *r1_sp; /* (r1) Stack Pointer */ 90 u nsigned32pc; /* (pc) Processor Control */90 uint32_t pc; /* (pc) Processor Control */ 91 91 void *g8; /* (g8) Global Register 8 */ 92 92 void *g9; /* (g9) Global Register 9 */ … … 95 95 void *g12; /* (g12) Global Register 12 */ 96 96 void *g13; /* (g13) Global Register 13 */ 97 u nsigned32g14; /* (g14) Global Register 14 */97 uint32_t g14; /* (g14) Global Register 14 */ 98 98 void *g15_fp; /* (g15) Frame Pointer */ 99 99 } Context_Control; … … 104 104 105 105 typedef struct { 106 u nsigned32fp0_1; /* (fp0) first word */107 u nsigned32fp0_2; /* (fp0) second word */108 u nsigned32fp0_3; /* (fp0) third word */109 u nsigned32fp1_1; /* (fp1) first word */110 u nsigned32fp1_2; /* (fp1) second word */111 u nsigned32fp1_3; /* (fp1) third word */112 u nsigned32fp2_1; /* (fp2) first word */113 u nsigned32fp2_2; /* (fp2) second word */114 u nsigned32fp2_3; /* (fp2) third word */115 u nsigned32fp3_1; /* (fp3) first word */116 u nsigned32fp3_2; /* (fp3) second word */117 u nsigned32fp3_3; /* (fp3) third word */106 uint32_t fp0_1; /* (fp0) first word */ 107 uint32_t fp0_2; /* (fp0) second word */ 108 uint32_t fp0_3; /* (fp0) third word */ 109 uint32_t fp1_1; /* (fp1) first word */ 110 uint32_t fp1_2; /* (fp1) second word */ 111 uint32_t fp1_3; /* (fp1) third word */ 112 uint32_t fp2_1; /* (fp2) first word */ 113 uint32_t fp2_2; /* (fp2) second word */ 114 uint32_t fp2_3; /* (fp2) third word */ 115 uint32_t fp3_1; /* (fp3) first word */ 116 uint32_t fp3_2; /* (fp3) second word */ 117 uint32_t fp3_3; /* (fp3) third word */ 118 118 } Context_Control_fp; 119 119 … … 124 124 125 125 typedef struct { 126 u nsigned32TBD; /* XXX Fix for this CPU */126 uint32_t TBD; /* XXX Fix for this CPU */ 127 127 } CPU_Interrupt_frame; 128 128 … … 162 162 void (*idle_task)( void ); 163 163 boolean do_zero_of_workspace; 164 u nsigned32idle_task_stack_size;165 u nsigned32interrupt_stack_size;166 u nsigned32extra_mpci_receive_server_stack;167 void * (*stack_allocate_hook)( u nsigned32);164 uint32_t idle_task_stack_size; 165 uint32_t interrupt_stack_size; 166 uint32_t extra_mpci_receive_server_stack; 167 void * (*stack_allocate_hook)( uint32_t ); 168 168 void (*stack_free_hook)( void* ); 169 169 /* end of fields required on all CPUs */ … … 268 268 #define _CPU_ISR_Set_level( newlevel ) \ 269 269 { \ 270 u nsigned32_mask = 0; \271 u nsigned32_level = (newlevel); \270 uint32_t _mask = 0; \ 271 uint32_t _level = (newlevel); \ 272 272 \ 273 273 __asm__ volatile ( "ldconst 0x1f0000,%0; \ … … 277 277 } 278 278 279 u nsigned32_CPU_ISR_Get_level( void );279 uint32_t _CPU_ISR_Get_level( void ); 280 280 281 281 /* ISR handler section macros */ … … 294 294 _isr, _entry, _is_fp ) \ 295 295 { CPU_Call_frame *_texit_frame; \ 296 u nsigned32_mask; \297 u nsigned32_base_pc; \298 u nsigned32_stack_tmp; \296 uint32_t _mask; \ 297 uint32_t _base_pc; \ 298 uint32_t _stack_tmp; \ 299 299 void *_stack; \ 300 300 \ 301 _stack_tmp = (u nsigned32)(_stack_base) + CPU_STACK_ALIGNMENT; \301 _stack_tmp = (uint32_t )(_stack_base) + CPU_STACK_ALIGNMENT; \ 302 302 _stack_tmp &= ~(CPU_STACK_ALIGNMENT - 1); \ 303 303 _stack = (void *) _stack_tmp; \ … … 338 338 339 339 #define _CPU_Fatal_halt( _errorcode ) \ 340 { u nsigned32_mask, _level; \341 u nsigned32_error = (_errorcode); \340 { uint32_t _mask, _level; \ 341 uint32_t _error = (_errorcode); \ 342 342 \ 343 343 __asm__ volatile ( "ldconst 0x1f0000,%0 ; \ … … 362 362 363 363 #define _CPU_Bitfield_Find_first_bit( _value, _output ) \ 364 { u nsigned32_search = (_value); \364 { uint32_t _search = (_value); \ 365 365 \ 366 366 (_output) = 0; /* to prevent warnings */ \ … … 411 411 412 412 void _CPU_ISR_install_raw_handler( 413 u nsigned32vector,413 uint32_t vector, 414 414 proc_ptr new_handler, 415 415 proc_ptr *old_handler … … 423 423 424 424 void _CPU_ISR_install_vector( 425 u nsigned32vector,425 uint32_t vector, 426 426 proc_ptr new_handler, 427 427 proc_ptr *old_handler -
cpukit/score/cpu/mips/ChangeLog
re6aeabd rc346f33d 1 2004-03-30 Ralf Corsepius <ralf_corsepius@rtems.org> 2 3 * cpu.c, rtems/score/cpu.h: Convert to using c99 fixed size types. 4 1 5 2004-03-29 Ralf Corsepius <ralf_corsepius@rtems.org> 2 6 -
cpukit/score/cpu/mips/cpu.c
re6aeabd rc346f33d 94 94 */ 95 95 96 u nsigned32_CPU_ISR_Get_level( void )96 uint32_t _CPU_ISR_Get_level( void ) 97 97 { 98 98 unsigned int sr; … … 118 118 119 119 120 void _CPU_ISR_Set_level( u nsigned32new_level )120 void _CPU_ISR_Set_level( uint32_t new_level ) 121 121 { 122 122 unsigned int sr, srbits; … … 186 186 187 187 void _CPU_ISR_install_raw_handler( 188 u nsigned32vector,188 uint32_t vector, 189 189 proc_ptr new_handler, 190 190 proc_ptr *old_handler … … 217 217 218 218 void _CPU_ISR_install_vector( 219 u nsigned32vector,219 uint32_t vector, 220 220 proc_ptr new_handler, 221 221 proc_ptr *old_handler -
cpukit/score/cpu/mips/rtems/score/cpu.h
re6aeabd rc346f33d 358 358 /* WARNING: If this structure is modified, the constants in cpu.h must be updated. */ 359 359 #if __mips == 1 360 #define __MIPS_REGISTER_TYPE u nsigned32361 #define __MIPS_FPU_REGISTER_TYPE u nsigned32360 #define __MIPS_REGISTER_TYPE uint32_t 361 #define __MIPS_FPU_REGISTER_TYPE uint32_t 362 362 #elif __mips == 3 363 #define __MIPS_REGISTER_TYPE u nsigned64364 #define __MIPS_FPU_REGISTER_TYPE u nsigned64363 #define __MIPS_REGISTER_TYPE uint64_t 364 #define __MIPS_FPU_REGISTER_TYPE uint64_t 365 365 #else 366 366 #error "mips register size: unknown architecture level!!" … … 582 582 void (*idle_task)( void ); 583 583 boolean do_zero_of_workspace; 584 u nsigned32idle_task_stack_size;585 u nsigned32interrupt_stack_size;586 u nsigned32extra_mpci_receive_server_stack;587 void * (*stack_allocate_hook)( u nsigned32);584 uint32_t idle_task_stack_size; 585 uint32_t interrupt_stack_size; 586 uint32_t extra_mpci_receive_server_stack; 587 void * (*stack_allocate_hook)( uint32_t ); 588 588 void (*stack_free_hook)( void* ); 589 589 /* end of fields required on all CPUs */ 590 590 591 u nsigned32clicks_per_microsecond;591 uint32_t clicks_per_microsecond; 592 592 } rtems_cpu_table; 593 593 … … 684 684 */ 685 685 686 #define CPU_STACK_MINIMUM_SIZE (2048*sizeof(u nsigned32))686 #define CPU_STACK_MINIMUM_SIZE (2048*sizeof(uint32_t )) 687 687 688 688 … … 798 798 */ 799 799 800 u nsigned32_CPU_ISR_Get_level( void ); /* in cpu.c */801 802 void _CPU_ISR_Set_level( u nsigned32); /* in cpu.c */800 uint32_t _CPU_ISR_Get_level( void ); /* in cpu.c */ 801 802 void _CPU_ISR_Set_level( uint32_t ); /* in cpu.c */ 803 803 804 804 /* end of ISR handler macros */ … … 858 858 #define _CPU_Context_Initialize( _the_context, _stack_base, _size, _isr, _entry_point, _is_fp ) \ 859 859 { \ 860 u nsigned32_stack_tmp = \861 (u nsigned32)(_stack_base) + (_size) - CPU_STACK_ALIGNMENT; \862 u nsigned32_intlvl = _isr & 0xff; \860 uint32_t _stack_tmp = \ 861 (uint32_t )(_stack_base) + (_size) - CPU_STACK_ALIGNMENT; \ 862 uint32_t _intlvl = _isr & 0xff; \ 863 863 _stack_tmp &= ~(CPU_STACK_ALIGNMENT - 1); \ 864 864 (_the_context)->sp = _stack_tmp; \ 865 865 (_the_context)->fp = _stack_tmp; \ 866 (_the_context)->ra = (u nsigned64)_entry_point; \866 (_the_context)->ra = (uint64_t )_entry_point; \ 867 867 (_the_context)->c0_sr = ((_intlvl==0)?(0xFF00 | _INTON):( ((_intlvl<<9) & 0xfc00) | \ 868 868 0x300 | \ … … 1063 1063 1064 1064 void _CPU_ISR_install_raw_handler( 1065 u nsigned32vector,1065 uint32_t vector, 1066 1066 proc_ptr new_handler, 1067 1067 proc_ptr *old_handler … … 1075 1075 1076 1076 void _CPU_ISR_install_vector( 1077 u nsigned32vector,1077 uint32_t vector, 1078 1078 proc_ptr new_handler, 1079 1079 proc_ptr *old_handler … … 1170 1170 ) 1171 1171 { 1172 u nsigned32byte1, byte2, byte3, byte4, swapped;1172 uint32_t byte1, byte2, byte3, byte4, swapped; 1173 1173 1174 1174 byte4 = (value >> 24) & 0xff; -
cpukit/score/cpu/no_cpu/ChangeLog
re6aeabd rc346f33d 1 2004-03-30 Ralf Corsepius <ralf_corsepius@rtems.org> 2 3 * cpu.c, rtems/score/cpu.h: Convert to using c99 fixed size types. 4 1 5 2004-03-29 Ralf Corsepius <ralf_corsepius@rtems.org> 2 6 -
cpukit/score/cpu/no_cpu/cpu.c
re6aeabd rc346f33d 70 70 */ 71 71 72 u nsigned32_CPU_ISR_Get_level( void )72 uint32_t _CPU_ISR_Get_level( void ) 73 73 { 74 74 /* … … 89 89 90 90 void _CPU_ISR_install_raw_handler( 91 u nsigned32vector,91 uint32_t vector, 92 92 proc_ptr new_handler, 93 93 proc_ptr *old_handler … … 121 121 122 122 void _CPU_ISR_install_vector( 123 u nsigned32vector,123 uint32_t vector, 124 124 proc_ptr new_handler, 125 125 proc_ptr *old_handler -
cpukit/score/cpu/no_cpu/rtems/score/cpu.h
re6aeabd rc346f33d 409 409 410 410 typedef struct { 411 u nsigned32some_integer_register;412 u nsigned32some_system_register;411 uint32_t some_integer_register; 412 uint32_t some_system_register; 413 413 } Context_Control; 414 414 … … 418 418 419 419 typedef struct { 420 u nsigned32special_interrupt_register;420 uint32_t special_interrupt_register; 421 421 } CPU_Interrupt_frame; 422 422 … … 437 437 void (*idle_task)( void ); 438 438 boolean do_zero_of_workspace; 439 u nsigned32idle_task_stack_size;440 u nsigned32interrupt_stack_size;441 u nsigned32extra_mpci_receive_server_stack;442 void * (*stack_allocate_hook)( u nsigned32);439 uint32_t idle_task_stack_size; 440 uint32_t interrupt_stack_size; 441 uint32_t extra_mpci_receive_server_stack; 442 void * (*stack_allocate_hook)( uint32_t ); 443 443 void (*stack_free_hook)( void* ); 444 444 /* end of fields required on all CPUs */ … … 727 727 } 728 728 729 u nsigned32_CPU_ISR_Get_level( void );729 uint32_t _CPU_ISR_Get_level( void ); 730 730 731 731 /* end of ISR handler macros */ … … 983 983 984 984 void _CPU_ISR_install_raw_handler( 985 u nsigned32vector,985 uint32_t vector, 986 986 proc_ptr new_handler, 987 987 proc_ptr *old_handler … … 999 999 1000 1000 void _CPU_ISR_install_vector( 1001 u nsigned32vector,1001 uint32_t vector, 1002 1002 proc_ptr new_handler, 1003 1003 proc_ptr *old_handler … … 1122 1122 ) 1123 1123 { 1124 u nsigned32byte1, byte2, byte3, byte4, swapped;1124 uint32_t byte1, byte2, byte3, byte4, swapped; 1125 1125 1126 1126 byte4 = (value >> 24) & 0xff; -
cpukit/score/cpu/unix/ChangeLog
re6aeabd rc346f33d 1 2004-03-30 Ralf Corsepius <ralf_corsepius@rtems.org> 2 3 * cpu.c, rtems/score/cpu.h: Convert to using c99 fixed size types. 4 1 5 2004-03-29 Ralf Corsepius <ralf_corsepius@rtems.org> 2 6 -
cpukit/score/cpu/unix/cpu.c
re6aeabd rc346f33d 87 87 void _CPU_Initialize_vectors(void) 88 88 { 89 u nsigned32i;89 uint32_t i; 90 90 proc_ptr old_handler; 91 91 … … 195 195 196 196 { 197 extern u nsigned32_SYSTEM_ID;197 extern uint32_t _SYSTEM_ID; 198 198 199 199 _SYSTEM_ID = 0x20c; … … 255 255 */ 256 256 257 u nsigned32_CPU_ISR_Get_level( void )257 uint32_t _CPU_ISR_Get_level( void ) 258 258 { 259 259 sigset_t old_mask; … … 328 328 329 329 void _CPU_ISR_install_raw_handler( 330 u nsigned32vector,330 uint32_t vector, 331 331 proc_ptr new_handler, 332 332 proc_ptr *old_handler … … 354 354 355 355 void _CPU_ISR_install_vector( 356 u nsigned32vector,356 uint32_t vector, 357 357 proc_ptr new_handler, 358 358 proc_ptr *old_handler … … 461 461 void _CPU_Context_Initialize( 462 462 Context_Control *_the_context, 463 u nsigned32*_stack_base,464 u nsigned32_size,465 u nsigned32_new_level,463 uint32_t *_stack_base, 464 uint32_t _size, 465 uint32_t _new_level, 466 466 void *_entry_point, 467 467 boolean _is_fp 468 468 ) 469 469 { 470 u nsigned32*addr;471 u nsigned32jmp_addr;472 u nsigned32_stack_low; /* lowest "stack aligned" address */473 u nsigned32_stack_high; /* highest "stack aligned" address */474 u nsigned32_the_size;475 476 jmp_addr = (u nsigned32) _entry_point;470 uint32_t *addr; 471 uint32_t jmp_addr; 472 uint32_t _stack_low; /* lowest "stack aligned" address */ 473 uint32_t _stack_high; /* highest "stack aligned" address */ 474 uint32_t _the_size; 475 476 jmp_addr = (uint32_t ) _entry_point; 477 477 478 478 /* … … 482 482 */ 483 483 484 _stack_low = (u nsigned32)(_stack_base) + CPU_STACK_ALIGNMENT - 1;484 _stack_low = (uint32_t )(_stack_base) + CPU_STACK_ALIGNMENT - 1; 485 485 _stack_low &= ~(CPU_STACK_ALIGNMENT - 1); 486 486 487 _stack_high = (u nsigned32)(_stack_base) + _size;487 _stack_high = (uint32_t )(_stack_base) + _size; 488 488 _stack_high &= ~(CPU_STACK_ALIGNMENT - 1); 489 489 … … 504 504 _CPU_Context_Default_with_ISRs_disabled; 505 505 506 addr = (u nsigned32*)_the_context;506 addr = (uint32_t *)_the_context; 507 507 508 508 #if defined(__hppa__) 509 509 *(addr + RP_OFF) = jmp_addr; 510 *(addr + SP_OFF) = (u nsigned32)(_stack_low + CPU_FRAME_SIZE);510 *(addr + SP_OFF) = (uint32_t )(_stack_low + CPU_FRAME_SIZE); 511 511 512 512 /* … … 519 519 if (jmp_addr & 0x40000000) { 520 520 jmp_addr &= 0xfffffffc; 521 *(addr + RP_OFF) = *(u nsigned32*)jmp_addr;521 *(addr + RP_OFF) = *(uint32_t *)jmp_addr; 522 522 } 523 523 #elif defined(__sparc__) … … 531 531 532 532 *(addr + RP_OFF) = jmp_addr + ADDR_ADJ_OFFSET; 533 *(addr + SP_OFF) = (u nsigned32)(_stack_high - CPU_FRAME_SIZE);534 *(addr + FP_OFF) = (u nsigned32)(_stack_high);533 *(addr + SP_OFF) = (uint32_t )(_stack_high - CPU_FRAME_SIZE); 534 *(addr + FP_OFF) = (uint32_t )(_stack_high); 535 535 536 536 #elif defined(__i386__) … … 541 541 542 542 { 543 u nsigned32stack_ptr;543 uint32_t stack_ptr; 544 544 545 545 stack_ptr = _stack_high - CPU_FRAME_SIZE; … … 552 552 *(addr + RET_OFF) = jmp_addr; 553 553 554 addr = (u nsigned32*) stack_ptr;554 addr = (uint32_t *) stack_ptr; 555 555 556 556 addr[ 0 ] = jmp_addr; 557 addr[ 1 ] = (u nsigned32) stack_ptr;558 addr[ 2 ] = (u nsigned32) stack_ptr;557 addr[ 1 ] = (uint32_t ) stack_ptr; 558 addr[ 2 ] = (uint32_t ) stack_ptr; 559 559 } 560 560 … … 668 668 */ 669 669 670 u nsigned32_CPU_ISR_Disable_support(void)670 uint32_t _CPU_ISR_Disable_support(void) 671 671 { 672 672 int status; … … 694 694 695 695 void _CPU_ISR_Enable( 696 u nsigned32level696 uint32_t level 697 697 ) 698 698 { … … 724 724 { 725 725 extern void _Thread_Dispatch(void); 726 extern u nsigned32_Thread_Dispatch_disable_level;726 extern uint32_t _Thread_Dispatch_disable_level; 727 727 extern boolean _Context_Switch_necessary; 728 728 … … 834 834 */ 835 835 836 void _CPU_Fatal_error(u nsigned32error)836 void _CPU_Fatal_error(uint32_t error) 837 837 { 838 838 setitimer(ITIMER_REAL, 0, 0); … … 951 951 952 952 void _CPU_SHM_Init( 953 u nsigned32maximum_nodes,953 uint32_t maximum_nodes, 954 954 boolean is_master_node, 955 955 void **shm_address, 956 u nsigned32*shm_length956 uint32_t *shm_length 957 957 ) 958 958 { -
cpukit/score/cpu/unix/rtems/score/cpu.h
re6aeabd rc346f33d 467 467 * 468 468 * jmp_buf regs; 469 * u nsigned32isr_level;469 * uint32_t isr_level; 470 470 * 471 471 * Doing it this way avoids conflicts between the native stuff and the … … 507 507 void (*idle_task)( void ); 508 508 boolean do_zero_of_workspace; 509 u nsigned32idle_task_stack_size;510 u nsigned32interrupt_stack_size;511 u nsigned32extra_mpci_receive_server_stack;512 void * (*stack_allocate_hook)( u nsigned32);509 uint32_t idle_task_stack_size; 510 uint32_t interrupt_stack_size; 511 uint32_t extra_mpci_receive_server_stack; 512 void * (*stack_allocate_hook)( uint32_t ); 513 513 void (*stack_free_hook)( void* ); 514 514 /* end of required fields */ … … 683 683 */ 684 684 685 extern u nsigned32_CPU_ISR_Disable_support(void);685 extern uint32_t _CPU_ISR_Disable_support(void); 686 686 687 687 #define _CPU_ISR_Disable( _level ) \ … … 696 696 */ 697 697 698 void _CPU_ISR_Enable(u nsigned32level);698 void _CPU_ISR_Enable(uint32_t level); 699 699 700 700 /* … … 707 707 #define _CPU_ISR_Flash( _level ) \ 708 708 do { \ 709 register u nsigned32_ignored = 0; \709 register uint32_t _ignored = 0; \ 710 710 _CPU_ISR_Enable( (_level) ); \ 711 711 _CPU_ISR_Disable( _ignored ); \ … … 729 729 } 730 730 731 u nsigned32_CPU_ISR_Get_level( void );731 uint32_t _CPU_ISR_Get_level( void ); 732 732 733 733 /* end of ISR handler macros */ … … 790 790 extern void _CPU_Context_Initialize( 791 791 Context_Control *_the_context, 792 u nsigned32*_stack_base,793 u nsigned32_size,794 u nsigned32_new_level,792 uint32_t *_stack_base, 793 uint32_t _size, 794 uint32_t _new_level, 795 795 void *_entry_point, 796 796 boolean _is_fp … … 911 911 912 912 void _CPU_ISR_install_raw_handler( 913 u nsigned32vector,913 uint32_t vector, 914 914 proc_ptr new_handler, 915 915 proc_ptr *old_handler … … 923 923 924 924 void _CPU_ISR_install_vector( 925 u nsigned32vector,925 uint32_t vector, 926 926 proc_ptr new_handler, 927 927 proc_ptr *old_handler … … 996 996 997 997 void _CPU_ISR_Set_signal_level( 998 u nsigned32level998 uint32_t level 999 999 ); 1000 1000 1001 1001 void _CPU_Fatal_error( 1002 u nsigned32_error1002 uint32_t _error 1003 1003 ); 1004 1004 … … 1027 1027 ) 1028 1028 { 1029 u nsigned32byte1, byte2, byte3, byte4, swapped;1029 uint32_t byte1, byte2, byte3, byte4, swapped; 1030 1030 1031 1031 byte4 = (value >> 24) & 0xff; … … 1082 1082 1083 1083 void _CPU_SHM_Init( 1084 u nsigned32maximum_nodes,1084 uint32_t maximum_nodes, 1085 1085 boolean is_master_node, 1086 1086 void **shm_address, 1087 u nsigned32*shm_length1087 uint32_t *shm_length 1088 1088 ); 1089 1089
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