Changeset c2b7528 in rtems


Ignore:
Timestamp:
Dec 23, 2013, 7:03:25 PM (5 years ago)
Author:
Daniel Ramirez <javamonn@…>
Branches:
4.11, master
Children:
2d1bdc8
Parents:
52943a2
git-author:
Daniel Ramirez <javamonn@…> (12/23/13 19:03:25)
git-committer:
Gedare Bloom <gedare@…> (12/23/13 20:06:12)
Message:

mips/shared: added new doxygen

Location:
c/src/lib/libbsp/mips/shared
Files:
1 added
5 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/mips/shared/gdbstub/gdb_if.h

    r52943a2 rc2b7528  
     1/**
     2 * @file
     3 * @ingroup mips_gdb
     4 * @brief Definition of the interface between stub and gdb
     5 */
     6
    17/*
    28 * gdb_if.h - definition of the interface between the stub and gdb
     
    1319 */
    1420
     21/**
     22 * @defgroup mips_gdb GDB Interface
     23 * @ingroup mips_shared
     24 * @brief GDB Interface
     25 * @{
     26 */
     27
    1528#ifndef _GDB_IF_H
    1629#define _GDB_IF_H
    1730
    18 /* Max number of threads in qM response */
     31/** @brief Max number of threads in qM response */
    1932#define QM_MAX_THREADS (20)
    2033
     
    2538};
    2639
    27 /*
    28  *  Prototypes
     40/**
     41 * @name Prototypes
     42 * @{
    2943 */
    3044
     
    7185);
    7286
    73 /*
    74  * MIPS registers, numbered in the order in which gdb expects to see them.
     87/** @} */
     88
     89/**
     90 * @name MIPS registers
     91 * @brief Numbered in the order in which gdb expects to see them.
     92 * @{
    7593 */
     94
    7695#define ZERO            0
    7796#define AT              1
     
    158177#define NUM_REGS        72
    159178
     179/** @} */
     180
    160181void mips_gdb_stub_install(int enableThreads) ;
    161182
     
    169190int gdbstub_add_memsegment(unsigned,unsigned,int);
    170191
     192/** @} */
     193
    171194#endif /* _GDB_IF_H */
  • c/src/lib/libbsp/mips/shared/gdbstub/memlimits.h

    r52943a2 rc2b7528  
     1/**
     2 * @file
     3 * @ingroup mips_limits
     4 * @brief Definition of machine and system dependent address limits.
     5 */
     6
    17/*
    28 * limits.h - definition of machine & system dependent address limits
     
    4652 */
    4753
     54/**
     55 * @defgroup mips_limits Address Limits
     56 * @ingroup mips_shared
     57 * @brief Address Limits
     58 */
     59
     60
    4861/*
    4962#define K0_LIMIT_FOR_READ  (K0BASE+0x18000000)
  • c/src/lib/libbsp/mips/shared/gdbstub/mips_opcode.h

    r52943a2 rc2b7528  
    1 /*-
     1/**
     2 * @file
     3 * @ingroup
     4 * @brief Instruction formats and opcode values for MIPS
     5 */
     6
     7/*
    28 * Copyright (c) 1992 The Regents of the University of California.
    39 * All rights reserved.
     
    4652#define _MIPS_OPCODE_H
    4753
    48 /*
    49  * Define the instruction formats.
    50  */
     54/**
     55 * @defgroup mips_ops MIPS Opcodes
     56 * @ingroup mips_shared
     57 * @brief MIPS Instruction Formats and Opcode Values
     58 * @{
     59 */
     60
     61/**
     62 * @name Instruction formats
     63 * @{
     64 */
     65
    5166typedef union {
    5267    unsigned word;
     
    117132} InstFmt;
    118133
    119 /*
    120  * Values for the 'op' field.
    121  */
     134/** @} */
     135
     136/**
     137 * @name 'op' field values
     138 * @{
     139 */
     140
    122141#define OP_SPECIAL      000
    123142#define OP_REGIMM       001
     
    185204#define OP_SD           077
    186205
    187 /*
    188  * Values for the 'func' field when 'op' == OP_SPECIAL.
    189  */
     206/**
     207 * @name 'func' field values when 'op' == OP_SPECIAL.
     208 * @{
     209 */
     210
    190211#define OP_SLL          000
    191212#define OP_SRL          002
     
    248269#define OP_DSRA32       077
    249270
    250 /*
    251  * Values for the 'func' field when 'op' == OP_REGIMM.
    252  */
     271/** @} */
     272
     273/**
     274 * 'func' field values when 'op' == OP_REGIMM.
     275 * @{
     276 */
     277
    253278#define OP_BLTZ         000
    254279#define OP_BGEZ         001
     
    268293#define OP_BGEZALL      023
    269294
    270 /*
    271  * Values for the 'rs' field when 'op' == OP_COPz.
    272  */
     295/** @} */
     296
     297/**
     298 * @name 'rs' field values when 'op' == OP_COPz.
     299 * @{
     300 */
     301
    273302#define OP_MF           000
    274303#define OP_DMF          001
     
    279308#define OP_BC           010
    280309
    281 /*
    282  * Values for the 'rt' field when 'op' == OP_COPz and 'rt' == OP_BC.
    283  */
     310/** @} */
     311
     312/**
     313 * @name 'rt' field values when 'op' == OP_COPz and 'rt' == OP_BC.
     314 * @{
     315 */
     316
    284317#define COPz_BCF        0x00
    285318#define COPz_BCT        0x01
     
    287320#define COPz_BCTL       0x03
    288321
    289 /*
    290  * Instructions with specal significance to debuggers.
    291  */
    292 #define BREAK_INSTR     0x0000000d      /* instruction code for break */
    293 #define NOP_INSTR       0x00000000      /* instruction code for no-op */
     322/** @} */
     323
     324/**
     325 * @name Instructions with specal significance to debuggers.
     326 * @{
     327 */
     328
     329#define BREAK_INSTR     0x0000000d      ///< @brief instruction code for break
     330#define NOP_INSTR       0x00000000      ///< @brief instruction code for no-op
     331
     332/** @} */
     333
     334/** @} */
    294335
    295336#endif  /* _MIPS_OPCODE_H */
  • c/src/lib/libbsp/mips/shared/irq/i8259.h

    r52943a2 rc2b7528  
     1/**
     2 * @file
     3 * @ingroup mips_i8259_irq
     4 * @brief Data structure and functions used to control i8259 chip.
     5 */
     6
    17/* irq.h
    28 *
     
    2026#define I8259_H
    2127
    22 /*
    23  * 8259 edge/level control definitions at VIA
    24  */
     28/**
     29 * @defgroup mips_i8259_irq i8259 Chip Support
     30 * @ingroup mips_shared
     31 * @brief i8259 Chip Support
     32 * @{
     33 */
     34
     35/**
     36 * @name 8259 edge/level control definitions at VIA
     37 * @{
     38 */
     39
    2540#if 1
    2641#define ISA8259_M_ELCR          0x4d0
     
    4560#define ELCRM_INT0_LVL          0x1
    4661
    47 /*
    48  * PIC's command and mask registers
    49  */
    50 #define PIC_MASTER_COMMAND_IO_PORT              0x20    /* Master PIC command register */
    51 #define PIC_SLAVE_COMMAND_IO_PORT               0xa0    /* Slave PIC command register */
    52 #define PIC_MASTER_IMR_IO_PORT                  0x21    /* Master PIC Interrupt Mask Register */
    53 #define PIC_SLAVE_IMR_IO_PORT                   0xa1    /* Slave PIC Interrupt Mask Register */
    54 
    55 /*
    56  * Command for specific EOI (End Of Interrupt): Interrupt acknowledge
    57  */
    58 #define PIC_EOSI        0x60    /* End of Specific Interrupt (EOSI) */
    59 #define SLAVE_PIC_EOSI  0x62    /* End of Specific Interrupt (EOSI) for cascade */
    60 #define PIC_EOI         0x20    /* Generic End of Interrupt (EOI) */
     62/** @} */
     63
     64/**
     65 * @name PIC's command and mask registers
     66 * @{
     67 */
     68
     69#define PIC_MASTER_COMMAND_IO_PORT              0x20    ///< @brief Master PIC command register */
     70#define PIC_SLAVE_COMMAND_IO_PORT               0xa0    ///< @brief Slave PIC command register */
     71#define PIC_MASTER_IMR_IO_PORT                  0x21    ///< @brief Master PIC Interrupt Mask Register */
     72#define PIC_SLAVE_IMR_IO_PORT                   0xa1    ///< @brief Slave PIC Interrupt Mask Register */
     73
     74/** @} */
     75
     76/**
     77 * @name Command for specific EOI (End Of Interrupt): Interrupt acknowledge
     78 * @{
     79 */
     80
     81#define PIC_EOSI        0x60    ///< @brief End of Specific Interrupt (EOSI) */
     82#define SLAVE_PIC_EOSI  0x62    ///< @brief End of Specific Interrupt (EOSI) for cascade */
     83#define PIC_EOI         0x20    ///< @brief Generic End of Interrupt (EOI) */
     84
     85/** @} */
    6186
    6287#ifndef ASM
     
    7095 */
    7196#if 0
    72 /*
    73  * ISA IRQ handler related definitions
    74  */
     97
     98/**
     99 * @name ISA IRQ handler related definitions
     100 * @{
     101 */
     102
    75103#define BSP_ISA_IRQ_NUMBER              (16)
    76104#define BSP_ISA_IRQ_LOWEST_OFFSET       (0)
    77105#define BSP_ISA_IRQ_MAX_OFFSET          (BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER - 1)
     106
     107/** @} */
    78108
    79109#ifndef qemu
     
    102132#define BSP_MISC_IRQ_LOWEST_OFFSET      (BSP_PROCESSOR_IRQ_MAX_OFFSET + 1)
    103133#define BSP_MISC_IRQ_MAX_OFFSET         (BSP_MISC_IRQ_LOWEST_OFFSET + BSP_MISC_IRQ_NUMBER - 1)
    104 /*
    105  * Summary
    106  */
     134
     135/**
     136 * @name Summary
     137 * @{
     138 */
     139
    107140#define BSP_IRQ_NUMBER                  (BSP_MISC_IRQ_MAX_OFFSET + 1)
    108141#define BSP_LOWEST_OFFSET               (BSP_ISA_IRQ_LOWEST_OFFSET)
    109142#define BSP_MAX_OFFSET                  (BSP_MISC_IRQ_MAX_OFFSET)
    110 /*
    111  * Some ISA IRQ symbolic name definition
    112  */
     143
     144/** @} */
     145
     146/**
     147 * @name Some ISA IRQ symbolic name definition
     148 * @{
     149 */
     150
    113151#define BSP_ISA_PERIODIC_TIMER          (0)
    114152#define BSP_ISA_KEYBOARD                (1)
     
    117155#define BSP_ISA_RT_TIMER1               (8)
    118156#define BSP_ISA_RT_TIMER3               (10)
    119 /*
    120  * Some PCI IRQ symbolic name definition
    121  */
     157
     158/** @} */
     159
     160/**
     161 * @name Some PCI IRQ symbolic name definition
     162 * @{
     163 */
     164
    122165#define BSP_PCI_IRQ0                    (BSP_PCI_IRQ_LOWEST_OFFSET)
    123166#if     BSP_PCI_IRQ_NUMBER > 0
    124167#define BSP_PCI_ISA_BRIDGE_IRQ          (BSP_PCI_IRQ0)
    125168#endif
     169
     170/** @} */
    126171
    127172#if defined(mvme2100)
     
    143188#endif
    144189
    145 /*
    146  * Some Processor execption handled as RTEMS IRQ symbolic name definition
     190/**
     191 * @brief Some Processor execption handled as RTEMS IRQ symbolic name definition
    147192 */
    148193#define BSP_DECREMENTER                 (BSP_PROCESSOR_IRQ_LOWEST_OFFSET)
    149194#endif
    150195
    151 /*
    152  * Type definition for RTEMS managed interrupts
    153  */
     196/**
     197 * @name Type definition for RTEMS managed interrupts
     198 * @{
     199 */
     200
    154201typedef unsigned short rtems_i8259_masks;
    155202extern  volatile rtems_i8259_masks i8259s_cache;
     203
     204/** @} */
    156205
    157206/*-------------------------------------------------------------------------+
     
    161210 * ------------------------ Intel 8259 (or emulation) Mngt Routines -------
    162211 */
     212
     213/**
     214 * @name Function Prototypes
     215 * @{
     216 */
     217
    163218void BSP_i8259s_init(void);
    164219
    165 /*
    166  * function to disable a particular irq at 8259 level. After calling
    167  * this function, even if the device asserts the interrupt line it will
    168  * not be propagated further to the processor
    169  *
    170  * RETURNS: 1/0 if the interrupt was enabled/disabled originally or
    171  *          a value < 0 on error.
     220/**
     221 * @brief function to disable a particular irq at 8259 level.
     222 *
     223 * After calling this function, even if the device asserts the interrupt
     224 * line it will not be propagated further to the processor.
     225 *
     226 * @retval 1 the interrupt was enabled originally
     227 * @retval 0 the interrupt was disabled originally
     228 * @retval <0 error
    172229 */
    173230int BSP_irq_disable_at_i8259s        (const rtems_irq_number irqLine);
    174 /*
    175  * function to enable a particular irq at 8259 level. After calling
    176  * this function, if the device asserts the interrupt line it will
    177  * be propagated further to the processor
     231
     232/**
     233 * @brief function to enable a particular irq at 8259 level.
     234 *
     235 * After calling this function, if the device asserts the interrupt line
     236 * it will be propagated further to the processor.
    178237 */
    179238int BSP_irq_enable_at_i8259s            (const rtems_irq_number irqLine);
    180 /*
    181  * function to acknowledge a particular irq at 8259 level. After calling
    182  * this function, if a device asserts an enabled interrupt line it will
    183  * be propagated further to the processor. Mainly usefull for people
    184  * writing raw handlers as this is automagically done for RTEMS managed
     239
     240/**
     241 * @brief function to acknowledge a particular irq at 8259 level.
     242 *
     243 * After calling this function, if a device asserts an enabled interrupt
     244 * line it will be propagated further to the processor. Mainly useful for
     245 * people writing raw handlers as this is automagically done for RTEMS managed
    185246 * handlers.
    186247 */
    187248int BSP_irq_ack_at_i8259s               (const rtems_irq_number irqLine);
    188 /*
    189  * function to check if a particular irq is enabled at 8259 level. After calling
     249
     250/**
     251 * @brief function to check if a particular irq is enabled at 8259 level.
    190252 */
    191253int BSP_irq_enabled_at_i8259s           (const rtems_irq_number irqLine);
     
    196258extern void BSP_i8259s_init(void);
    197259
     260/** @} */
     261
     262/** @} */
     263
    198264#ifdef __cplusplus
    199265};
  • c/src/lib/libbsp/mips/shared/liblnk/regs.h

    r52943a2 rc2b7528  
     1/**
     2 * @file
     3 * @ingroup mips_regs
     4 * @brief Standard MIPS register names.
     5 */
     6
    17/*
    28 * regs.S -- standard MIPS register names.
     
    1521 */
    1622
    17 /* Standard MIPS register names: */
     23/**
     24 * @defgroup mips_regs MIPS Registers
     25 * @ingroup mips_shared
     26 * @brief MIPS Registers
     27 * @{
     28 */
     29
     30/**
     31 * @name Standard MIPS register names:
     32 * @{
     33 */
     34
    1835#define zero    $0
    1936#define z0      $0
     
    4259#define t8      $24
    4360#define t9      $25
    44 #define k0      $26     /* kernel private register 0 */
    45 #define k1      $27     /* kernel private register 1 */
    46 #define gp      $28     /* global data pointer */
    47 #define sp      $29     /* stack-pointer */
    48 #define fp      $30     /* frame-pointer */
    49 #define ra      $31     /* return address */
    50 #define pc      $pc     /* pc, used on mips16 */
     61#define k0      $26     ///< @brief kernel private register 0 */
     62#define k1      $27     ///< @brief kernel private register 1 */
     63#define gp      $28     ///< @brief global data pointer */
     64#define sp      $29     ///< @brief stack-pointer */
     65#define fp      $30     ///< @brief frame-pointer */
     66#define ra      $31     ///< @brief return address */
     67#define pc      $pc     ///< @brief pc, used on mips16 */
    5168
    5269#define fp0     $f0
    5370#define fp1     $f1
    5471
    55 /* Useful memory constants: */
     72/** @} */
     73
     74/**
     75 * @name Useful memory constants:
     76 * @{
     77 */
     78
    5679#define K0BASE          0x80000000
    5780#ifndef __mips64
     
    6184#endif
    6285
     86/** @} */
     87
    6388#define PHYS_TO_K1(a)   ((unsigned)(a) | K1BASE)
    6489
    65 /* Standard Co-Processor 0 register numbers: */
    66 #define C0_COUNT        $9              /* Count Register */
    67 #define C0_SR           $12             /* Status Register */
    68 #define C0_CAUSE        $13             /* last exception description */
    69 #define C0_EPC          $14             /* Exception error address */
    70 #define C0_CONFIG       $16             /* CPU configuration */
     90/**
     91 * @name Standard Co-Processor 0 register numbers:
     92 * @{
     93 */
    7194
    72 /* Standard Status Register bitmasks: */
    73 #define SR_CU1          0x20000000      /* Mark CP1 as usable */
    74 #define SR_FR           0x04000000      /* Enable MIPS III FP registers */
    75 #define SR_BEV          0x00400000      /* Controls location of exception vectors */
    76 #define SR_PE           0x00100000      /* Mark soft reset (clear parity error) */
     95#define C0_COUNT        $9              ///< @brief Count Register */
     96#define C0_SR           $12             ///< @brief Status Register */
     97#define C0_CAUSE        $13             ///< @brief last exception description */
     98#define C0_EPC          $14             ///< @brief Exception error address */
     99#define C0_CONFIG       $16             ///< @brief CPU configuration */
    77100
    78 #define SR_KX           0x00000080      /* Kernel extended addressing enabled */
    79 #define SR_SX           0x00000040      /* Supervisor extended addressing enabled */
    80 #define SR_UX           0x00000020      /* User extended addressing enabled */
     101/** @} */
    81102
    82 /* Standard (R4000) cache operations. Taken from "MIPS R4000
    83    Microprocessor User's Manual" 2nd edition: */
     103/**
     104 * @name Standard Status Register bitmasks:
     105 * @{
     106 */
    84107
    85 #define CACHE_I         (0)     /* primary instruction */
    86 #define CACHE_D         (1)     /* primary data */
    87 #define CACHE_SI        (2)     /* secondary instruction */
    88 #define CACHE_SD        (3)     /* secondary data (or combined instruction/data) */
     108#define SR_CU1          0x20000000      ///< @brief Mark CP1 as usable */
     109#define SR_FR           0x04000000      ///< @brief Enable MIPS III FP registers */
     110#define SR_BEV          0x00400000      ///< @brief Controls location of exception vectors */
     111#define SR_PE           0x00100000      ///< @brief Mark soft reset (clear parity error) */
    89112
    90 #define INDEX_INVALIDATE                (0)     /* also encodes WRITEBACK if CACHE_D or CACHE_SD */
     113#define SR_KX           0x00000080      ///< @brief Kernel extended addressing enabled */
     114#define SR_SX           0x00000040      ///< @brief Supervisor extended addressing enabled */
     115#define SR_UX           0x00000020      ///< @brief User extended addressing enabled */
     116
     117/** @} */
     118
     119/**
     120 * @name Standard (R4000) cache operations.
     121 * @brief Taken from "MIPS R4000 Microprocessor User's Manual" 2nd edition:
     122 * @{
     123 */
     124
     125#define CACHE_I         (0)     ///< @brief primary instruction */
     126#define CACHE_D         (1)     ///< @brief primary data */
     127#define CACHE_SI        (2)     ///< @brief secondary instruction */
     128#define CACHE_SD        (3)     ///< @brief secondary data (or combined instruction/data) */
     129
     130#define INDEX_INVALIDATE                (0)     ///< @brief also encodes WRITEBACK if CACHE_D or CACHE_SD */
    91131#define INDEX_LOAD_TAG                  (1)
    92132#define INDEX_STORE_TAG                 (2)
    93 #define CREATE_DIRTY_EXCLUSIVE          (3)     /* CACHE_D and CACHE_SD only */
     133#define CREATE_DIRTY_EXCLUSIVE          (3)     ///< @brief CACHE_D and CACHE_SD only */
    94134#define HIT_INVALIDATE                  (4)
    95 #define CACHE_FILL                      (5)     /* CACHE_I only */
    96 #define HIT_WRITEBACK_INVALIDATE        (5)     /* CACHE_D and CACHE_SD only */
    97 #define HIT_WRITEBACK                   (6)     /* CACHE_I, CACHE_D and CACHE_SD only */
    98 #define HIT_SET_VIRTUAL                 (7)     /* CACHE_SI and CACHE_SD only */
     135#define CACHE_FILL                      (5)     ///< @brief CACHE_I only */
     136#define HIT_WRITEBACK_INVALIDATE        (5)     ///< @brief CACHE_D and CACHE_SD only */
     137#define HIT_WRITEBACK                   (6)     ///< @brief CACHE_I, CACHE_D and CACHE_SD only */
     138#define HIT_SET_VIRTUAL                 (7)     ///< @brief CACHE_SI and CACHE_SD only */
    99139
    100140#define BUILD_CACHE_OP(o,c)             (((o) << 2) | (c))
    101141
    102 /* Individual cache operations: */
     142/** @} */
     143
     144/**
     145 * @name Individual cache operations:
     146 * @{
     147 */
     148
    103149#define INDEX_INVALIDATE_I              BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_I)
    104150#define INDEX_WRITEBACK_INVALIDATE_D    BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_D)
     
    135181#define HIT_SET_VIRTUAL_SD              BUILD_CACHE_OP(HIT_SET_VIRTUAL,CACHE_SD)
    136182
     183/** @} */
     184
     185/** @} */
     186
    137187/*> EOF regs.S <*/
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