Changeset c2463d9 in rtems


Ignore:
Timestamp:
Apr 19, 1999, 9:02:31 PM (22 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, 5, master
Children:
6313537
Parents:
338502f
Message:

Intel i960HA support submitted by Jimen Ching <jimen@…>
based on 3.6.0. It was very lucky that this went in as well as it
did.

Files:
4 edited

Legend:

Unmodified
Added
Removed

  • c/src/exec/score/cpu/i960/rtems/score/cpu.h

    r338502f rc2463d9  
    6868#define CPU_PROVIDES_IDLE_THREAD_BODY    FALSE
    6969#define CPU_STACK_GROWS_UP               TRUE
    70 #define CPU_STRUCTURE_ALIGNMENT          __attribute__ ((aligned (16)))
     70#define CPU_STRUCTURE_ALIGNMENT          /* __attribute__ ((aligned (16))) */
    7171
    7272/*
    … …  
    170170  /* end of fields required on all CPUs */
    171171
    172 #if defined(__i960CA__) || defined(__i960_CA__) || defined(__i960CA)
    173   i960ca_PRCB *Prcb;
    174 #endif
     172  i960_PRCB *Prcb;
    175173}   rtems_cpu_table;
    176174

  • c/src/exec/score/cpu/i960/rtems/score/i960.h

    r338502f rc2463d9  
    3636
    3737#define CPU_MODEL_NAME  "i960ca"
     38#define I960_HAS_FPU 0
     39
     40#elif defined(i960ha)
     41
     42#define CPU_MODEL_NAME  "i960ha"
    3843#define I960_HAS_FPU 0
    3944
    … …  
    95100  unsigned int mcon15;            /* memory region 15 configuration */
    96101                            /* Control Group 6 */
     102  unsigned int reserved;          /* reserved */
    97103  unsigned int bpcon;             /* breakpoint control */
    98104  unsigned int tc;                /* trace control */
    99105  unsigned int bcon;              /* bus configuration control */
    100   unsigned int reserved;          /* reserved */
    101106}   i960ca_control_table;
    102107 
    … …  
    118123  unsigned int     reg_cache_cfg; /* register cache configuration word */
    119124}   i960ca_PRCB;
    120  
     125
     126typedef i960ca_control_table i960_control_table;
     127typedef i960ca_PRCB i960_PRCB;
     128
     129#elif defined(__i960HA__) || defined(__i960_HA__) || defined(__i960HA)
     130
     131/* i960HA control structures */
     132
     133/* Intel i960HA Control Table */
     134
     135typedef struct {
     136                            /* Control Group 0 */
     137  unsigned int ipb0;              /* IP breakpoint 0 */
     138  unsigned int ipb1;              /* IP breakpoint 1 */
     139  unsigned int dab0;              /* data address breakpoint 0 */
     140  unsigned int dab1;              /* data address breakpoint 1 */
     141                            /* Control Group 1 */
     142  unsigned int imap0;             /* interrupt map 0 */
     143  unsigned int imap1;             /* interrupt map 1 */
     144  unsigned int imap2;             /* interrupt map 2 */
     145  unsigned int icon;              /* interrupt control */
     146                            /* Control Group 2 */
     147  unsigned int mcon0;             /* memory region 0 configuration */
     148  unsigned int mcon1;             /* memory region 1 configuration */
     149  unsigned int mcon2;             /* memory region 2 configuration */
     150  unsigned int mcon3;             /* memory region 3 configuration */
     151                            /* Control Group 3 */
     152  unsigned int mcon4;             /* memory region 4 configuration */
     153  unsigned int mcon5;             /* memory region 5 configuration */
     154  unsigned int mcon6;             /* memory region 6 configuration */
     155  unsigned int mcon7;             /* memory region 7 configuration */
     156                            /* Control Group 4 */
     157  unsigned int mcon8;             /* memory region 8 configuration */
     158  unsigned int mcon9;             /* memory region 9 configuration */
     159  unsigned int mcon10;            /* memory region 10 configuration */
     160  unsigned int mcon11;            /* memory region 11 configuration */
     161                            /* Control Group 5 */
     162  unsigned int mcon12;            /* memory region 12 configuration */
     163  unsigned int mcon13;            /* memory region 13 configuration */
     164  unsigned int mcon14;            /* memory region 14 configuration */
     165  unsigned int mcon15;            /* memory region 15 configuration */
     166                            /* Control Group 6 */
     167  unsigned int reserved;          /* reserved */
     168  unsigned int bpcon;             /* breakpoint control */
     169  unsigned int tc;                /* trace control */
     170  unsigned int bcon;              /* bus configuration control */
     171}   i960ha_control_table;
     172
     173/* Intel i960HA Processor Control Block */
     174
     175typedef struct {
     176  unsigned int    *fault_tbl;     /* fault table base address */
     177  i960ha_control_table
     178                  *control_tbl;   /* control table base address */
     179  unsigned int     initial_ac;    /* AC register initial value */
     180  unsigned int     fault_config;  /* fault configuration word */
     181  void           **intr_tbl;      /* interrupt table base address */
     182  void            *sys_proc_tbl;  /* system procedure table
     183                                     base address */
     184  unsigned int     reserved;      /* reserved */
     185  unsigned int    *intr_stack;    /* interrupt stack pointer */
     186  unsigned int     ins_cache_cfg; /* instruction cache
     187                                     configuration word */
     188  unsigned int     reg_cache_cfg; /* register cache configuration word */
     189}   i960ha_PRCB;
     190
     191typedef i960ha_control_table i960_control_table;
     192typedef i960ha_PRCB i960_PRCB;
     193
    121194#endif
    122195

  • cpukit/score/cpu/i960/rtems/score/cpu.h

    r338502f rc2463d9  
    6868#define CPU_PROVIDES_IDLE_THREAD_BODY    FALSE
    6969#define CPU_STACK_GROWS_UP               TRUE
    70 #define CPU_STRUCTURE_ALIGNMENT          __attribute__ ((aligned (16)))
     70#define CPU_STRUCTURE_ALIGNMENT          /* __attribute__ ((aligned (16))) */
    7171
    7272/*
    … …  
    170170  /* end of fields required on all CPUs */
    171171
    172 #if defined(__i960CA__) || defined(__i960_CA__) || defined(__i960CA)
    173   i960ca_PRCB *Prcb;
    174 #endif
     172  i960_PRCB *Prcb;
    175173}   rtems_cpu_table;
    176174

  • cpukit/score/cpu/i960/rtems/score/i960.h

    r338502f rc2463d9  
    3636
    3737#define CPU_MODEL_NAME  "i960ca"
     38#define I960_HAS_FPU 0
     39
     40#elif defined(i960ha)
     41
     42#define CPU_MODEL_NAME  "i960ha"
    3843#define I960_HAS_FPU 0
    3944
    … …  
    95100  unsigned int mcon15;            /* memory region 15 configuration */
    96101                            /* Control Group 6 */
     102  unsigned int reserved;          /* reserved */
    97103  unsigned int bpcon;             /* breakpoint control */
    98104  unsigned int tc;                /* trace control */
    99105  unsigned int bcon;              /* bus configuration control */
    100   unsigned int reserved;          /* reserved */
    101106}   i960ca_control_table;
    102107 
    … …  
    118123  unsigned int     reg_cache_cfg; /* register cache configuration word */
    119124}   i960ca_PRCB;
    120  
     125
     126typedef i960ca_control_table i960_control_table;
     127typedef i960ca_PRCB i960_PRCB;
     128
     129#elif defined(__i960HA__) || defined(__i960_HA__) || defined(__i960HA)
     130
     131/* i960HA control structures */
     132
     133/* Intel i960HA Control Table */
     134
     135typedef struct {
     136                            /* Control Group 0 */
     137  unsigned int ipb0;              /* IP breakpoint 0 */
     138  unsigned int ipb1;              /* IP breakpoint 1 */
     139  unsigned int dab0;              /* data address breakpoint 0 */
     140  unsigned int dab1;              /* data address breakpoint 1 */
     141                            /* Control Group 1 */
     142  unsigned int imap0;             /* interrupt map 0 */
     143  unsigned int imap1;             /* interrupt map 1 */
     144  unsigned int imap2;             /* interrupt map 2 */
     145  unsigned int icon;              /* interrupt control */
     146                            /* Control Group 2 */
     147  unsigned int mcon0;             /* memory region 0 configuration */
     148  unsigned int mcon1;             /* memory region 1 configuration */
     149  unsigned int mcon2;             /* memory region 2 configuration */
     150  unsigned int mcon3;             /* memory region 3 configuration */
     151                            /* Control Group 3 */
     152  unsigned int mcon4;             /* memory region 4 configuration */
     153  unsigned int mcon5;             /* memory region 5 configuration */
     154  unsigned int mcon6;             /* memory region 6 configuration */
     155  unsigned int mcon7;             /* memory region 7 configuration */
     156                            /* Control Group 4 */
     157  unsigned int mcon8;             /* memory region 8 configuration */
     158  unsigned int mcon9;             /* memory region 9 configuration */
     159  unsigned int mcon10;            /* memory region 10 configuration */
     160  unsigned int mcon11;            /* memory region 11 configuration */
     161                            /* Control Group 5 */
     162  unsigned int mcon12;            /* memory region 12 configuration */
     163  unsigned int mcon13;            /* memory region 13 configuration */
     164  unsigned int mcon14;            /* memory region 14 configuration */
     165  unsigned int mcon15;            /* memory region 15 configuration */
     166                            /* Control Group 6 */
     167  unsigned int reserved;          /* reserved */
     168  unsigned int bpcon;             /* breakpoint control */
     169  unsigned int tc;                /* trace control */
     170  unsigned int bcon;              /* bus configuration control */
     171}   i960ha_control_table;
     172
     173/* Intel i960HA Processor Control Block */
     174
     175typedef struct {
     176  unsigned int    *fault_tbl;     /* fault table base address */
     177  i960ha_control_table
     178                  *control_tbl;   /* control table base address */
     179  unsigned int     initial_ac;    /* AC register initial value */
     180  unsigned int     fault_config;  /* fault configuration word */
     181  void           **intr_tbl;      /* interrupt table base address */
     182  void            *sys_proc_tbl;  /* system procedure table
     183                                     base address */
     184  unsigned int     reserved;      /* reserved */
     185  unsigned int    *intr_stack;    /* interrupt stack pointer */
     186  unsigned int     ins_cache_cfg; /* instruction cache
     187                                     configuration word */
     188  unsigned int     reg_cache_cfg; /* register cache configuration word */
     189}   i960ha_PRCB;
     190
     191typedef i960ha_control_table i960_control_table;
     192typedef i960ha_PRCB i960_PRCB;
     193
    121194#endif
    122195
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